|
US5628021A
(en)
*
|
1992-12-31 |
1997-05-06 |
Seiko Epson Corporation |
System and method for assigning tags to control instruction processing in a superscalar processor
|
|
US5751995A
(en)
*
|
1994-01-04 |
1998-05-12 |
Intel Corporation |
Apparatus and method of maintaining processor ordering in a multiprocessor system which includes one or more processors that execute instructions speculatively
|
|
WO1996012231A1
(en)
|
1994-10-14 |
1996-04-25 |
Silicon Graphics, Inc. |
A translation buffer for detecting and preventing conflicting virtual addresses from being stored therein
|
|
JPH10509819A
(ja)
|
1994-10-14 |
1998-09-22 |
シリコン グラフィックス インク. |
インターリーブされるキャッシュメモリアレイのインデッキシングとマルチプレキシング
|
|
US5737749A
(en)
*
|
1996-05-20 |
1998-04-07 |
International Business Machines Corporation |
Method and system for dynamically sharing cache capacity in a microprocessor
|
|
US5872976A
(en)
*
|
1997-04-01 |
1999-02-16 |
Landmark Systems Corporation |
Client-based system for monitoring the performance of application programs
|
|
US6175899B1
(en)
*
|
1997-05-19 |
2001-01-16 |
International Business Machines Corporation |
Method for providing virtual atomicity in multi processor environment having access to multilevel caches
|
|
US6092156A
(en)
*
|
1997-11-05 |
2000-07-18 |
Unisys Corporation |
System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations
|
|
US7237093B1
(en)
|
1998-12-16 |
2007-06-26 |
Mips Technologies, Inc. |
Instruction fetching system in a multithreaded processor utilizing cache miss predictions to fetch instructions from multiple hardware streams
|
|
US6389449B1
(en)
*
|
1998-12-16 |
2002-05-14 |
Clearwater Networks, Inc. |
Interstream control and communications for multi-streaming digital processors
|
|
US7529907B2
(en)
|
1998-12-16 |
2009-05-05 |
Mips Technologies, Inc. |
Method and apparatus for improved computer load and store operations
|
|
US7020879B1
(en)
*
|
1998-12-16 |
2006-03-28 |
Mips Technologies, Inc. |
Interrupt and exception handling for multi-streaming digital processors
|
|
US7257814B1
(en)
|
1998-12-16 |
2007-08-14 |
Mips Technologies, Inc. |
Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors
|
|
US6341331B1
(en)
*
|
1999-10-01 |
2002-01-22 |
International Business Machines Corporation |
Method and system for managing a raid storage system with cache
|
|
US6591361B1
(en)
|
1999-12-28 |
2003-07-08 |
International Business Machines Corporation |
Method and apparatus for converting data into different ordinal types
|
|
US6701424B1
(en)
*
|
2000-04-07 |
2004-03-02 |
Nintendo Co., Ltd. |
Method and apparatus for efficient loading and storing of vectors
|
|
US6857061B1
(en)
|
2000-04-07 |
2005-02-15 |
Nintendo Co., Ltd. |
Method and apparatus for obtaining a scalar value directly from a vector register
|
|
US6859862B1
(en)
|
2000-04-07 |
2005-02-22 |
Nintendo Co., Ltd. |
Method and apparatus for software management of on-chip cache
|
|
DE60143896D1
(de)
|
2000-07-14 |
2011-03-03 |
Mips Tech Inc |
Anweisungsabruf und -absendung in einem multi-thread-system
|
|
US7406554B1
(en)
*
|
2000-07-20 |
2008-07-29 |
Silicon Graphics, Inc. |
Queue circuit and method for memory arbitration employing same
|
|
US7181600B1
(en)
|
2001-08-02 |
2007-02-20 |
Mips Technologies, Inc. |
Read-only access to CPO registers
|
|
US7185183B1
(en)
|
2001-08-02 |
2007-02-27 |
Mips Technologies, Inc. |
Atomic update of CPO state
|
|
GB2392742B
(en)
*
|
2002-09-04 |
2005-10-19 |
Advanced Risc Mach Ltd |
Synchronisation between pipelines in a data processing apparatus
|
|
US7634638B1
(en)
|
2002-10-22 |
2009-12-15 |
Mips Technologies, Inc. |
Instruction encoding for system register bit set and clear
|
|
US6836833B1
(en)
*
|
2002-10-22 |
2004-12-28 |
Mips Technologies, Inc. |
Apparatus and method for discovering a scratch pad memory configuration
|
|
JP3855270B2
(ja)
*
|
2003-05-29 |
2006-12-06 |
ソニー株式会社 |
アンテナ実装方法
|
|
CN100461142C
(zh)
*
|
2005-07-05 |
2009-02-11 |
威盛电子股份有限公司 |
微处理器、处理器总线系统、及执行稀疏写入处理的方法
|
|
US7454492B2
(en)
*
|
2005-08-26 |
2008-11-18 |
International Business Machines Corporation |
Method and apparatus for configuring and modeling server information in an enterprise tooling environment
|
|
US7596661B2
(en)
*
|
2005-09-01 |
2009-09-29 |
Mediatek Inc. |
Processing modules with multilevel cache architecture
|
|
US7734901B2
(en)
*
|
2005-10-31 |
2010-06-08 |
Mips Technologies, Inc. |
Processor core and method for managing program counter redirection in an out-of-order processor pipeline
|
|
US7711934B2
(en)
*
|
2005-10-31 |
2010-05-04 |
Mips Technologies, Inc. |
Processor core and method for managing branch misprediction in an out-of-order processor pipeline
|
|
US20070204139A1
(en)
|
2006-02-28 |
2007-08-30 |
Mips Technologies, Inc. |
Compact linked-list-based multi-threaded instruction graduation buffer
|
|
US7721071B2
(en)
*
|
2006-02-28 |
2010-05-18 |
Mips Technologies, Inc. |
System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor
|
|
US7370178B1
(en)
|
2006-07-14 |
2008-05-06 |
Mips Technologies, Inc. |
Method for latest producer tracking in an out-of-order processor, and applications thereof
|
|
US20080016326A1
(en)
*
|
2006-07-14 |
2008-01-17 |
Mips Technologies, Inc. |
Latest producer tracking in an out-of-order processor, and applications thereof
|
|
US7650465B2
(en)
|
2006-08-18 |
2010-01-19 |
Mips Technologies, Inc. |
Micro tag array having way selection bits for reducing data cache access power
|
|
US7657708B2
(en)
*
|
2006-08-18 |
2010-02-02 |
Mips Technologies, Inc. |
Methods for reducing data cache access power in a processor using way selection bits
|
|
US8032734B2
(en)
*
|
2006-09-06 |
2011-10-04 |
Mips Technologies, Inc. |
Coprocessor load data queue for interfacing an out-of-order execution unit with an in-order coprocessor
|
|
US7647475B2
(en)
*
|
2006-09-06 |
2010-01-12 |
Mips Technologies, Inc. |
System for synchronizing an in-order co-processor with an out-of-order processor using a co-processor interface store data queue
|
|
US20080082793A1
(en)
*
|
2006-09-29 |
2008-04-03 |
Mips Technologies, Inc. |
Detection and prevention of write-after-write hazards, and applications thereof
|
|
US8078846B2
(en)
|
2006-09-29 |
2011-12-13 |
Mips Technologies, Inc. |
Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated
|
|
US9946547B2
(en)
|
2006-09-29 |
2018-04-17 |
Arm Finance Overseas Limited |
Load/store unit for a processor, and applications thereof
|
|
US7594079B2
(en)
|
2006-09-29 |
2009-09-22 |
Mips Technologies, Inc. |
Data cache virtual hint way prediction, and applications thereof
|
|
US7996632B1
(en)
*
|
2006-12-22 |
2011-08-09 |
Oracle America, Inc. |
Device for misaligned atomics for a highly-threaded x86 processor
|
|
US7769958B2
(en)
*
|
2007-06-22 |
2010-08-03 |
Mips Technologies, Inc. |
Avoiding livelock using intervention messages in multiple core processors
|
|
US7769957B2
(en)
*
|
2007-06-22 |
2010-08-03 |
Mips Technologies, Inc. |
Preventing writeback race in multiple core processors
|
|
US7953932B2
(en)
*
|
2008-02-13 |
2011-05-31 |
International Business Machines Corporation |
System and method for avoiding deadlocks when performing storage updates in a multi-processor environment
|
|
US8672411B2
(en)
*
|
2010-03-22 |
2014-03-18 |
Faurecia Automotive Seating, Llc |
Vehicle seat cushion with integrated ventilation
|
|
CN103473095A
(zh)
*
|
2013-09-10 |
2013-12-25 |
江苏中科梦兰电子科技有限公司 |
Cpu二级缓存的加速初始化方法
|
|
JP6093322B2
(ja)
*
|
2014-03-18 |
2017-03-08 |
株式会社東芝 |
キャッシュメモリおよびプロセッサシステム
|
|
GB2551529B
(en)
*
|
2016-06-21 |
2018-09-12 |
Advanced Risc Mach Ltd |
Switching between private cache and shared memory to handle atomic operations
|