TW380307B - Manufacturing method of interconnection layer for semiconductor - Google Patents

Manufacturing method of interconnection layer for semiconductor Download PDF

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Publication number
TW380307B
TW380307B TW087106994A TW87106994A TW380307B TW 380307 B TW380307 B TW 380307B TW 087106994 A TW087106994 A TW 087106994A TW 87106994 A TW87106994 A TW 87106994A TW 380307 B TW380307 B TW 380307B
Authority
TW
Taiwan
Prior art keywords
layer
forming
pattern
copper
item
Prior art date
Application number
TW087106994A
Other languages
English (en)
Chinese (zh)
Inventor
Shikin Ra
Original Assignee
Lg Semicon Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lg Semicon Co Ltd filed Critical Lg Semicon Co Ltd
Application granted granted Critical
Publication of TW380307B publication Critical patent/TW380307B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/045—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/038—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures
    • H10W20/039—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures also covering sidewalls of the conductive structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/043—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroplating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/057—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
TW087106994A 1997-12-22 1998-05-06 Manufacturing method of interconnection layer for semiconductor TW380307B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970071889A KR100253385B1 (ko) 1997-12-22 1997-12-22 반도체 소자의 배선형성 방법

Publications (1)

Publication Number Publication Date
TW380307B true TW380307B (en) 2000-01-21

Family

ID=19528155

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087106994A TW380307B (en) 1997-12-22 1998-05-06 Manufacturing method of interconnection layer for semiconductor

Country Status (4)

Country Link
US (1) US6294462B1 (2)
JP (1) JP4829389B2 (2)
KR (1) KR100253385B1 (2)
TW (1) TW380307B (2)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9287207B2 (en) 2003-09-23 2016-03-15 Micron Technology, Inc. Methods for forming conductive vias in semiconductor device components

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100330163B1 (ko) * 2000-01-06 2002-03-28 윤종용 반도체 장치의 텅스텐 콘택 플러그 형성 방법
KR20040002065A (ko) * 2002-06-29 2004-01-07 주식회사 하이닉스반도체 파워 소자 형성 방법
JP4666339B2 (ja) * 2004-05-14 2011-04-06 株式会社トリケミカル研究所 導電性バリア膜形成材料、導電性バリア膜形成方法、及び配線膜形成方法
KR100711920B1 (ko) * 2005-12-28 2007-04-27 동부일렉트로닉스 주식회사 반도체 소자의 금속 배선 및 그의 형성 방법
JP5170589B2 (ja) * 2010-12-08 2013-03-27 株式会社トリケミカル研究所 導電性バリア膜形成材料、導電性バリア膜形成方法、及び配線膜形成方法
CN103500728B (zh) * 2013-09-29 2016-03-02 武汉新芯集成电路制造有限公司 一种铜阻挡层和铜晶籽层的形成方法
CN110085569B (zh) * 2018-01-25 2020-12-22 联华电子股份有限公司 半导体结构及其制作方法

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US5316974A (en) * 1988-12-19 1994-05-31 Texas Instruments Incorporated Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer
US5219788A (en) * 1991-02-25 1993-06-15 Ibm Corporation Bilayer metallization cap for photolithography
JPH0555167A (ja) * 1991-08-28 1993-03-05 Nec Corp 半導体装置の製造方法
JPH05198525A (ja) * 1992-01-21 1993-08-06 Sony Corp 配線構造及び配線の形成方法
JPH05235174A (ja) * 1992-02-20 1993-09-10 Toshiba Corp 半導体装置の製造方法
JPH05347269A (ja) * 1992-06-16 1993-12-27 Sony Corp 半導体装置の製造方法
US5654245A (en) * 1993-03-23 1997-08-05 Sharp Microelectronics Technology, Inc. Implantation of nucleating species for selective metallization and products thereof
US5506449A (en) 1993-03-24 1996-04-09 Kawasaki Steel Corporation Interconnection structure for semiconductor integrated circuit and manufacture of the same
JPH06291194A (ja) * 1993-04-05 1994-10-18 Nec Corp 半導体装置の製造方法
KR0147682B1 (ko) * 1994-05-24 1998-11-02 구본준 반도체 소자의 금속배선 제조방법
KR0132490B1 (ko) * 1994-07-21 1998-04-16 문정환 박막트랜지스터 제조방법
US5635423A (en) 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure
US5529953A (en) * 1994-10-14 1996-06-25 Toshiba America Electronic Components, Inc. Method of forming studs and interconnects in a multi-layered semiconductor device
KR0144913B1 (ko) * 1995-03-03 1998-08-17 김광호 반도체장치의 금속배선층 형성방법
US5484747A (en) * 1995-05-25 1996-01-16 United Microelectronics Corporation Selective metal wiring and plug process
US5891804A (en) * 1996-04-18 1999-04-06 Texas Instruments Incorporated Process for conductors with selective deposition
KR100193897B1 (ko) * 1996-06-28 1999-06-15 김영환 반도체 소자의 플러그 형성 방법
US5969422A (en) * 1997-05-15 1999-10-19 Advanced Micro Devices, Inc. Plated copper interconnect structure
US5893752A (en) * 1997-12-22 1999-04-13 Motorola, Inc. Process for forming a semiconductor device
US6077780A (en) * 1997-12-03 2000-06-20 Advanced Micro Devices, Inc. Method for filling high aspect ratio openings of an integrated circuit to minimize electromigration failure
US5968333A (en) * 1998-04-07 1999-10-19 Advanced Micro Devices, Inc. Method of electroplating a copper or copper alloy interconnect

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9287207B2 (en) 2003-09-23 2016-03-15 Micron Technology, Inc. Methods for forming conductive vias in semiconductor device components

Also Published As

Publication number Publication date
KR100253385B1 (ko) 2000-05-01
JPH11260920A (ja) 1999-09-24
US6294462B1 (en) 2001-09-25
JP4829389B2 (ja) 2011-12-07
KR19990052424A (ko) 1999-07-05

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MM4A Annulment or lapse of patent due to non-payment of fees