TW444285B - Method of forming dual metal gate structures or CMOS devices - Google Patents

Method of forming dual metal gate structures or CMOS devices Download PDF

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Publication number
TW444285B
TW444285B TW089103005A TW89103005A TW444285B TW 444285 B TW444285 B TW 444285B TW 089103005 A TW089103005 A TW 089103005A TW 89103005 A TW89103005 A TW 89103005A TW 444285 B TW444285 B TW 444285B
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conductive material
transistor
gate electrode
work function
gate
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TW089103005A
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Glen D Wilk
Scott R Summerfelt
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Texas Instruments Inc
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/013Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01316Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/013Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01318Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/665Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172Manufacturing their gate conductors
    • H10D84/0177Manufacturing their gate conductors the gate conductors having different materials or different implants
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/017Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311Gate electrodes for field-effect devices
    • H10D64/411Gate electrodes for field-effect devices for FETs
    • H10D64/511Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

A7 B7 4442 8 5 五、發明說明(1 ) 【相關專利/專利申請案之對照參考】 下列之一般所指定專利/專利申請案是在此一併作為 參考: 專利號碼/編號 申請曰 Ή案號 1996/**/** ΤΙ-22027 1998/**/** ΤΙ-22748 1998/**/** ΤΙ-24776 【發明領域】 本發明是有關於半導體裝置製造方法和處理過程,更 明確地說明,是有關於一種製造一CMOS裝置之金屬閘極 結構之方法。 【發明背景】 當電子裝置變得越來越複雜化時,在該裝置上面之電 晶體數目越來越多之需求亦隨之增加。再者,是需要減少 耗電量’同時需要增加這些裝置之運算速度。至少這些規 格之部分答案是牽涉到減少每一個電晶體所占有面積。然 而,反之這將影響到一個或者多個其他規格。更特別是’ 當這些電晶體之小型化(scale down )時,亦會使該閘極 結構之小型化,並且這將增加該閘極之電阻。如此,會增 加耗電量並且降低該裝置之運作速度。 從前,是已公開若干方法來降低這些閘極結構之薄膜 電阻(sheet resistivity)。首先,是以n型和p型摻雜劑 (d〇pants )以更加濃厚之濃度來摻雜該多晶體矽 (P〇丨ycrystalline silicon)。則,該閘極之上側部分是矽化 (猜先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 ^ m I— ^1 ^1 ϋ I I ..^1 ί— I I n _ _ _ _ T 言 — — — — — — —— — — — — — — — — — I*
4442 85 A7 五、發明說明( 鎢或者矽化鈦。現今,县祐 便減少較小區域之電阻=ri(e°baUSiiiClde)以 極結構。 可此方法是牵涉到金屬閘 金屬閉極結構是具有較低薄膜電阻,盆 到該間極之寬度。然而,在„ = ^慮 許多金屬閘極材料之前,它們…::體處理-程貫订 命多金屬在靠近二氧㈣時會變得不穩定, dielectr Λ二氧化石夕來作為該閘極介質層(柳 ecrlc ayer。另一個問題是如下:當許多金 時,它們會變得較不具傳導性。 乳 線 是已經使用銘和鶴來形成閑極結構。銘是因上述之問 題而不是-個良好選擇,而鶴是具有一個界於p型多晶體 夕(聚口物poly)和n型聚合物之功函數之間的工作函 數雖然使用鶴之問題是如下:當所施加電壓變得 越f越小時,實際上該功函數是在中間間隙(midgap)並 且是無法變更(與η型和p型聚合物相比較時),提供一 個高於該PMOS和NM0S裝置之臨界電壓的閑極位能 (gate potential)是有困難。 在使用一個用於PM0S和NM〇s兩者裝置之中間間 隙金屬(midgap metal)來克服這個臨界值電壓問題之方法, 是已經使用鋁來作為—種型態之裝置,同時,是使用白金 (platinum)來作為另一種型態之裝置。然而,白金是很昂貴 並且難以結合,而鋁是受到上述之問題並非良好選擇。如 此,是需要一種閘電極材料,其傳導率是與該閘極寬度無 -4- 本紙張尺度適用令國國豕標準(CNS)A4規格<210 X 297公爱 4442 8 5 A7 B7 五、發明說明(3) 關並且具有用於pM〇S裝置和NM〇s裝置之不同功函 數。 【發明概要】 本發明之一較佳貫施例是揭露一種方法,其是在一個 半導體基板上面形成一個具有一第1閘電極之第i電晶體 和—個具有一第2閘電極之第2電晶體,該方法是含有下 列之步驟:形成一個第i傳導材料,.其是以絕緣方式沈積 在該半導體基板之一第丨部分,該第丨傳導材料是具有一 個第1功函數;形成一個第2傳導材料,其是以絕緣方式 沈積在該半導體基板之一第2部分,該第2傳導材料是含 有該第1料材料,但是其具有—個與該帛1功函數不同 之第2功函數;及其甲,是使用該第丨傳導材料來形成該 第1閘電極,並且是使用該第2傳導材料來形成該第2閘 電極。在另一個較佳實施例,該第丨·傳導材料是含有钽 (Ta),而遠第2傳導材料是含有丁心%。在其他較佳實施 例,該第1傳導材料是含有鉬(M〇),而該第2傳導材料是 含有MoxNy。在另外之較佳實施例,該第【傳導材料是含 有欽(Ti),而該第2傳導材料是含有TixNy。 本發明之另一較佳實施例是揭露一種方法,其是在一 個半導體基板上面形成一個具有一第丨閘電極之第丨電晶 體和一個具有一第2閘電極之第2電晶體’該方法是含有 下列之步驟:形成一個傳導材料,其是以絕緣方式沈積在 該半導體基板,該傳導材料是具有一個功函數;及變更一 部分之傳導材料,以便改變已變更傳導材料之功函數,該 本紙張尺度適用中國固豕標準(CNS)A4規格<210 κ 297公爱) {請先閱讀背面之注意事項再填寫本頁) ^-------—訂_1 —晒 ί— 線· 經濟部智慧財產局員工消费合作杜印製 4442 8 5 A7 B7 五、發明說明(4) 傳導材料是形成該第1閘電極’而該已變更傳導材料是形 成該第2閘電極。最好是’該第1電晶體是一個NMOS 裝置’該第2電晶體是一個PMOS裝置,而該第1電晶體 和該第2電晶體是形成一個CMOS裝置。最好是,該傳導 材料是含有一個導體’其是由组(Ta)、鉬(Mo)、鈦(Ti)和 其任何結合物所組成之組群來選定。最好是,變更一部分 之傳導材料的步驟是含有:使該部分之傳導材料曝露到一 種結合一含I氣體之電敷。 【附圖簡述】 圖1是一個截面圖,其圖示一個本發明之一較佳實施 例的方法所部分製成之CMOS裝置。 圖2是一個本發明之一較佳實施例的方法之流程圖。 圖3a-3e是截面圖,其圖示一個如阅圖2所示之使用 本發明方法所部分製成之半導體裝置。 圖4是一個圖表,其圖示不同材料之功函數。 除非另外指示’否則在不同附圖之類似數字或者符號 是表示對應之結構。所提供之附圖是僅說明本發明之觀 念。這些附圖並非依照比例來繪製。 【附圖詳細說明】 基本上,本發明是牽涉到一種CMOS裝置和一種方 法’該方法是能製造結合一個用於NMOS裝置和PMOS 裝置及使用不同金屬閘電極版本之用於其他裝置、PMOS 裝置或者NMOS裝置(各別地)金屬閘電極的裝置。最好 是’本發明是牵涉到:至少是部分形成鈕NMOS裝置之 本紙張尺度適用中國國象標準(CNS)A4規格(21Q X 297公楚) (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消费合作社印製 ^ I I I ϊ I I I — — — — I II — — — — — — — — — — — — — — — — — 111 — 4442 8 5
五、發明說明(5 ) 閘電極,和至少是部分形成氮化组之PM〇s裝置的閘電 極。如此,本發明是牽涉到相同之基極金屬,例如是钽, 但疋使用另種型式之基極金屬來作為該裝置閘電極之 一者。是能使用一種可沈積之閘極方法(gate methodology)(基本上是如同圖2和圖3a_3e所說明般),或 者以習知之閘極形成方法(基本上是如同圖丨所示般)來實 施本發明。 參考圖1 ’是能使用習知技術來製造本發明之CMOS 裝置100,或者是使用在圖2和圖3a-3e所示之可沈積閘 極方法來製造該者。該形成閘極結構之習知方法是牽涉到 形成絕緣結構 118,其是呈 LOCOS(Localized Oxidation Semiconductor)型絕緣結構,淺溝絕緣(shallow trench isolation)結構(STI如同圖1所示來作為絕緣結構118),或 者摻雜質絕緣區域(doped isolation regions)。是形成一層閘 極絕緣層並且附加一層覆蓋閘極傳導層(over丨ying gate conductor layer)。在本發明,該閘極絕緣層含有下列者為 較佳:二氧化矽,氮化矽,一種高介電常數材料(諸如 PZT锆酸鈦酸鉛,BST鈦酸鋇锶,五氧化钽,或其他一般 所使用之材料),一種碎酸鹽(silicate),一種或者多種上列 者之結合物,一種氧氮化物(oxynitride),或者其叠層。該 閘極導體層含有一種金屬,其能以選擇方式來變更以便改 變其功函數為較佳。這些例子是欽(titanium),組 (tantalum),銦(molybdenum),或其他類似金屬。在該閘極 結構形成圖案或者蝕刻之前或者在這些步驟之後,是轉換 -7- 本紙張尺度適用中國國家標準(CNS)A4規格(210x 297公釐) (請先閱讀背面之注意事項再填寫本頁)
於,-------訂 ----I 經濟部智慧財產局員工消费合作社印製 < 4442 8 5 經濟部智慧財產局貝工消费合作社印製 A7 五、發明說明(6 ) -部分之雜導體以便變更其功函數。最好是,使這部分 之傳V層C或者-部分之已形成圖案和已蚀刻的閘極結構) 氮化’和在部分之閘極結構上面使用—種金屬/氮化物 /金屬疊層,俾使這層金屬熱處理來均勻分佈氮,來完成 該者。因為該傳導材料是相當薄(在5至5〇nm(奈米)左右 為較佳)’在一個含氮氣環境(諸如氦氣)使這部分之層(或 者it些特定閘極導體’其是已形成.圖案並已㈣)熱處 if ’或者使所選定部分之傳導層或閘結構曝露在—種結合 —電敢之含氮氣體(I氣為較佳),來使這些將Su化部分氣 化。然而,替代—層已經形成之傳導層的氮化部分,是能 NMOS閑極結構分隔開來形成該pM〇s閘極結構。 ^此’是能歧、翻或鈦來形成-個閘極結構,而其他者 疋能以组、_歧和—個含i氣來源(朴氮氣)來共同沈 積(co deposit)。另一方面,該氮化物是含有—疊層之鉅、 則鈦及層含氮層(諸如氣化组,氣化钥或氣化欽)’接 著,其熱處理,以便使敗氣均句分佈到這些間極結構。最 好是’該NMOS裝置102之問極導體1〇6是含有组、鉬 或鈦,而該PMOS裝置丨〇4之閉極導體應是含有氣氣和 鈕、鉬、鈦和一種與其結合之結合物。
在形成該閘極結構之後,是形成源極/沒極延伸區域 (如果是有使用)和這麵極/祕區域U4和ιΐ6。在該 者之後是依照標準處理過程。 〇X 在圖2和圖3a_3e是說明本發明之另一較佳實施例。 这個較佳實施例之細節是適用於上述之較佳實施例。參考 -8- κ紙張尺度適用中國標準(CNS)A4規格⑵G χ 297公笼 ------------^.!tl--------- 線 (請先閱讀背面之注意事項再填寫本頁)
圖2和圖3a之步驟2G2 ’是形成絕緣結構316。絕緣結構 3^6疋含有LOCOS、STI、或者摻雜質絕緣區域。接著, 尺形成第1和第2虛設層(dummy layers)。該第1虛設層 是含有形成該間極絕緣物之材料或者其僅是—層虛設層。 如果該第1虛設層是含有該閘極絕緣材料(二氧化矽,氮 化矽’一種氧氮化合物’ BST,五氧化组,一種矽酸鹽, 或者其他適當之閘極絕緣材料為較佳),則接著不是移除 這層,在步驟214亦不是形成閘極絕緣層324。在該第i 和2虛設層是已經形成圖案並且已經蝕刻過’以便形成 PMOS裝置302和NMOS裝置304之虛設閘極結構。該虛 設閘極結構是含有2層。如果該底層(層31〇和311)並非 確實含有該閘極絕緣材料,則當在步驟212移除該者時, 其是含有一種材料,該材料是能移除並且不會損害該結構 301或反之影響周圍結構。如果該第!層是一層可移除 層’則該第1和第2層是能含有相同材料。如此,結構 310、306、311和308是含有相同材料。最好是,這些結 構是含有一種材料,當移除時,該材料反之是不會實質影 響該基層基板(underlying substrate)301或者周圍結構(諸如 側壁絕緣物318和3丨9,及平面絕緣材料322)。所以,社 構310 ' 306、311、和308是含有氮化石夕,二氧化石夕,多 晶體石夕,錯化碎(silic〇n germanium),或者其他任何材料, 其對該基層矽基板和氧化物或氮化物側壁絕緣物是可選擇 地移除。 參考圖2之步驟204,是使用該絕緣結構316和可沈 -9- 本紙張尺度刺中關1標準(CNS)A4規格C 297公釐〉 (請先閱讀背面之注意事項再填寫本頁) --------訂-! 丨 經濟部智慧財產局員工消費合作社印製 4 442 8 5 經濟部智慧財產局員工消费合作社印製 A7 B7 五、發明說明(8 ) 積之閘極結構(結構310/306和311/308)來對準,以便形成 源極/汲極延伸區域(如果有需要)。PM〇s裝置3〇2之源/極/ 没極延伸區域312最好是含有—種p型摻雜物(諸如蝴), 而NMOS裝置304之源極/汲極延伸區域3〗4最好是含有 η型摻雜物(諸如磷或者砷)。 參考圖2和圖3b之步驟206,是形成側壁絕緣物318 和319。側壁絕緣物318和319是含有熱成長二氧化矽 (thermally grown silicon oxide),可沈積之二氧化矽,氮化 矽,一種氧氮化物,或一種結合物或其疊層。參考步驟 208 ’接著是形成源極/汲極區域313和315。最好是,使 該基板摻雜蝴來形成源極/汲極區域313,及使該基板摻 雜砰(arsenic)及/或麟來形成源極/;;及極區域315。 參考圖2和圖3之步驟210 ’是形成絕緣層322。最 好是’是使絕緣層322流到該晶圓上面,以便使其頂端表 面是與該可沈積之閘極結構和側壁絕緣物之頂端呈大約相 同高度。然而’是能使絕緣層322沈積或者流到該晶圓上 面’接著使用化學一機械拋光(chemical-mechanical polishing, CMP)來拋光並與該可沈積之閘極結構和侧壁絕 緣物共同延伸(co-extensive)。較好是,絕緣層是含有一種 可流動氧化物(諸如氣凝膠(aexogel),乾燥凝膠(xer〇gel), 或者HSQ(氫倍半氧矽烷)),BPSG,TEOS(四乙氧基矽 烷)’ PETEOS(電漿增強式四乙氧基矽烷),PSG,FSG,或 者其他氧化矽材料。 參考圖3d和圖2之步驟212,是移除該可沈積之閘 -10- 本紙張尺度適用中圉國家標準(CNS>A4規格(210 X 297公釐) -------^--------訂 i — —----1-線 (請先閱讀背面之注意事項再填寫本頁) 4442 8£ Γ A7 B7 五、發明說明( 經濟部智慧財產局員工消费合作社印製 ^構(結構306和·及結構31〇和3ΐι,如果它們並不 包^該閘㈣緣㈣)。最好是,完成該者,俾使該基板 ’側壁絕緣物318和319,絕緣層322及這些問極絕緣 物31()和311(如果它們是㈣閘極絕緣材料來形成,立是 這些裝置所需要者)在實質上不會劣化或者银刻掉_ away) 〇 參考圖2之步驟214,如果在步驟m,結構310和 % 所冑^_料和移除掉,是形成閘極絕緣 層324。閘極絕緣材料最好是含有二氧㈣,氮化石夕,一 種氧氮化合物,-财酸鹽,或者—種高—κ值材料 (high{ material)(諸如贿,五氧化紐或者其他適當材 料)。 在圖2之步驟216是形成導體326。最好是,導體 326是含有钽,鉬,鈦或者其他適當導體,其能以選擇方 式來變更,以便能以選擇方式改變其功函數。然而,一部 分之導體326是能含有鈕、鉬或鈦,同時,其他部分是含 有另一種型式之钽' 鉬或鈦(一種氮化物者為較佳)。該已 變更型式可以是下列者:钽、鉬或鈦是以氮氣來共同沈積 (co-deposit)或者其可以是一疊層之鉅、鉬及/或鈦和一氮 化物。最好疋,導體326是含有组 ' 麵和欽,並且接著將 其變更。導體320是相當薄,俾使其功函數能界定該閘極 之運作(functioning^導體326之厚度是在大約5到50nm 左右(在厚度方面是大約8到10個單元晶胞或更多)。 在導體326和絕緣層324形成圖案和蝕刻之前及在這 -11- 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 X 297公釐) ---— Ill----I ^ --------訂---I ί I I--線 (請先間讀背面之注意事項再填寫本頁) 4442 85 A7 ______________ B7____ 五、發明說明(10) ' (請先閲讀背面之注意事項再填寫本頁) 個步驟之後’是能變更-部分(或該間極導體—導體切 之一者)’以便改變其功函數。是使該部分之導體326(或 導體329)去除光罩及使該導體326或導體327之曝露部分 曝露到一種變質劑(altering agent),來完成該者。最好是, 使該晶圓曝露到一種能在一電漿内結合之氮氣(氮氣為較 佳)來形成這個變更例(aeration)。這個步驟最好是在二種 周圍溫度或大約:?〇〇到50(rc持續大約2〇秒到2分鐘來實 施。這個步驟之目的在實質上是胁、麵或鈦完全轉換^
TaxNy、MoxNy、或 TixNy。 一旦完成這個變更例並且在該閘極結構形成圖案和蝕 刻,是能形成另一種傳導材料,以便充填該閘電極之剩餘 部分(如果有需要時)。最好是,這個額外之傳導材料是含 有鎢、鋁或其他傳導材料。 雖然在此是說明本發明之特定較衩實施例,它們並不 會構成本發明範圍之限制。對於這些熟悉該技藝者,借助 該說明書之方法’是能使本發明之許多較佳實施例變得更 加明顯。是僅以下列之申請專利範圍來限制本發明之範 圍0 經濟部智慧財產局具工消费合作杜印製 適 I度 尺 張 紙 本 II J準 標 家 爱 公 97 2 一 X 10 2 I規 4 Μ

Claims (1)

  1. 經濟部智慧財產局員工消費合作杜印製 IZ能在-個半導體基板上㈣成_歸有1 u ^之弟1電晶體和—個具有1 2閘電極之第2電 B曰體之方法,該方法是財下列之步驟: 形成-個第1傳導材料’其是以絕緣方式沈積在 斜導體基板之一第1部分,該第!傳導材料是具有 —個第1工作函數; 形成-個第2傳導材料,其是以絕緣方式沈積在 該半導體基板之一第2部分,該第2傳導材料是含有 S亥第1傳導材料,但其具有—個與該第i功函數不同 之第2功函數;及 其中是使用該第1傳導材料來形成該第1閘電 極,並使用該第2傳導材料來形成該第2閘電極。 2·如申請專利範圍第!項之方法,其中該第i傳導材料 是含有组(邱,而該第2傳導材料是4有TaxNy。 3.如申請專利範圍第丄項之方法,其中該第"事導材料 是含有_) ’而料2料㈣是含有Μ。#。 (如申請專利範圍第1項之方法,其中該第丄傳導材料 是含有鈦(Ti),而該第2傳導材料是含有TixN。 5. -種月匕在一個半導體基板上面形成一個具有一第!閘 電極之第1電晶體和一個具有一第2閉電極之第2電 晶體之方法,該方法是含有下列之步驟: 形成-個傳導村料,其是以絕緣方式沈積在該半 導體基板,該傳導材料是具有一個功函數;及 變更一部分之傳導材料,以便改變該已變更傳導 -13 - --------^------—,^ --------訂---------線— --- <請先閱讀背面之注意事項再填寫本頁) 89038Β(9Τί) 4442 85
    六、 申請專利範圍 材料之功函數,該傳導材料是形成該第1閘電極,而 該已變更傳導材料是形成該2閘電極。 6-如申請專利範圍第5項之方法,其中該第丨電晶體是 一個NMOS裝置,而該第2電晶體是一個pM〇s铲 置。 < 如申請專利範圍第6項之方法,其中該第1電晶體和 遠第2電晶體是形成一個CMOS裝置。 8. 如申請專利範圍第5項之方法,其中該傳導材料是含 有-個導體’該導體是從由纽、銦、欽和任何其結合 物所構成之族群所選定者。 …D 9. 如申請專利範圍第5項之方法,其中該變更—部分之 傳導材料的步驟是含有:使該部分之傳導材料曝露到 一種能結合一含氮氣體之電漿。 f請先閱讀背面之注意事項再填寫本頁) ----訂--------線— 經濟部智慧財產局員工消費合作杜印製 14 本紙張又度適用中國國私標準(CNS)A4規格(21〇 X 297公爱)
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