461069 。 A7 _______________B7五、發明説明（） Ι·1發明領域： 經濟部中央標準局員工消費合作社印製 本發明係有關於一種靜電保護電路，特洌是有關於利 用堆疊式動態隨機存取記憶體（Stack DRAM)之製程，在 打線銲（bonding pad)下的空間，形成一等效電阻，藉以 完成整個堆疊式靜電保護電路。 5·2發明背景： 參見第1圖所示，爲靜電保護電路之電路示意圖。在 打線鮮(bόndlng pad) 1 〇與内部電路之間，以一電阻）2 與一 M0S元件14形成具保護内部電路之靜電保護電路 16。該内部電路係根據不同的半導體製程之需求，設計 成具不同功能性之電路。 參見第2A圖所示，爲依據傳統方法，形成靜電保護 電路完成之剖面結構圖。參見第2B圖所示，爲依據第2A 圖相對應之佈局（Layout)示意圖。在傳統的靜電保護電路 製程中，利用一隔離製程，例如區域氧化法（LOCOS),在 半導體底材矽20上形成一場氧化層（Field Oxide ; F〇X)22以定義出一主動區域，接著在半導體底材砂20 上之主動區域内，沈積多晶♦層並以光罩（Layout)24a爲 蝕刻罩幕，形成M0S元件之閘極24 ，接著利用光罩 本紙張尺度適用_國國家標準（€阳）八4規格（210父297公釐） m, -- I:°ml —LI !0 - It/, HI I I I In —«t· ......1- - - : 1^1 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標隼局員工消費合作社印製 461069 A7 _________B7 _五、發明説明（） (Layout)26a進行離子植入，摻雜離子擴散驅入底材矽 20，以形成MOS元件之汲極26和源極28。之後，在場 氧化層22、閘極24與底材矽20上，形成一介電層3〇 / 接著利用光罩（Layout>32a ，以非等向性蝕刻介電層30 以形成一打線銲接觸窗（bonding pad contact hole)32。 利用光罩（Layout)36a ’以非等向性触刻介電層3〇以形 成一内連線接觸窗（interconnect contact ho.丨e)36。接著 在場氧化層22與介電層30上，形成一金屬層以填如打線 鋒接觸窗3 2與内連線接觸窗3 6内，並個别利用光罩 (Layout)34a 與光罩（Layout)38a，定義出打線銲（bonding pad〉34圖案·與金屬内連線（interconnect)38圖案，以完成 整個靜電保護電路。此時，M0S元件之汲極26係作爲靜 電保護電路之電阻，而金屬内連線（interconnect)38連接 至半導髏製程的其他内部電路之M0S元件。 由於傳統的靜電保護電路，係以M0S元件之没極作 爲靜電保護電路之電阻，因此隨著製程之中電阻僅增加的 需求’將會被不斷地要求加長半導體底材矽上的掺雜區域 (M0S元件之汲極）以增加電阻値，因此對於整個積體電路 的設計，將造成過度空間的浪費。此外，因爲利用離子植 入和熱擴散方法，在半導體底材矽上形成摻雜區域（M〇s 元件之汲極和源極），並以M0S元件之汲極作爲靜電保護 電路架構中的電阻，因此藉由擴散所形成的電阻値，往往 不易控制，造成誤姜過大。 (請先閲讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標準（CNS〉A4規格（210X297公釐） 6 1069 A7 B7 五、發明説明（） 5·5發明目的及概述： ， 本發明的主要目的在提供一種堆疊式靜電保護電 路，用以節省空間，並可提昇控制電限値的精確度。 根據以上所述之目的，本發明之堆疊式靜電保護電路 架構，係利用堆疊式動態隨機存取記憶體（Stack DRAM) 之製程，在打線銲（bonding pad〉下的空間，形成一等效 電阻，以節省空間.，Jt有效地控制電阻値。該堆疊式靜電 保護電路製程如下所述： 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 利用一隔離製程以形成一場氧化層於一半導體底材 矽上；形成一 MOS元件於底材矽上，該MOS元^具有源 極、汲極與閘極；形成第一介電層於閘極、源極與底材石夕 上，用以作爲一絶緣層；形成第一導電層於場氧化層、没 極與赛一介電層上’係由微影蝕刻以定義出第一導電層圖 案，用以作爲電容之下極板；形成第二介電層於第一導電 層、第一介電層上，用以作爲電容之介電層；形成第二導 電層於第一介電層上，係由微影姓刻以定義出第二導電層 圖案’用以作爲電谷之上極板，形成.第三介電層於第一導 電層、第二介電層上，用以作爲一保護層；形成打線銲接 觸窗於場氧化層上，係由乾式蝕刻位於場氧化層上之第— 本紙張尺度適用中國國家標準（CNS ) A4規格（210X2974^ 7" 461069 經濟部中央標準局員工消費合作社印製 A7 B7五、發明説明（） 介電層、第二導電層與第二介電層至第一導電層以形成； 形成位元線接觸窗於MOS之源極上，係由乾式蝕刻位於 MOS之源極上之第三介電層、第二介電層與第一介電薈 至源極以形成；形成金屬導電層於第三介電層上，並填入 打線銲接觸窗、位元線接觸窗中，該金屬導電層藉由微影 蝕刻以定義出一打線銲（bonding pad)圖案’用以封装 (package)與一位元線（bit line)圖案。 5_4圖式簡單説明： 第1圖爲靜電保護電路之電路架構示意圖。 第2A圖爲依據傳统方法，形成靜電保護電路完成之剖面 結構圖。 第2B圖爲依據第2A圖相對應之佈局（Lfyout>示意圖。 第3A圖至第3F圖爲依據本發明方法，形成堆疊式靜電保 護電路之各階段完成之剖面結構圖。 第4A圖爲依據本發明方法，形成堆疊式靜電保護電路完 成之刻面結構圖。 第4B圖爲依據第4A圖相對應之佈局（Layout)示意圖。 5-5發明詳細説明： (請先閲讀背面之注意事項再填寫本頁) 訂 .< 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 461069 A7 __B7 五、發明説明（） 本發明之堆#式靜電#護電路，係利用堆疊式動態随 機存取記憶體（Stack DRAM)之製程，形成具堆疊式的電* 容結構，並在堆聲式電容的上極板與介電層上形成一接觸 窗，之後一金屬廣形成於其結構之上，並填入接觸窗中， 以作爲打線銲（bonding pad)。利甩該接觸窗與，〇3元件 之汲極之間之堆疊式電容的下極板來有效地控制堆疊式 靜電保護電路之電阻値。 參見第3A圖所示’藉由一隔離製程，例如區域氧化 法（L 0 CO S) ’在半導體底材梦1〇〇上形成一場氧化層 (Field Oxide ; FOX) 102以定義出一主動區域，接著在 半導體底材矽100上之主動區域内.，形成_ M0S電晶體 (Meta卜Oxide-Semiconductor Field Effect Transistor)， 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填窝本頁) 其具有閘極10_4、没極1 (}¾和源極1 〇 8。場氧化層1 Q2 形成於底材梦100上，並且和汲極106相鄰以作爲隔離製 程。接著以化學氣梱沈積法（CVD>沈積第一介電層11〇於 M0S電晶體、底材矽1 〇〇、場氧化層彳〇2上，用以作爲 一絶緣層》該第一介電層1 1 〇爲二氡化矽，其厚度约爲 9Q0至1 1 〇〇埃之間β之後利用微影蝕刻技術，形成一層 光阻111以定義出第一介電層no圖案，並以光阻m 爲触刻罩幕，蝕刻去除場氧化層1〇2與没極1〇6上之部份 第一介電層110，以形成第一介電層110圖案。 本紙張尺度賴巾咖家標準（CNS) M雜（2Ι()χ297公楚） 461069 A7 B7 五、發明説明（） 參見第3B囷所示，在場氧化層1〇2、汲極1〇6與第 一介電廣110上，形成具厚度约爲9〇〇至11〇〇埃之間之 第一導電層112。該第一導電層112可爲多晶矽層。接著· 利用微影蝕刻技術，形成一層光阻彳]3以定義•出第—導電 層112囷案，並以光阻113爲蝕刻罩幕，蝕刻去除部份第 -導電層112,以形成第—導電層112圖案，用以作爲電 容之下極板。 接著參見第3C圖所示，利用化學氣相沈積法（cvd) 沈積第二介電層114於第一導電層112、第—介電層11〇 上，其材質可爲二氧化矽或二氧化矽、氮化矽、二氧化矽 之組合結構（ΟΝΟ)等，其厚度約爲6〇至7〇 1 今〈間，該第 二介電層1 1 4用以作無電容之介電層。 接著參見第3D圖所示，在第二介電層1(| 上，形成 第二導電層116。該第二導電層116之厚度約爲9〇〇至 1 100埃之間，其材質可爲多晶矽層。接著覆蓋一層光阻 117以定義出第二導電層116圖案，並以光阻] 1 1 ,爲蝕刻 軍幕，蝕刻去除部份第二導電層6，以形成s /叫弟二導電層 116圖案，用以作爲電容之上極板。 經濟部中央標準局負工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 參見第3E圖所示，以化學氣相沈積法（CVD)沈積第 三介電層118於第二導電層116、第二介電層114上，、其 材質可爲二氧化矽、磷矽玻璃、硼磷矽玻璃等，其厚产約 461069 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（） 爲7000至90 00埃之間r用以作爲保護層。接著上一層 光阻119於第三介電層H8上，以定義出位元線接觭窗 (bit line contact hole〉120 與打線銲接觸窗（ponding pad contact hole) 1 22。之後以光阻11 9爲蝕射罩幕，利用乾 式蝕刻方式触刻位於場氧化層1〇2上之部份第三介電層 118、第二介電層114輿第一介電層ίΐ〇至源極1〇8 ,以 形成位元線接觸窗（|3丨〖丨丨116〇〇1^3(：'1|1〇丨.6)120。同時，以 光阻1 1 9爲’餘刻罩慕，利用乾式钟刻方式蚀刻位於源極 108上之部份第三介電層118、第二導電層116、第二介 電層114至第一導電層112 ，以形成打線銲接觸窗 (ponding pad contact ho丨e>122。由於電阻値與導電係 數、面積與長度有關： R = pX L/A => R 〇c L 其中R爲電阻値、L爲長度。 因此，僅需根據堆疊式靜電保護電路製程中電阻的需求， 在場氧化層102上的適當位置，形成打線銲接觸窗122， 即可利用打線銲接觸窗122與汲極106之間距離（L) 123 之第一導電層112來控制靜電保護電路之電阻値^ 參見第3F圖所示，形成第三導電層124於第三介電 層118上，並填入打線銲接觸窗（ponding pad contact hole)122與位元線接觸窗（bit line contacthole>120 中。 該第三導電層124材質可爲鋁矽銅合金，其厚度約爲7500 至8500埃之間。接著利用微影蝕刻技術，形成一層光阻 „L. ξ--^---- (請先閲讀背面之注意事項再填寫本頁)461069. A7 _______________B7 V. Description of the invention (1.1) Field of invention: Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs This invention is about an electrostatic protection circuit, especially about the use of stacked dynamic random access memory (Stack In the DRAM) process, an equivalent resistance is formed in the space under the bonding pad to complete the entire stacked electrostatic protection circuit. 5.2 Background of the Invention: See Figure 1 for a schematic circuit diagram of an electrostatic protection circuit. An electrostatic protection circuit 16 is provided between the wiring pad 1 〇 and the internal circuit with a resistor 2 and a MOS device 14 to protect the internal circuit. The internal circuit is designed into circuits with different functions according to the requirements of different semiconductor processes. Refer to FIG. 2A, which is a cross-sectional structure diagram of a conventional method for forming an electrostatic protection circuit. Refer to FIG. 2B for a schematic diagram of the layout according to FIG. 2A. In the traditional electrostatic protection circuit manufacturing process, an isolation process, such as the LOCOS method, is used to form a field oxide layer (Field Oxide; F0X) 22 on the semiconductor substrate silicon 20 to define an active area. Then, In the active area on the semiconductor substrate sand 20, a polycrystalline layer is deposited and a mask (Layout) 24a is used as an etching mask to form the gate 24 of the M0S element, and then the mask is used. This paper is applicable for this paper. (€ yang) 8 specifications (210 father 297 mm) m,-I: ° ml —LI! 0-It /, HI III In — «t · ...... 1---: 1 ^ 1 (Please read the precautions on the back before filling out this page) Printed by the Central Consumers' Bureau of the Ministry of Economic Affairs, Employee Consumer Cooperative 461069 A7 _________B7 _V. Description of the Invention () (Layout) 26a for ion implantation, doped ion diffusion drive The substrate silicon 20 is used to form a drain 26 and a source 28 of the MOS device. After that, a dielectric layer 30 is formed on the field oxide layer 22, the gate electrode 24, and the substrate silicon 20. Then, the dielectric layer 30 is anisotropically etched using a photomask (Layout> 32a) to form a wire bond. Bonding pad contact hole 32. The dielectric layer 30 is etched with anisotropy by using a mask 36a 'to form an interconnect contact ho. 丨 e 36. Then in A metal layer is formed on the field oxide layer 22 and the dielectric layer 30 to fill the contact window 32 and the interconnect window 36, respectively, and each uses a mask 34a and a layout. 38a, defining bonding pattern (bonding pad> 34 pattern and metal interconnect 38 pattern to complete the entire electrostatic protection circuit. At this time, the drain 26 of the M0S element is used as the resistance of the electrostatic protection circuit, and the metal Interconnect 38 is connected to the M0S components of other internal circuits in the semi-conductor process. As the traditional electrostatic protection circuit, the end of the M0S component is used as the resistance of the electrostatic protection circuit, so with the process, the resistance is only 'Increased demand' will be continuously requested Long doped regions on the semiconductor substrate silicon (the drain of the MOS device) to increase the resistance 値, so the design of the entire integrated circuit will cause excessive waste of space. In addition, because of the use of ion implantation and thermal diffusion methods, A doped region (drain and source of the MOS device) is formed on the semiconductor substrate silicon, and the drain of the MOS device is used as a resistor in the electrostatic protection circuit structure. Therefore, the resistance formed by diffusion is often It is not easy to control, which may cause the ginger to be too large. (Please read the notes on the back before filling in this page.) The size of the paper is applicable to Chinese national standards (CNS> A4 size (210X297 mm) 6 1069 A7 B7 V. Description of invention () 5 · 5 Purpose and Summary of the Invention: The main purpose of the present invention is to provide a stacked electrostatic protection circuit to save space and improve the accuracy of controlling the electrical threshold. According to the above-mentioned object, the stacked type of the present invention The electrostatic protection circuit architecture uses the process of stacked dynamic random access memory (Stack DRAM) to form an equivalent space under the bonding pad. Resistance to save space. Jt effectively controls the resistance 堆叠. The process of the stacked electrostatic protection circuit is as follows: Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). Isolation process to form a field oxide layer on a semiconductor substrate silicon; forming a MOS device on the substrate silicon, the MOS element has a source, a drain and a gate; forming a first dielectric layer on the gate and the source The electrode and substrate Shi Xi are used as an insulating layer; the formation of the first conductive layer on the field oxide layer, the electrode and the Sai dielectric layer is etched by lithography to define the first conductive layer pattern, and It is used as a capacitor under the plate; a second dielectric layer is formed on the first conductive layer and the first dielectric layer as a dielectric layer of the capacitor; a second conductive layer is formed on the first dielectric layer. The second conductive layer pattern is defined by the lithographic surname to be used as an electrode plate on the valley. The third dielectric layer is formed on the first conductive layer and the second dielectric layer as a protective layer. ; Forming a wire bonding contact window on the field oxide layer by dry etching Located on the field oxide layer — This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X2974 ^ 7 " 461069 A7 B7 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. The conductive layer and the second dielectric layer are formed to the first conductive layer to form a bit line contact window on the source of the MOS. The third dielectric layer and the second dielectric layer on the source of the MOS are dry-etched. The first dielectric layer is formed from the source to the source; a metal conductive layer is formed on the third dielectric layer and filled in the wire bonding contact window and the bit line contact window. The metal conductive layer is defined by lithographic etching. A bonding pad pattern is used to package and a bit line pattern. 5_4 diagram brief description: Figure 1 is a schematic diagram of the circuit structure of the electrostatic protection circuit. Fig. 2A is a cross-sectional structure diagram of a conventional method for forming an electrostatic protection circuit. Fig. 2B is a schematic diagram corresponding to the layout of Fig. 2A (Lfyout >). Figs. 3A to 3F are cross-sectional structural diagrams of each stage of forming a stacked electrostatic protection circuit according to the method of the present invention. Fig. 4A is based on The method of the present invention forms a faceted structure diagram of a stacked electrostatic protection circuit. Figure 4B is a schematic diagram of the layout according to Figure 4A. 5-5 Detailed description of the invention: (Please read the precautions on the back first (Fill in this page) Order. ≪ This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) 461069 A7 __B7 V. Description of the invention () The pile # 式 electrostatic # protection circuit of the present invention uses stacking dynamics The random access memory (Stack DRAM) process forms a stacked capacitor structure, and a contact window is formed on the upper plate and the dielectric layer of the stacked capacitor, after which a metal is widely formed on it. Above the structure, and filled into the contact window as a bonding pad. The lower electrode plate of the stacked capacitor between the contact window and the drain of the 〇3 component can be effectively controlled to effectively control the stacked static electricity. protection The resistance of the circuit is shown in Fig. 3A. "With an isolation process, such as a region oxidation method (L 0 CO S)", a field oxide layer (Field Oxide; FOX) 102 is formed on the semiconductor substrate Dream 100. An active area is defined, and then in the active area on the semiconductor substrate silicon 100, a _ M0S transistor (Metab Oxide-Semiconductor Field Effect Transistor) is formed, printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read first Note on the back page is refilled) It has a gate electrode 10_4, a pole electrode 1 (} ¾ and a source electrode 108. The field oxide layer 1 Q2 is formed on the substrate dream 100 and is adjacent to the drain electrode 106. As an isolation process, the chemical dielectric gas deposition method (CVD) was used to deposit the first dielectric layer 110 on the MOS transistor, the substrate silicon 100, and the field oxide layer 002 as an insulating layer. The first dielectric layer 110 is silicon dioxide, and its thickness is about β between 9Q0 and 1 100 angstroms. Afterwards, a photoresist 111 is formed by using a lithography etching technique to define the no pattern of the first dielectric layer. , And using the photoresist m as the engraved mask, the field oxide layer 102 and the electrode are etched and removed. A part of the first dielectric layer 110 on 106 is formed to form the pattern of the first dielectric layer 110. The paper size is based on the CNS Standard (CNS) M (2Ι () × 297), 461069 A7 B7 V. Description of the invention () As shown in FIG. 3B (a), a field oxide layer 102, a drain electrode 106, and a first dielectric layer 110 are formed with a thickness of about 900 to 1100 angstroms. A conductive layer 112. The first conductive layer 112 may be a polycrystalline silicon layer. Next · Use lithography etching technology to form a layer of photoresistance] 3 to define • Draw out the first conductive layer 112 case, and use photoresist 113 as an etching mask to etch away part of the first conductive layer 112 to form the first conductive layer 112. -The pattern of the conductive layer 112 is used as a plate under the capacitor. Next, referring to FIG. 3C, a second dielectric layer 114 is deposited on the first conductive layer 112 and the first dielectric layer 110 by chemical vapor deposition (cvd). The material may be silicon dioxide or dioxide. The combined structure of silicon, silicon nitride, silicon dioxide (ONO), etc., has a thickness of about 60 to 700, and the second dielectric layer 1 14 is used as a capacitor-free dielectric layer. Referring to FIG. 3D, a second conductive layer 116 is formed on the second dielectric layer 1 (|. The thickness of the second conductive layer 116 is between about 900 and 1 100 angstroms, and the material can be Polycrystalline silicon layer. Then cover a layer of photoresist 117 to define the pattern of the second conductive layer 116, and use the photoresist] 1 1 for etching the military curtain, and remove a portion of the second conductive layer 6 to form s / called second conductive The pattern of layer 116 is used as the upper plate of the capacitor. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) See Figure 3E, using chemical vapor deposition (CVD) A third dielectric layer 118 is deposited on the second conductive layer 116 and the second dielectric layer 114. The material may be silicon dioxide, phosphosilicate glass, borophosphosilicate glass, etc., and its thickness is about 461069 A7. B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention () r is between 7000 and 90,000 angstroms as a protective layer. Then the upper layer of photoresist 119 is placed on the third dielectric layer H8 to define Bit line contact hole (120) and line bonding contact window (ponding pad con tact hole) 1 22. Afterwards, a photoresist 11 9 is used as an etch mask, and dry etching is used to touch the third dielectric layer 118 and the second dielectric layer 114 on the field oxide layer 102. A dielectric layer from ΐ0 to source 108 is formed to form a bit line contact window (| 3 丨 〖丨 丨 116〇〇1 ^ 3 (: '1 | 1〇 丨 .6) 120. At the same time, light The resistance 1 1 9 is 'remaining mask', and a part of the third dielectric layer 118, the second conductive layer 116, the second dielectric layer 114 to the first conductive layer 112 on the source 108 is etched by a dry clock engraving method. To form a bonding pad contact window (ponding pad contact ho 丨 e> 122. Because the resistance 値 is related to the conductivity, area and length: R = pX L / A => R 〇c L where R is the resistance 値, L is Therefore, only the wire bonding contact window 122 needs to be formed at the appropriate position on the field oxide layer 102 according to the resistance requirements of the stacked electrostatic protection circuit manufacturing process. (L) 123 is the first conductive layer 112 to control the resistance of the electrostatic protection circuit. Referring to FIG. 3F, a third conductive layer 124 is formed on the third dielectric layer 11 8 and filled in a bonding pad contact hole 122 and a bit line contact hole 120. The third conductive layer 124 may be made of aluminum-silicon-copper alloy and has a thickness of about 7500. To 8500 angstroms. Then use photolithography to form a layer of photoresist „L. ξ-^ ---- (Please read the precautions on the back before filling in this page)
、tT 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 461069 經濟部中央標隼局員工消費合作社印製 A7 B7 五、發明説明（） 以定義出第三導電層124圖索，並以該光阻爲蝕刻軍幕， 钱刻去除部份第三導電層1:24，以形成打線辞（（ponding pad) 1 26 > 用以封装（package)，與位元線（bitline>128 综舍上述，第4A囷爲依據本發明方法，形成堆疊式 靜電保護電路完成之剖面結構圖。第4B圖爲依據第4A 圖相對應之佈局（Layout)示意圖。在本發明之堆疊式靜電 保護電路製程中，利用一隔離製程，例如區域氧化法 (LOCOS)，在半導體底材矽40上形成一場氧化層（Field Oxide ; FOX}42以定義出一主動區域，接著在半導體底 材矽40上之主動區域内，沈積多晶矽層並以光罩 (Layout)44a爲缺刻單幕’形成M0S元件之閘極44，接 著利用光罩（Layout) 46a進行離子植入，掺雜離子擴散驅 入底#矽40，以形成M0S元件之汲極46和源極48。之 後，在場氧化層（Field Oxide ; FOX)48上陸續形成具堆 疊式電容形式之第一導線層50與第二導線層52,並利用 光罩（Layout>50a形成第一導線層50與第二導線層52圖 案。接著形成一介電層54於其結構之上，.之後利用光罩 (l_ayout)56a ，藉由乾式蝕刻以形成一打線鮮接觸窗 (bonding padcontacthole)56 ° 利用光罩（i_ay〇ut)58a， 藉由乾式蝕刻以形成一位元線接觸窗（bit line ccrnUet hole>58。接著在介電層54上’形成一金屬層以塡如打 線銲接觸窗56與位元線接觸窗58内，並個别利用光罩 (Layout)56a 與光罩（Layout>58a’定義出打線銲（b〇nding 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂 461069 A7 B7 經濟部中央標準局貞工消費合作社印製 五、發明説明（） pad)60圖案與位元線（bit line)58圖案，以完成本發明之 堆疊式靜電保護電路。此時，MOS元件之汲極46與介$ 打線銲接觸窗56與没極46之間之第一導線層5〇，作< 本發明之堆疊式靜電保護電路所需的—等效電阻。 根據上述，由於傳統靜電保護電路架構，需利用離子 植入和熱擴散方法，在半導體底材矽上形成摻雜區域 (MOS元件之汲極或源極）’其中以MOS元件之汲極作爲 靜電保護電路架構中的電阻，往往因爲電阻是藉由擴散所 形成的，因此不易控制電組値，造成誤差過大，且佔用過 多的空間，造成不必要的浪費。本發明之堆疊式靜電保護 電路架構，係利用堆疊式動態隨機存取記憶體（stack DR A Μ)之製程，在打線鋅（bonding pac〇下的空間，形成 由第一導電層與汲極所組成的一等效電阻，藉以節省製作 靜電保護電路時，所需的空間，以提昇整個半導體製程的 積集度。此外’由於電阻値的控制係由第一導電層與没極 所決定，因此可藉由調整製程中打線鮮接觸窗之形成位 置，亦即利用調整介於打線銲接觸窗與汲極之間之第一導 線層長度，而控制靜電保護電路之電阻値，進而得到精確 的靜電保護電路之電阻値。 以上所述僅爲本發明之較佳實施例而已，並非用以限 定本發明之申請專利範園；凡其它未脱離本發明所揭示之 精神下所完成之等效改變或修飾，均應包含在下述之申請 10 木紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） t請先聞讀背面之注意事項存填寫本頁) 訂 461069 A7 B7五、發明説明（）專利範園内。 (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐）, TT This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 461069 Printed by A7 B7, Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention () to define the third conductive layer 124 map, The photoresist is used as an etching military curtain, and a portion of the third conductive layer 1:24 is removed by money engraving to form a (ponding pad) 1 26 > for packaging, and a bitline (bitline) 128 According to the above, Section 4A 囷 is a cross-sectional structural diagram of a stacked electrostatic protection circuit according to the method of the present invention. Figure 4B is a schematic diagram of the layout according to Figure 4A. In the stacked electrostatic of the present invention In the protection circuit process, an isolation process, such as the LOCOS method, is used to form a field oxide layer (Field Oxide; FOX) 42 on the semiconductor substrate silicon 40 to define an active area, and then the semiconductor substrate silicon 40 is formed. In the active area above, a polycrystalline silicon layer is deposited, and the gate 44 of the MOS device is formed with the mask 44a as the notch. Then, the mask 46a is used for ion implantation, and doped ion diffusion drives in. # Silicon 40 to form the drain 46 and source 48 of the MOS device. After that, a first wire layer 50 and a second wire layer 52 in the form of a stacked capacitor are successively formed on the field oxide layer (FOX) 48. Then, a photomask (Layout> 50a) is used to form a pattern of the first wiring layer 50 and the second wiring layer 52. Then a dielectric layer 54 is formed on the structure, and then a photomask (l_ayout) 56a is used to dry-etch To form a bonding pad contact hole 56 °, a photomask 58a is used to form a bit line ccrnUet hole > 58 by dry etching. Next, on the dielectric layer 54 'Form a metal layer such as wire bonding contact window 56 and bit line contact window 58, and use mask (Layout) 56a and mask (Layout> 58a') to define wire bonding (bonding this paper) Standards are applicable to Chinese National Standards (CNS) A4 specifications (210X297 mm) (Please read the precautions on the back before filling out this page) Order 461069 A7 B7 Printed by Zhengong Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs ) 60 pattern and bit line 58 To complete the stacked electrostatic protection circuit of the present invention. At this time, the first lead layer 50 between the drain electrode 46 of the MOS device and the wire bonding contact window 56 and the non-electrode 46 is used as < Required for stacked electrostatic protection circuits-equivalent resistance. According to the above, due to the traditional electrostatic protection circuit architecture, it is necessary to use ion implantation and thermal diffusion methods to form a doped region (the drain or source of the MOS device) on the semiconductor substrate silicon. The drain of the MOS device is used as static electricity. The resistors in the protection circuit structure are often formed by diffusion, so it is not easy to control the power unit, causing excessive errors, occupying too much space, and causing unnecessary waste. The stacked electrostatic protection circuit architecture of the present invention uses a process of stacked dynamic random access memory (stack DR AM) to form a space formed by a first conductive layer and a drain electrode in a space under a bonding pac. An equivalent resistance is formed to save the space required to make the electrostatic protection circuit to improve the integration of the entire semiconductor process. In addition, 'the control of the resistance 値 is determined by the first conductive layer and the electrode, so The resistance of the electrostatic protection circuit can be controlled by adjusting the formation position of the fresh contact window in the manufacturing process, that is, by adjusting the length of the first wire layer between the contact window and the drain electrode of the wire, thereby obtaining accurate static electricity. The resistance of the protection circuit 以上 The above is only a preferred embodiment of the present invention, and is not intended to limit the patent application scope of the present invention; all other equivalent changes made without departing from the spirit disclosed by the present invention Or the modification should be included in the following application. 10 Wood paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm). Please read the notes on the back first Complete this page) Order 461069 A7 B7 V. invention is described in () Patent Park range. (Please read the notes on the back before filling out this page) Order Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs This paper applies the Chinese National Standard (CNS) A4 specification (210X 297 mm)