TW504756B - Post deposition sputtering - Google Patents
Post deposition sputtering Download PDFInfo
- Publication number
- TW504756B TW504756B TW090115749A TW90115749A TW504756B TW 504756 B TW504756 B TW 504756B TW 090115749 A TW090115749 A TW 090115749A TW 90115749 A TW90115749 A TW 90115749A TW 504756 B TW504756 B TW 504756B
- Authority
- TW
- Taiwan
- Prior art keywords
- hole
- sputtering
- layer
- metal
- conductive layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/052—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein
- H10W20/0523—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein by irradiating with ultraviolet or particle radiation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
- H10W20/043—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroplating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/054—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by selectively removing parts thereof
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Physical Vapour Deposition (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US62177300A | 2000-07-21 | 2000-07-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW504756B true TW504756B (en) | 2002-10-01 |
Family
ID=24491571
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW090115749A TW504756B (en) | 2000-07-21 | 2001-06-28 | Post deposition sputtering |
Country Status (3)
| Country | Link |
|---|---|
| AU (1) | AU2001275973A1 (fr) |
| TW (1) | TW504756B (fr) |
| WO (1) | WO2002009149A2 (fr) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004063556A (ja) * | 2002-07-25 | 2004-02-26 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
| TWI435386B (zh) * | 2009-07-21 | 2014-04-21 | 愛發科股份有限公司 | 被膜表面處理方法 |
| CN102820255A (zh) * | 2011-06-08 | 2012-12-12 | 无锡华润上华半导体有限公司 | 一种pvd沉积薄膜的方法 |
| US11162170B2 (en) * | 2014-02-06 | 2021-11-02 | Applied Materials, Inc. | Methods for reducing material overhang in a feature of a substrate |
| US9666516B2 (en) | 2014-12-01 | 2017-05-30 | General Electric Company | Electronic packages and methods of making and using the same |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2602276B2 (ja) * | 1987-06-30 | 1997-04-23 | 株式会社日立製作所 | スパツタリング方法とその装置 |
| US5929526A (en) * | 1997-06-05 | 1999-07-27 | Micron Technology, Inc. | Removal of metal cusp for improved contact fill |
| US6077779A (en) * | 1998-05-22 | 2000-06-20 | Taiwan Semiconductor Manufacturing Company | Multi-step deposition to improve the conformality of ionized PVD films |
| US6187682B1 (en) * | 1998-05-26 | 2001-02-13 | Motorola Inc. | Inert plasma gas surface cleaning process performed insitu with physical vapor deposition (PVD) of a layer of material |
| US6124203A (en) * | 1998-12-07 | 2000-09-26 | Advanced Micro Devices, Inc. | Method for forming conformal barrier layers |
| US6228754B1 (en) * | 1999-01-05 | 2001-05-08 | Advanced Micro Devices, Inc. | Method for forming semiconductor seed layers by inert gas sputter etching |
-
2001
- 2001-06-28 TW TW090115749A patent/TW504756B/zh not_active IP Right Cessation
- 2001-07-18 WO PCT/US2001/022566 patent/WO2002009149A2/fr not_active Ceased
- 2001-07-18 AU AU2001275973A patent/AU2001275973A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| WO2002009149A2 (fr) | 2002-01-31 |
| WO2002009149A3 (fr) | 2002-05-16 |
| AU2001275973A1 (en) | 2002-02-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW518718B (en) | Method for forming damascene interconnection of semiconductor device and damascene interconnection fabricated thereby | |
| US20080190760A1 (en) | Resputtered copper seed layer | |
| JP3291889B2 (ja) | ドライエッチング方法 | |
| US8512526B2 (en) | Method of performing physical vapor deposition with RF plasma source power applied to the target using a magnetron | |
| JP4159615B2 (ja) | バイアススパッタリング方法 | |
| US6350353B2 (en) | Alternate steps of IMP and sputtering process to improve sidewall coverage | |
| US8765596B1 (en) | Atomic layer profiling of diffusion barrier and metal seed layers | |
| US6200433B1 (en) | IMP technology with heavy gas sputtering | |
| TWI427737B (zh) | 形成積體電路結構的方法 | |
| US20020175420A1 (en) | Method of reducing junction spiking through a wall surface of an overetched contact via | |
| TW504756B (en) | Post deposition sputtering | |
| TWI257645B (en) | Barrier metal re-distribution process for resistivity reduction | |
| US5997699A (en) | Insitu faceting during deposition | |
| JP3659653B2 (ja) | 基板上に層を設ける方法およびこれに使用するスパッタリング装置 | |
| KR100227636B1 (ko) | 반도체 소자의 콘택 홀 형성 방법 | |
| TWI827525B (zh) | 物理氣相沉積方法、懸伸減少的方法及沉積銅襯墊的方法 | |
| JP2004131839A (ja) | パルス化された電力によるスパッタリング堆積 | |
| JPH07273046A (ja) | 高融点金属層のｃｖｄ方法およびそのｃｖｄ装置 | |
| US20230113961A1 (en) | Overhang reduction using pulsed bias | |
| WO2006083929A2 (fr) | Reacteur de depot physique en phase vapeur assiste par plasma a puissance de source r.f. appliquee sur une cible plasma | |
| KR100260519B1 (ko) | 반도체 소자의 제조 방법 | |
| JPH09171976A (ja) | 高アスペクト比フィーチャの側面と底部に膜厚制御可能な被膜を付着する方法および装置 | |
| JP3120513B2 (ja) | ドライエッチング方法 | |
| JPH0982665A (ja) | コンタクトプラグの形成方法 | |
| JPH05226284A (ja) | 半導体装置の製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MM4A | Annulment or lapse of patent due to non-payment of fees |