WO2002009149A3 - Pulverisation cathodique apres depot - Google Patents

Pulverisation cathodique apres depot Download PDF

Info

Publication number
WO2002009149A3
WO2002009149A3 PCT/US2001/022566 US0122566W WO0209149A3 WO 2002009149 A3 WO2002009149 A3 WO 2002009149A3 US 0122566 W US0122566 W US 0122566W WO 0209149 A3 WO0209149 A3 WO 0209149A3
Authority
WO
WIPO (PCT)
Prior art keywords
metal
deposited
feature
sputtering
reducing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2001/022566
Other languages
English (en)
Other versions
WO2002009149A2 (fr
Inventor
Valli Arunachalam
Peter L G Ventzek
Shahid Rauf
Dean J Denning
Jiming Zhang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Priority to AU2001275973A priority Critical patent/AU2001275973A1/en
Publication of WO2002009149A2 publication Critical patent/WO2002009149A2/fr
Publication of WO2002009149A3 publication Critical patent/WO2002009149A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/052—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein
    • H10W20/0523—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein by irradiating with ultraviolet or particle radiation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/043—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroplating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/054—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by selectively removing parts thereof

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Procédé servant à améliorer la conformité et à optimiser la couverture de caractéristiques (200) de semi-conducteurs, telles que des trous d'interconnexion (200) et des tranchées. L'exécution d'une étape supplémentaire de pulvérisation cathodique après le dépôt sur une tranche d'au moins une partie du métal (250) permet de limiter les dépôts de métal trop épais à proximité du sommet et au fond d'un trou d'interconnexion (200). La réduction du porte-à-faux au niveau de la partie supérieure d'une caractéristique (200), telle qu'un trou d'interconnexion (200), permet au métal d'atteindre plus facilement les parois latérales et de se déposer sur ces dernières. La diminution de l'épaisseur du métal déposé au fond d'un trou d'interconnexion (200) permet de diminuer la résistance de celui-ci. On peut exécuter l'étape supplémentaire de pulvérisation une seule fois après le dépôt de la totalité du métal. Dans un autre mode de réalisation, on peut déposer une petite quantité de métal, exécuter une étape de pulvérisation, déposer davantage de métal et exécuter d'autres étapes de pulvérisation supplémentaires.
PCT/US2001/022566 2000-07-21 2001-07-18 Pulverisation cathodique apres depot Ceased WO2002009149A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001275973A AU2001275973A1 (en) 2000-07-21 2001-07-18 Post deposition sputtering

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US62177300A 2000-07-21 2000-07-21
US09/621,773 2000-07-21

Publications (2)

Publication Number Publication Date
WO2002009149A2 WO2002009149A2 (fr) 2002-01-31
WO2002009149A3 true WO2002009149A3 (fr) 2002-05-16

Family

ID=24491571

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/022566 Ceased WO2002009149A2 (fr) 2000-07-21 2001-07-18 Pulverisation cathodique apres depot

Country Status (3)

Country Link
AU (1) AU2001275973A1 (fr)
TW (1) TW504756B (fr)
WO (1) WO2002009149A2 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004063556A (ja) * 2002-07-25 2004-02-26 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
TWI435386B (zh) * 2009-07-21 2014-04-21 愛發科股份有限公司 被膜表面處理方法
CN102820255A (zh) * 2011-06-08 2012-12-12 无锡华润上华半导体有限公司 一种pvd沉积薄膜的方法
US11162170B2 (en) * 2014-02-06 2021-11-02 Applied Materials, Inc. Methods for reducing material overhang in a feature of a substrate
US9666516B2 (en) 2014-12-01 2017-05-30 General Electric Company Electronic packages and methods of making and using the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0297502A2 (fr) * 1987-06-30 1989-01-04 Hitachi, Ltd. Méthode et appareil pour la pulvérisation
US5963832A (en) * 1997-06-05 1999-10-05 Micron Technology, Inc. Removal of metal cusp for improved contact fill
US6077779A (en) * 1998-05-22 2000-06-20 Taiwan Semiconductor Manufacturing Company Multi-step deposition to improve the conformality of ionized PVD films
US6124203A (en) * 1998-12-07 2000-09-26 Advanced Micro Devices, Inc. Method for forming conformal barrier layers
US6187682B1 (en) * 1998-05-26 2001-02-13 Motorola Inc. Inert plasma gas surface cleaning process performed insitu with physical vapor deposition (PVD) of a layer of material
US6228754B1 (en) * 1999-01-05 2001-05-08 Advanced Micro Devices, Inc. Method for forming semiconductor seed layers by inert gas sputter etching

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0297502A2 (fr) * 1987-06-30 1989-01-04 Hitachi, Ltd. Méthode et appareil pour la pulvérisation
US5963832A (en) * 1997-06-05 1999-10-05 Micron Technology, Inc. Removal of metal cusp for improved contact fill
US6077779A (en) * 1998-05-22 2000-06-20 Taiwan Semiconductor Manufacturing Company Multi-step deposition to improve the conformality of ionized PVD films
US6187682B1 (en) * 1998-05-26 2001-02-13 Motorola Inc. Inert plasma gas surface cleaning process performed insitu with physical vapor deposition (PVD) of a layer of material
US6124203A (en) * 1998-12-07 2000-09-26 Advanced Micro Devices, Inc. Method for forming conformal barrier layers
US6228754B1 (en) * 1999-01-05 2001-05-08 Advanced Micro Devices, Inc. Method for forming semiconductor seed layers by inert gas sputter etching

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
HASHIM I ET AL: "IMP TA/CU SEED LAYER TECHNOLOGY FOR HIGH ASPECT RATIO VIA FILL BY ELECTROPLATING, AND ITS APPLICATION TO MULTILEVEL SINGLE DAMASCENCECOPPER INTERCONNECTS", PROCEEDINGS OF THE SPIE, SPIE, BELLINGHAM, VA, US, vol. 3508, 1998, pages 58 - 64, XP000910780 *

Also Published As

Publication number Publication date
WO2002009149A2 (fr) 2002-01-31
TW504756B (en) 2002-10-01
AU2001275973A1 (en) 2002-02-05

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