TW523887B - Semiconductor packaged device and its manufacturing method - Google Patents

Semiconductor packaged device and its manufacturing method Download PDF

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Publication number
TW523887B
TW523887B TW090128302A TW90128302A TW523887B TW 523887 B TW523887 B TW 523887B TW 090128302 A TW090128302 A TW 090128302A TW 90128302 A TW90128302 A TW 90128302A TW 523887 B TW523887 B TW 523887B
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semiconductor package
semiconductor
patent application
item
manufacturing
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TW090128302A
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Ji-Chiuan Wu
Jian-Ping Huang
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Siliconware Precision Industries Co Ltd
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Priority to TW090128302A priority Critical patent/TW523887B/zh
Priority to US10/060,564 priority patent/US6590281B2/en
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Publication of TW523887B publication Critical patent/TW523887B/zh
Priority to US10/456,251 priority patent/US6764880B2/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/70—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
    • H10W40/77—Auxiliary members characterised by their shape
    • H10W40/778—Auxiliary members characterised by their shape in encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07141—Means for applying energy, e.g. ovens or lasers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07521—Aligning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/865—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

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Description

523887
五、發明說明（i ) 【發明領域】： 經濟部智慧財產局員工消費合作社印製 本發明係關於一種半導體封裝件’尤指一種具有錫銲 凸塊之四邊形平面無導腳式半導體封裝件（Quad Flat
Non-Lead Package，QFN)。 【發明背景】： 為因應電子產品輕薄短小的開發趨勢，現今半導體裝 置多朝向低成本、咼性能以及高度集積化之方向發展，惟 在半導體裝置之製造成本、性能性及記憶容量上力求改良 之餘，半導體裝置的體積以及整體厚度亦要求儘量精巧， 遂有晶片尺寸封裝（Chip Size Package，CSP )、晶圓層級 封裝（Wafer Level Package )或多晶片模組（Multi_chip Module, MCM )等封裝產品問世。然上述封裝裝置常以多 層印刷電路板（Multi-layer Printed Circuit Board )安置晶 片’各電路板間仰賴金線連結往往因線路過於龐雜而導致 打線困難。 鑒此，美國專利第6，198，171號係揭露一種以導線架取 代印刷電路板作為晶片承載件之QFN半導體封裝件。如第i 圖所示，是種QFN封裝件1係包括一導線架1 〇，該導線架j 〇 具有一晶片座11及環置該晶片座11外圍之多數導腳12，經 半餘或沖麼方法令各導腳12内端122形成一厚度小於導腳 12他部之凸出部123 ; —半導體晶片14，採電路面14〇朝下 方式黏晶打線，以供該晶片14與該導腳12凸出部123底面 121形成電性導接關係，以及一包覆該晶片座11、晶片μ、 金線180及填滿該導腳12凸出部123底部空隙之封裝膠體 本紙張尺度適用中國國家標翠（CNS)A4規格（210 X 297公釐） 16425 -----------•裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 523887 A7 __ _B7 --------二____ ______ 五、發明說明（2 ) 19° 降低凸出部U3之導腳12厚度可為該凸出部123底端 開設一打線空間，遂當該晶片14以電路面14〇向下方式與該 凸出部U3導電連結時，晶片14距離導㈣之金線連接端 (未圖示）很近，故能降低打線弧長，縮短電訊傳導路徑 繼而提昇封裝件之電性功能；同時，線弧安置於導腳以 部亦會令晶片U上方的空間大為增加，丨而容納更多晶片 以倍增封裝產品之功能及處理速度。第2圖即顯示經過改良 之多晶片結構1 ’如圖所示，該結構！的特點係在原晶片14 上方另增設一尺寸較大之第二半導體晶片15，且該第二晶 片15係以部分電路面15〇與原晶片14相接。同時，為使線路 複雜性降低兼具備優良電性品質，該第二晶片15電路面 上並形成有複數個金屬銲塊16以供該晶片15與該凸出部 123頂面120電性連結。 經濟部智慧財產局員工消費合作社印製 <請先閱讀背面之注意事項再填寫本頁) 惟上述多晶片半導體裝置之製作係先將該第二晶片 15妥善銲接到導腳12凸出部123頂面12〇，方能實施原晶片 14的銲線製程。故而，如第3圖所示，當打線機18 ( Bonder)滑移到導腳12打線位置124時，相對於該打線位置 124背侧之導腳12頂面12〇實已植妥多數金屬銲塊16;又因 該等銲塊16乃係一質脆合金材料製成，導致金線18〇壓接時 該打線機18施予該打線位置124之向下壓力會順勢傳遞到 金屬銲塊16上，引發銲塊16結構碎裂甚至危及該第二晶片 15的電性銲接品質。 【發明概述】： 本紙張尺度適用中國國家標準(CNS)A4規格（210 X ?Q7公蝥） ·； -—^- 523887 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 A7 ___B7五、發明說明（ 本發明之主要目的你 A /5 Λί ^ ^ 4* 、，、一種導腳底面打線區域與 〃反側之知塊植接位置互呈錯位隔 得與該銲塊銲接位置完全避開 施力方向 半導體封裝件。 避開以岐塊文屋裂損之QFN 再目的係提供一種導腳底面打線區域與 中，之曰塊植接位置互呈錯位隔開’以免鲜塊作業環境 之㈣半導體封裝件。貝到打線位置而影響金線銲接信賴性 之二目的’本發明係提供-具有金屬銲塊至+複數Μ #，係包含·—導線架，該導線架係由 m:所構成’且鄰近晶片安置區域之導腳底面 有-階梯狀結構(steppedstructure) :於導腳他部之凸出段，其中，該凸出段具有一第一：面 相對第一表面，且該第二表面上已預先定義出 銲接區域俾與該第一矣 金線 =位置錯位隔開；—第-晶片’係以其作用表面二 線銲接區域打線導接；-第二晶片，藉其作用I ^成之多數金屬銲塊將該晶片電性竊接至該鲜塊植接 置上’以及一用以包 等導腳部分外露之封袭膠體。第一“金線並令該 之凸tr:r係於各導腳底面上開設厚度小於導腳 一表面之銲塊植接位 第 時該打線機施懕方A 互錯位隔開，因此執行打線作業 :__向會完全避開該銲塊植接位置’金線壓 本紙狀度適^國家標準（C^iiTTK) x 297公爱）
I 訂 3 16425 523887 經濟部智慧財產局員工消費合作社印製 -— /¾ tl ' ΪΓ ^ ^ 本紙張&度適用中國國家標準規格（210 d97公釐） A7 i、發明說明u ) 接時產生之向下壓力不會對遠距之金屬銲塊造成壓迫，遂 可免除銲塊壓裂之虞。再者’該導腳打線部位因遠離該銲 塊植接位置而不易受銲塊作業環境使用之溶液（如助鲜劑 (Flux )、酸鹼清洗液等）所污染，有 β双維持導腳預鍍表面 之完整以提供金線更優良的銲接品質。 【圖式簡單說明】： 以下茲以最佳具體例配合所附圖式詳細揭露本發明 之特點及功效： 第1圖係為美國專利第6，198，171號之qfn半導體封裝 件之剖面示意圖； 第2圖係為習知打線與銲塊接置位置上下正對之qfn 半導體封裝件之剖面示意圖； 第3圖係為習知金線與鲜塊接置位置上下正對之半導 體封裝件執行打線作業時之局部放大示意圖； 第4圖係為本發明第一實施例之qfn半導體封裝件之 剖面示意圖； 苐5A至5D圖係為本發明第一實施例之qfn半導體封 I件之整體製作流程示意圖； 第6圖係為本發明第二實施例之QFN半導體封裝件之 剖面示意圖；以及 第7圖係為本發明第三實施例之QFN半導體封裝件之 剖面示意圖。 【發明詳細說明】 以下即配合_讀至)詳細說明本發明QFN半導體
Lt 4 μ 1 16425 — — — — — — — — — — I ·1111111 ^ I I I I I--I (請先閱讀背面之注意事項再填寫本頁) 523887 A7 五、發明說明（ (讀先閱讀背面之注意事項再填寫本頁) 封裝件之實施例，惟為清楚揭露本發明之製作流程，遂採 雙曰曰片半導體封裝件為例釋之。然而，該實施例之製法亦 係廣泛適用於所有導腳連接型（Lea(j frame Based)半導體 封裝件’且在不增加封裝結構之整體高度下，晶片容置數 量得為三片甚至更多。 請參閱第4圖，該圖係為本發明第一實施例之qFN半導 體封裝件之剖面示意圖。如圖所示，該半導體封裝件2係包 含有一導線架20,該導線架20具有一位於中央之晶片座21 及環設於該晶片座21外圍之多數導腳22，且鄰近該晶片座 21之内導腳22底面221上設有階梯狀結構（stepped
Structure )以形成一小於導腳22他部厚度之凸出段223 ; — 第一晶片24,係以其作用表面240向下方式黏接至該晶片座 21上’一弟二晶片25’以其作用表面250上形成之多數金屬 ~塊26將該晶片25與該凸出段22 3之導腳22頂面220形成電 性藕接；多數金線280,俾供該第一晶片24導電連結於該凸 出段223導腳22底面221上且其打線位置係與該金屬銲塊26 植接部位互呈錯位隔開；以及，一用以包覆該第一、第二 經濟部智慧財產局員工消費合作社印製 晶片24,25並令該等導腳22底面221部分外露之封裝膠體 29 〇 以下即以第5A圖至5D圖詳細說明本發明qfn半導體 封裝件之整體製作流程。 如第5A圖所示，備一以銅、銅合金或類似金屬材質製 成之導線架20，該導線架20係由一晶片座21以及環設於該 晶片座21外圍之多數導腳22所構成，其中，該導腳22靠近 523887 A7 B7___ 五、發明說明（6 ) <請先閱讀背面之注意事項再填寫本頁) 晶片座21部分係定義為内導腳22(標號同導腳22)。而後， 利用習知半蝕（Half-Etching)或沖壓（punch)技術於該内導 腳22上製作至少一階梯狀結構（Pepped Structure )以形成 一自導腳22中央向該内導腳端222延伸之凸出段223，俾令 該凸出段223厚度明顯小於導腳22他部厚度以具備一空間 23提供打線線弧收納；並且，該凸出段223須具有足夠長度 之第一表面220以及相對之第二表面221，致使該第一表面 220保留充足面積而可預先定義出互不重疊之金線銲接區 域224以及銲塊對應區域225,且該銲塊對應區域225係與該 第二表面221上之銲塊植接位置226 (如圖中銲塊假想線所 示）上下正對，俾令該銲塊植接位置226與其反側之金線銲 接區域224互呈錯位關係。 經濟部智慧財產局員工消費合作社印剩衣 之後，如第5B圖所示，預製一第一晶片24及一第二晶 片25，俾使該等晶片24,25各具有一作用表面24〇,25〇 (即 舖設有多數電子電路與電子元件之表面）及一非作用表面 241，251 ;其中，該第二晶片25之作用表面25〇上已預先植 妥多數金屬銲塊26以藉之提供該晶片25與導腳22形成電性 導接。待該第一晶片24以其作用表面240朝下黏接至該晶片 座21後，於該第一晶片24非作用表面24 i上塗佈一膠黏層 (未圖示），即可藉由該等金屬銲塊26將該第二晶片25銲接 至該凸出段223上而使該金屬銲塊26位於該銲塊對應區域 225之正上方。 接著，如第5C圖所示，將該封裝件半成品2，移入一治 具（Jig) 27内夾固翻轉並施以預熱；該治具η係包含一上 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公f ) 523887 A7 B7 五、發明說明（7 ) /訇身按对负面之注意事項再填寫本頁) 壓板270及一得與該上壓板270同時夾合之下壓板271所構 成，且該下壓板271對應於該導腳22凸出段223位置係具有 一延長平台部272以便支撐該凸出段223以免導腳22發生晃 動。而後，如第5D圖所示，用一傳統打線機28( Wire Bonder) 將多條金線280自該第一晶片24作用表面240打線至導腳22 凸出段223之金線銲接區域224上進行銲固壓接。由於導腳 22底面221上該金線銲接區域224與導腳22第一表面220上 之銲塊植接位置226距離甚遠且互呈錯位，因此打線機28 施予該金線銲接區域224之向下壓力不會影響該銲塊植接 位置226而能免除金屬銲塊26壓裂之虞。再者，該金線銲接 區域224與銲塊植接位置226相隔一距離，是以，執行銲塊 銲固時施加之溶蝕溶液（如助銲劑（Flux )、酸鹼清洗液等） 不易污染該金線銲接區域224而可確保金線280與該金線銲 接£域224間之鲜接品質，同時該凸出段223之製作乃完全 沿用習用方式無須額外增加設備，遂亦不致增加導線架之 製作成本。 經濟部智慧財產局員工消費合作社印製 第6圖及第7圖係分別顯示本發明半導體封裝件之另 二實施例，該等實施例之結構倶與前述第一實施例大致相 同，惟其不同處僅於該第二晶片35之非作用表面351係直接 外露（如第6圖所示）或於其上另行增置散熱件37 (如第7 圖所示）。如圖所示，該凸出段323長度增加迫使導腳32外 露之散熱面積相對地縮減，利用晶片3 5非作用表面3 5丨外露 或增設散熱件37方式將能補強封裝件3之整體散熱效能，進 而有效維護雙晶片（甚至多晶片）封裝件之晶片性 本紙張尺度適用中國國家標準（CNS)A4規袼（21〇x 297公釐） 7 16425 經濟部智慧財產局員工消費合作社印製 523887 A7 B7 五、發明說明（8 ) 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之實質技術内容，本發明之實質技術内容係廣義 地定義於下述之申請專利範圍中。任何他人所完成之技術 實體或方法，如若與下述之申請專利範圍所定義者為完全 相同、或為一種等效之變更，均將視同涵蓋於此專利範圍 内。 【符號標號說明】： ------------裝--------訂--- (請先閱讀背面之注意事項再填寫本頁) 禮· 1，2,3 半導體封裝件 2， 封裝件半成品 10,20 導線架 11,21 晶片座 12,22,32 導腳 120,220 凸出段第一表面 121,221,321 凸出段第二表面 122,222 内導腳端 123,223,323 凸出段（部） 124 導腳打線位置 224 金線銲接區域 225 銲塊對應區域 226 銲塊植接位置 23 凸出段空間 14,24 第一晶片 140 電路面 240 第一晶片作用表面 241 第一晶片非作用表面 15,25,35 第二晶片 150,250 第二晶片作用表面 251,351 第二晶片非作用表面 16,26 金屬銲塊 27 治具 270 上壓板 271 下壓板 272 延長平台部 37 散熱件 18,28 打線機 180,280 金線 19,29 封裝膠體 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 8 16425

Claims (1)

  1. B8 C8 D8
    經濟部智慧財產局員工消費合作社印製 523887 々、申請專利範圍 1· 一種半導體封裝件，係包含： -導線架，其具有複數條導腳，於該底面上並 一小於導腳厚度之凸屮jyt ο η »1, 又之凸出段，且該凸出段之一第一表面上 係預先定義出至少一箆_扭处π A ^ v弟鲜接區域，俾與該凸出段相對 之第二表面上形成之第二銲接區域錯位隔開； 至少-第-半導體晶片，其具有—作用表面及一非 並以該作用表面向下方式藉多數銲線連結該 晶片至該第—銲接區域，俾令該第-晶片與 該導腳間形成電性藕接關係； 至夕帛_半導體晶片，藉多數導電元件將該第二 晶片電性導接至該第二銲接區域上；以及 封裝膠m包覆該等半導體晶片及該等導電 元件。 2.如申請專利範圍第i項之半導體封裝件，其中，該半導 體封裝件係一 QFN半導體封裝件。 3·如申請專利範圍第1項之丰 千等體封裝件，其中，該導線 架之材質係選自如鋼、銅人冬 』幻口金或類似金屬所組組群之一 者所製得。 4·如申請專利範圍第1項之半導# 不π心千等體封裝件，其中，該凸出 段係自該導腳中央向内沿伸 1甲主曰日片周圍之導腳内端以 構成一階梯狀結構。 5·如申請專利範圍第1項之半導俨 ^ <干等體封裝件，其中，該導電 元件係為質脆金屬銲塊。 」:如申凊專利耗圍第i項之半導體裝件，其令，該凸 本紙張尺度適用中國國家標準（CNS)A4規袼（210 X 297公查—〜一 访 9 16425 ------------------------I ! (請先閱讀背面之注意事項再填寫本頁) 523887 A8 B8 C8 D8
    經濟部智慧財產局員工消費合作社印製 申請專利範圍 二表面上形成有一完全正對於該第二銲接區域之~塊對應區域。 奮專利範圍第6項之半導體封裝件，其中，該銲塊 對應區域與該第一銲接區域互不重叠。 8.=Γ範圍第1項之半導體封心，其中，該打線 區域上銲結壓接。 金線對位至該第一銲接 9·如申請專利範圍第5項之半導體封裝件，其中， 機會施予該第一銲接區域一向下壓力。 ^ 、’、 10· 一種半導體封裝件製法’係、包含以下步驟： ，備-導㈣’其具有複數條導腳，於該底面 ^小於導腳他料度之凸出段，且該凸麵之 面上係預先定義出至少一第—銲 段之一相對第二表面上形成之笛良 早一該凸出 開； y成之第二銲接區域錯位隔預製至少一第一半導體晶片 該第-主道曰u # 乐一牛導體晶片，待 Λ第一丰導體晶片藉由多數導電元 一録接_ 電座導接至該第 一鲜接£域後，將該導線架移入一户罝 業，搜你4够 σ ’、内實施録線作 業俾使該弟一半導體晶片與該第一錄 藕接關係；以及 鉢接區域形成電性 最後用一封裝膠體包覆該第一與 以及該等導電元件。 *、 一半導體晶片 11.如申請專利範圍第1〇 本莫^ 導體封裝件製法，1中，該 丰導體封裝件係一 QFN半導體扭 八中 ㈣張尺度_，國家標準（⑽石規格（21G x 297公^ 10 16425 (請先閲讀背面之注意事項再填寫本頁) 0 ϋ I n —訂--------- 523887
    六、申請專利範圍 12=申請專利範圍第1G項之半導體封裝件製法，其中，該 V線架之材質係選自如鋼、銅合金或類似金屬所紐組群 之一者所製得。 (請先閱讀背面之注意事項再填寫本頁) 13·如申請專利範圍第1G項之半導體封裝件製法，其中，該 凸出奴係自該導腳中央向内延伸至晶片周園之導腳内 端以構成一階梯狀結構。 14·如申請專利範圍第1〇項之半導體封裝件製法，其中，該 導電元件係為質脆金屬銲塊。 15·如申請專利範圍第1〇項之半導體封裝件製法，其中，該 凸出部第二表面上形成有一完全正對於該第二銲接區 域之銲塊對應區域。 16·如申請專利範圍第15項之半導體封裝件製法，其中，該 銲塊對應區域與該第一銲接區域互不重疊。 17. 如申請專利範圍第1〇項之半導體封裝件製法，其中，該 /〇具係包含一上壓板及一相對之下壓板，且該下壓板對 應於該導腳處係形成有一提供該凸出段支撐之延長平 台部。 經濟部智慧財產局員工消費合作社印製 18, 如申請專利範圍第1〇項之半導體封裝件製法，其中，該 打線方式係藉一傳統打線機將多數金線對位至該第一 銲接區域上銲結壓接。 19·如申請專利範圍第18項之半導體封裝件製法，其中，該 打線機會施予該第一銲接區域一向下壓力。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 11 16425.
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