TWI282929B - Generating a logic design - Google Patents

Generating a logic design Download PDF

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TWI282929B
TWI282929B TW091119566A TW91119566A TWI282929B TW I282929 B TWI282929 B TW I282929B TW 091119566 A TW091119566 A TW 091119566A TW 91119566 A TW91119566 A TW 91119566A TW I282929 B TWI282929 B TW I282929B
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design
instructions
computer
machine
generate
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William R Wheeler
Matthew J Adiletta
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Intel Corp
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/32Circuit design at the digital level
    • G06F30/33Design verification, e.g. functional simulation or model checking
    • G06F30/3308Design verification, e.g. functional simulation or model checking using simulation
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/32Circuit design at the digital level
    • G06F30/323Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/32Circuit design at the digital level
    • G06F30/33Design verification, e.g. functional simulation or model checking

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

1282929 A7 B7 五、發明説明(1 ) 技術領域 本發明有關積體電路設計工具。 發明背景 積體電路(integrated circuit,1C )之邏輯設計通常包括示 意設計或文字設計。示意設計為將具有邏輯元件之電腦晶 片顯示成二維圖形。邏輯元件為狀態元件(如,正反器 (flip-flops)、閂(latch)等)或組合元件(如及閘(AND gate),非或閘(NOR gate))。各種幾何圖形代表該邏輯元 件。拉進或拉出該邏輯元件的線通常代表輸入、輸出、時 鐘(clock)、或啟動(enabling)訊號。連接該幾何形狀的線 指示於該邏輯元件間之功能邏輯關係。 一文字呈現(representation )描述了使用」維文字線之電 腦晶片的邏輯元件。文字呈現以硬體描述語言(HDL )來被 使用,其允許設計師於在矽上形成該邏輯前可模擬邏輯設 計。該語言的範例包括Vedlog與非常高階設計語言(Very High-Level Design Language,VHDL)。使用這些語言,一 設計師可撰寫程式碼來模擬一邏輯設計且依序執行該程式 碼來確定該邏輯設計是否可正確執行。 標準電腦語言還可用來模擬一邏輯設計。可使用之標準 電腦語言的一範例為C++。 圖式之簡述 圖1為顯示產生一邏輯設計程序之流程圖。 圖2為圖1程序可在其上執行之電腦系統的區塊圖。 -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐)
裝 訂
1282929 A7 B7 ) 五、發明説明(2 圖式之詳述 參考圖1,程序1 0如用於產生包括示意設計與文字設計 特徵之邏輯設計而被顯示。程序1 〇可使用在一電腦或其 他型態機器(如下文將以較詳細的細節來描述)上執行之電 腦程式來被實作。該程序」〇存取代表一積體電路 (integrated circuit,1C )之完整可見模型且嵌入一組合一維 資料區塊。該組合資料區塊允許將文字設計混合成二雉呈 現。此外,一組抽象可被程序1 〇來使用以縮短該統合資 料庫的發展時間。該統合資料庫可被設計師與I C設計的 實作者用來產生一 1C而不需參考兩個分開且不相連的設 計規劃(scheme )。 該統合資料庫在為I C設計二維呈現之暫存器移轉圖 (Register Transfer Diagrams,RTD )中來被呈現。RTD 為例 示一 I C設計所有狀態元件之階層圖,同時允許一使用者將 該組合邏輯抽象化成簡單箱(simple box)。RTD簡要地傳 達(1 )所有狀態元件,(2 )將於狀態元件間被完成工作的分 割(partition ),( 3 )通過狀態元件之資料流,(4 )位於階層 層級内與之間的設計分割與邏輯組織,(5 )該設計之意圖, 與(6)訊號資訊。 在運作上,程序1 0產生組合資料區塊(丨2 )。I C設計師決 定於I C設計之特別部份中一組合元件是需要的。使用一 文字描述以呈現該組合元件。文字描述最好是用簡化形式 來避免由在設計過程中必需解釋之複雜文字描述所引進的 複雜度。因而,該組合資料區塊包括用簡化形式來便利對 -5- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 1282929 A7 __ B7__ 五、發明説明(3 ) 二維或圖形階層規劃的整合之文字描述。該簡化遵循一組 設計掏取規則。例如,一組合資料區塊於Verilog中如下 文來呈現: always @ () begin case (f2一ctx一w) "synopsys parallel一case 3’b000: next—seq一thd—w = 3’b001 ; 3丨bOOl: next—seq一thd—w = 3*b010 ; 3’b010: next—seq—thd—w = 3’b011 ; 3丨bOll: next一seq—thd一w = 3’bl00 ; 3’bl00: next_seq_thd一w = 3’blOl ; 3’bl01: next—seq—thd一w = 3’bllO ; 3’bllO: next一seq—thd一w = 3’blll ; 3’blll: next一seq一thd一w = 3’bOOO ; endcase end 用來簡化於本範例中之組合資料區塊的設計擷取規則包 括:(1)避免使用!g告(declaration )與(2)避免於敏感性 (sensitivity )表列中的項目(entry )。如果使用宣告與項目 時,若因I C設計更動且該組合區塊被影響,則這些欄位 必需被更改。藉由不允許於該組合資料區塊之敏感性表列 中的宣告與項目,程序1 〇減少了於丨c發展程序期間内j c 設計師更改這些攔位的需要。換言之,當於I C設計發生 更動時’ IC設計師不需任何手動更動來應對這些更改。 -6- 本纸張尺度適用中國國家標準(CNS) A4規格(210X297公爱) 1282929 A7 ______ B7 五、發明説明(4 ) 藉由設定這些限制,當設計更改發生時,人為錯誤的機會 較少。其他設計擷取規則於發展設計過程中可被實作來簡 化該組合資料區塊與減少不必要的更動。 程序1 0輸入該組合資料區塊(i 4)。於本具體實施例 中,這藉由以下所述經由一輸出入介面(如滑鼠、鍵盤)來 於一電腦系統上被執行。當該組合資料區塊被輸入到該邏 輯設计系統時,程序1 〇檢查以確保產生該組合資料區塊 之設計擷取規則從12(16)來被遷循。程序1〇通知設計師 一錯誤是否發生(1 8 )。例如,錯誤訊息顯示在〗c設計師 的電腦螢幕上。 程序10使用一組抽象來便利統合資料庫(2〇)的發展。 該組抽象為各種邏輯組件的縮小呈現。例如,比較器 (comparator)為數千個電晶體。於該ic設計每個電晶體的 產生或攜載與每個電晶體所結合的資料會很麻煩。該縮小 呈現為具有輸入與輸出之區竣圖。抽象可從程式館來例舉 (instantiate ),因此從一抽象產生一邏輯元件對設計師是 很快且容易來做。例如,使用程序1 0之I c設計工具位在 個人電腦上且該工具在微軟視窗(MS_Wind〇w@)環境中操 作。'如果該I C設計師確定在該設計中,比較器是必要 的,該設計師下拉該應用程式中的選單且選擇—比較器。 後績的箱會出現並且該設計師需檢視該區塊來得出該比較 器所需參數(如,輸入)^藉由使用該組抽象,於該設計師 選擇該邏輯組件之後,其被儲存在該統合資料庫中。 程序1 0將該組合資料區塊嵌入到該二維示意演示之中 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 1282929 A7 _ B7 五、發明説明(5 ) 以完成該統合資料庫(2 2 )。因而,該統合資料庫為該j c 的完整呈現並且可在RTD中呈現。 於Ί C設計過程期間内,設計師一般在設計過程的開始就 實作區塊圖且使用一維文字描述之RTL碼來發展該設計。 該區塊圖通常並非被保持著最新的版本,因為設計師會將 所有更動對RTL來進行,因而RTL成為該設計碼。由程序 1 〇所產生之統合資料庫在整個設計過程間藉由將所有設 計資料保存在一個位置來確保1(:設計的置 (configuration)管理。因而,因為經常反覆進行示意與文 字設計規劃的調和,此邏輯設計規劃減少了發生於先前實 作與設計模型間所發生的傳統混沌不明。以具有統合資料 庫,程序1 0允許從單一位置來產生〇+與Veril〇g碼。其 還允許從文字與可見元件來產生可合成Verilog。 圖2顯示使用程序1〇來產生一邏輯設計之電腦4〇。電腦 4 0包括一處理器4 2、記憶體4 4、與儲存媒介4 6 (如硬 碟)。儲存媒介46儲存定義一邏輯設計之資料52、用於實 作該邏輯設計之圖形館(graphic library) 50、機器可執行指 令4 8、其可被處理器4 2從記憶體4 4讀出而對資料5 2來執 行程存1 0。 然而,程序10非受限於使用圖2的硬體與軟體;可在任 何計算或處理環境中找到其應用性。程序1 〇可用硬體、 軟體、或兩者的組合來被實作。程序1 〇可用在可程式化 電腦或包括處理器、該處理器可讀取的儲存媒介(包括依 電性(volatile)或非依電性記憶體且/或儲存元件)、至少一 -8- 本紙張尺度適用中國國豕標準(CNS) A4規格(210 X 297公爱) 1282929 A7 - ~—— ________ B7_ 五、發明說明(6~~ "~ ----— =入裝置、與一個或更多輸出裝置之其他機器上執行的電 腦程式來實作。程式碼可應用到使用如滑鼠或鍵盤等輸2 裝置來輸入的資料來執行程序10且產生一模擬。 居每個私式可用咼階程序(procedural)或物件導向 (〇bject-onented)程式語言來與一電腦系統溝通而被實 作。然而,該程式可用組合或機器語言來被實作。該語言 可為編譯(compi】ed )或解譯(interpreted )語言。 每個電腦程式可被儲存在製造的物品上(如c D氺〇 M、硬 莱或磁碟),其可被一奴性或特殊目的可程式化機器來 讀取以在當該儲存媒介或裝置被該機器讀取而來執行程序 10時,配置與操作該機器。程序10也可實作成機器可讀 儲存媒介,以電腦程式來配置,當執行時電腦程式中的^ 令讓該機器根據程序1 〇來運作。 本發明不限定於以上所述之特定具體實施例。例如,程 序1 0不受限於將一維設計淚入到二維設計。程序可為任 何η維設計,以嵌入到(n + m )維設計,其中n仝丨且mi。 程序1 〇不受限於以上所述之電腦語言,如Veril〇g、c++、 與VHDL。其可使用任何合適的電腦語言來被實作。程序 1 〇也不受限於圖1中所述的順序。即程序1 〇的區塊可以不 同於所顯示的順序來產生一可接受的結果。 其他未於本文中所述之具體貫施例也在以下申請專利範 圍之内。 -9- 本紙張尺度適用中國國家標準(CNS) A4规格(210 X 297公釐) 1282929 A7 B7 五、發明説明(7 ) 序號 元件參照編號 原文 中文 1 10 Process 程序 2 12、14 Combinatorial data block 組合資料區塊 3 20 Unified database 統合資料庫 4 40 computer 電腦 5 42 processor 處理器. 6 44 memory 記憶體 7 46 Storage medium 儲存媒介 8 48 Machine-executable instructions 機器可執行指令 9 50 Graphic library 圖形館 10 52 Data 資料 -10- 本紙張尺度適用中國國家標準(CNS) A4規格(210’x 297公釐)

Claims (1)

  1. ί9566號專利申請案 清專利範圍替換本(95年10月) Α8 Β8 C8 D8
    產生一邏輯設計以用於設計一積體電路(I C )之方 法,該方法包含以下步驟: 產生一電腦指令, 從記憶體輸入該電腦指令;以及 將嵌入該電腦指令於該邏輯設計之一二維示意呈現内 以產生該邏輯設計之一統合資料庫呈現,該電腦指令缺 乏宣告與敏感性表列中之項目; 其中該二維示意呈現包括一組暫存器移轉圖 (RTD)。 2. 如申請專利範圍第1項之方法,進一步包含當擴取使用 該電腦指令之資料達反一組設計擷取規則時,通知一設 計師。 3. 如申請專利範圍第1項之方法,進一步包含從該統合資 料庫來產生C++。 4. 如申請專利範圍第3項之方法,進一步包含從該統合資 料庫來產生Verilog。 5. 如申請專利範圍第1項之方法,進一步包含從該統合資 料庫來產生可合成Verilog。 6 .如申請專利範圍第1項之方法,進一步包含致使一使用 者可藉由修改該電腦指令改變該邏輯設計。 7. —種儲存可執行指令以產生一邏輯設計來用於設計一積 體電路(I C )之機器可讀取媒體,該指令引起一機器: 產生一電腦指令; 將該電腦指令嵌入在該邏輯設計之一二維示意呈現内 80263-951030.doc - 1 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 1282929 i D8 六、申請專利範圍 以產生該邏輯設計之一統合資料庫呈現,該電腦指令缺 乏宣告與敏感性表列中之項目; 其中該二維示意呈現包括一組暫存器移轉圖(RTD)。 8. 如申請專利範圍第7項之機器可讀取媒體·,進一步包含 指令引起一機器以輸入該電腦指令。 9. 如申請專利範圍第7項之機器可讀取媒體,進一步包含 指令引起一機器以當擷取資料達反一組設計擷取規則 時,通知一設計師。 10. 如申請專利範圍第7項之機器可讀取媒體,進一步包含 指令引起一機器以從該統合資料庫產生C++。 11. 如申請專利範圍第7項之機器可讀取媒體,進一步包含 指令引起一機器以從該統合資料庫產生Verilog。 12. 如申請專利範圍第7項之機器可讀取媒體,進一步包含 指令引起一機器以從該統合資料庫產生可合成Verilog。 13. 如申請專利範園第7項之機器可讀取媒體,進一步包含 指令引起一機器以致使一使用者可藉由修改該電腦指令 改變該邏輯設計。 14. 一種用於產生一邏輯設計以用在設計一積體電路(I C )之 裝置,包括: 一記憶體,其儲存可執行指令;以及 一處理器,其執行該指令以: 產生一電腦指令;以及 將該電腦指令嵌入在該邏輯設計之一二維示意呈現 内以產生該邏輯設計之一統合資料庫呈現,該電腦指 80263-951030.doc - 2 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐). A8 B8 C8 D8
    1282929 六、申州專利範圍 令缺乏宣告與敏感性表列中之项目· 其中該二維示意呈現包括—组暫存器移轉圖(rtd)。 15.如:請專利範圍第“項之裝置’進—步包含指令來輸入 該電腦指令。 ’進一步包含指令來當擷 時,通知一設計師。 ’進一步包含指令來從該 16.如申請專利範圍第1 4項之裝置 取資料達反一組設計擴取規則 如申請專利範圍第i 4項之裝置 統合資料庫產生C++。 步包含指令來從該 步包含指令來從該 18·如申請專利範圍第1 7項之裝置,進— 統合資料庫產生Verilog。 19·如申請專利範圍第1 4項之裝置,進— 統合資料庫產生可合成Verilog。 20.如申請專利範圍第1 4項之裝置,進—止二 ,+ m . 步匕含指令以致使 一使用者可藉由修改該電腦指令改變 又磺邏輯設計。 80263-951030.doc , 3
    本纸浪尺度適用中國國家標準(CNS) A4規格(210X297公董).
TW091119566A 2001-08-29 2002-08-28 Generating a logic design TWI282929B (en)

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