TWI456385B - 資料處理裝置 - Google Patents

資料處理裝置 Download PDF

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Publication number
TWI456385B
TWI456385B TW098122014A TW98122014A TWI456385B TW I456385 B TWI456385 B TW I456385B TW 098122014 A TW098122014 A TW 098122014A TW 98122014 A TW98122014 A TW 98122014A TW I456385 B TWI456385 B TW I456385B
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TW
Taiwan
Prior art keywords
memory
cpu
power supply
data processing
cache memory
Prior art date
Application number
TW098122014A
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English (en)
Other versions
TW201009561A (en
Inventor
Sadao Miyazaki
Osamu Ishibashi
Rikizo Nakano
Yoshinori Mesaki
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of TW201009561A publication Critical patent/TW201009561A/zh
Application granted granted Critical
Publication of TWI456385B publication Critical patent/TWI456385B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/202—Non-volatile memory
    • G06F2212/2024—Rewritable memory not requiring erasing, e.g. resistive or ferroelectric RAM
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/22—Employing cache memory using specific memory technology
    • G06F2212/222—Non-volatile memory
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)

Claims (6)

  1. 一種資料處理裝置，包含：一個包括一暫存器的中央處理單元(CPU)；一個快取記憶體；一個被構築來與該快取記憶體交換資料的主記憶體；一個被構築來控制在該主記憶體與該快取記憶體之間之資料交換的控制部份；及一個被構築來把電力供應到該暫存器、該快取記憶體、與該主記憶體的電源供應部份；其中，該暫存器、該快取記憶體、與該主記憶體是各被構築來在沒有被供應有來自該電源供應部份的電力之下儲存資料並維持該儲存資料在其內；其中，該控制部份是被構築來在一不正常發生於該電源供應部份時停止該CPU存取該暫存器、該快取記憶體、與該主記憶體；其中，該快取記憶體是為一非依電性記憶體。
  2. 如申請專利範圍第1項所述之資料處理裝置，其中，當該電源供應部份在該不正常發生之後復原時，該控制部份致使該CPU恢復由該暫存器、該快取記憶體、與該主記憶體所維持之儲存資料的處理。
  3. 如申請專利範圍第1項所述之資料處理裝置，其中，該CPU被構築來在該不正常發生時儲存該CPU的控制訊號和該CPU的位址訊號於該暫存器中。
  4. 如申請專利範圍第1項所述之資料處理裝置，其中，該CPU 被構築來執行一個包括數個步驟的程式及當該不正常發生時停止執行該程式，其中，該CPU被構築來當該電源供應部份在該不正常發生之後復原時恢復該程式的執行；其中，該程式的執行是自一個直到該不正常發生為止是處於執行狀態的持續步驟恢復或者是自一個在該持續步驟之前一步的步驟恢復。
  5. 如申請專利範圍第1項所述之資料處理裝置，其中，該暫存器、該快取記憶體、該主記憶體各是為非依電性記憶體。
  6. 如申請專利範圍第1項所述之資料處理裝置，更包含：一個備援電源供應器；其中，該暫存器、該主記憶體各是為當該不正常發生時電力係從該備援電源供應器供應的依電性記憶體。
TW098122014A 2008-08-29 2009-06-30 資料處理裝置 TWI456385B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008222243A JP5581577B2 (ja) 2008-08-29 2008-08-29 データ処理装置

Publications (2)

Publication Number Publication Date
TW201009561A TW201009561A (en) 2010-03-01
TWI456385B true TWI456385B (zh) 2014-10-11

Family

ID=41727063

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098122014A TWI456385B (zh) 2008-08-29 2009-06-30 資料處理裝置

Country Status (4)

Country Link
US (1) US8135971B2 (zh)
JP (1) JP5581577B2 (zh)
CN (1) CN101661435A (zh)
TW (1) TWI456385B (zh)

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TW201229738A (en) * 2011-01-11 2012-07-16 Hon Hai Prec Ind Co Ltd Power supply system
JP2012203583A (ja) * 2011-03-24 2012-10-22 Toshiba Corp 情報処理装置およびプログラム
CN103946811B (zh) * 2011-09-30 2017-08-11 英特尔公司 用于实现具有不同操作模式的多级存储器分级结构的设备和方法
WO2013048497A1 (en) 2011-09-30 2013-04-04 Intel Corporation Apparatus and method for implementing a multi-level memory hierarchy
CN104025060B (zh) 2011-09-30 2017-06-27 英特尔公司 支持近存储器和远存储器访问的存储器通道
CN103946826B (zh) 2011-09-30 2019-05-31 英特尔公司 用于在公共存储器通道上实现多级存储器层级的设备和方法
GB201200219D0 (en) * 2012-01-09 2012-02-22 Calder Martin A clock signal generator for a digital circuit
JP2013243565A (ja) * 2012-05-22 2013-12-05 Semiconductor Energy Lab Co Ltd 半導体装置とその駆動方法

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US5931951A (en) * 1996-08-30 1999-08-03 Kabushiki Kaisha Toshiba Computer system for preventing cache malfunction by invalidating the cache during a period of switching to normal operation mode from power saving mode
TW200632655A (en) * 2004-12-03 2006-09-16 Intel Corp Prevention of data loss due to power failure
US20070055901A1 (en) * 2003-09-16 2007-03-08 Koninklijke Philips Electronics N.V. Power saving operation of an apparatus with a cache memory
TW200745863A (en) * 2005-11-15 2007-12-16 Montalvo Systems Inc Power conservation via DRAM access

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JPH06251570A (ja) 1993-02-26 1994-09-09 Fujitsu Ltd ライブラリ装置
JPH07146820A (ja) * 1993-04-08 1995-06-06 Hitachi Ltd フラッシュメモリの制御方法及び、それを用いた情報処理装置
JPH07253935A (ja) 1994-03-15 1995-10-03 Toshiba Corp コンピュータのデータ保護装置
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Patent Citations (4)

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US5931951A (en) * 1996-08-30 1999-08-03 Kabushiki Kaisha Toshiba Computer system for preventing cache malfunction by invalidating the cache during a period of switching to normal operation mode from power saving mode
US20070055901A1 (en) * 2003-09-16 2007-03-08 Koninklijke Philips Electronics N.V. Power saving operation of an apparatus with a cache memory
TW200632655A (en) * 2004-12-03 2006-09-16 Intel Corp Prevention of data loss due to power failure
TW200745863A (en) * 2005-11-15 2007-12-16 Montalvo Systems Inc Power conservation via DRAM access

Also Published As

Publication number Publication date
US20100058094A1 (en) 2010-03-04
JP5581577B2 (ja) 2014-09-03
US8135971B2 (en) 2012-03-13
TW201009561A (en) 2010-03-01
CN101661435A (zh) 2010-03-03
JP2010055531A (ja) 2010-03-11

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