TWI922013B - Memory chip integration architecture - Google Patents

Abstract

A chip-integrated memory architecture includes a memory unit and an application-specific integrated circuit (ASIC). The memory unit comprises one or more stacked memory chips, each memory chip having a first data register. The ASIC has a second data register, wherein the first data register of the memory unit and the second data register of the ASIC are coupled through an inter-chip interface. The chip-integrated architecture transmits data externally through one or more high-bandwidth interfaces disposed on the ASIC.

Description

Memory chip integration architecture

This invention relates to a memory device, and more particularly to a chip-integrated memory structure.

With the development of technology, semiconductor miniaturization has become a key development area for various manufacturers. In order to increase capacity while reducing the size of memory, high-density memory, such as 3D memory, has been developed. It has a higher-density circuit architecture by stacking and bonding multiple substrates. However, the problems of low circuit performance and low process yield of high-density architecture need to be improved by technical personnel in this field.

The main purpose of this invention is to solve the problems of low circuit performance and low process yield in habituation memory.

To address the aforementioned problems, this invention provides a chip-integrated memory architecture, comprising a memory unit and an application-specific integrated circuit (ASIC). The memory unit includes one or more stacked memory chips, each memory chip having a first data register. The ASIC has a second data register, wherein the first data register of the memory unit and the second data register of the ASIC are coupled through an inter-chip interface. The chip-integrated architecture transmits data externally through one or more high-bandwidth interfaces disposed on the ASIC.

To address the aforementioned problems, the present invention also provides a chip-integrated memory architecture, including a memory unit and an application-specific integrated circuit (ASIC). The memory unit includes one or more stacked memory chips, each memory chip having a first data register. The ASIC has a second data register, wherein the first data register of the memory unit and the second data register of the ASIC are coupled through an inter-chip interface. The chip-integrated architecture transmits data externally through a high-bandwidth interface disposed on the ASIC. Alternatively, the chip's integrated structure may transmit data externally through a high-bandwidth interface located in the memory unit.

The terms used herein are for the purpose of illustrating specific embodiments only and are not intended to limit the invention. Unless the context otherwise indicates, the singular forms “a” and “the” used herein may also include the plural forms.

Referring to Figures 1 and 2, which are schematic diagrams of different embodiments of the present invention, a memory chip integration structure 1 is disclosed. The memory chip integration structure 1 includes one or more memory chips 11, a special application integrated circuit (SAIC) chip 21, and one or more high data bandwidth interfaces 40. The memory chip 11 has a first data register 111, and the SAIC chip 21... Chip 21 has a second data register 211. The application-specific integrated circuit (ASIC) chip 21 is stacked on the memory chip 11 and integrated into a single chip. Therefore, data transfer between the memory chip 11 and the ASIC chip 21 can be achieved through an inter-die interface 30 between the first data register 111 and the second data register 211. Multiple memory chips 11 can be stacked on top of each other, while the ASIC chip 21 can be stacked on only one of the memory chips 11. The multiple memory chips 11 are also connected to each other via the inter-die interface.

The inter-chip interface 30 can be achieved through microbump bonding, hybrid bonding, or wire bonding, forming an interconnect structure. This significantly improves the data transfer speed between the memory chip 11 and the application-specific integrated circuit (ASIC) chip 21. Conversely, the high data bandwidth interface 40 can be disposed on the memory chip 11 (as shown in Figure 2) or the ASIC chip 21 (as shown in Figure 1). By integrating and combining the inter-chip interface 30 and the high data bandwidth interface 40, the memory chip integrated structure 1 can achieve better high-speed data transfer at a lower cost.

Figure 3 is a schematic diagram of the architecture of the first embodiment of the present invention, revealing a memory chip integration structure 1. The memory chip integration structure 1 includes a memory unit 10, a special application integrated circuit unit 20, an inter-chip interface 30, and one or more high data bandwidth interfaces 40. The memory unit 10 and the special application integrated circuit unit 20 are coupled through the inter-chip interface 30 to achieve signal communication. The connection structure between the inter-chip interface 30 and the memory unit 10 and the special application integrated circuit unit 20 can be microbump bonding, hybrid bonding, or wire bonding.

The memory unit 10 includes one or more memory chips 11, each of which has a first data register 111, a memory array 112, an input/output gate (I/O gating) 113, a column decoder 114, a row address multiplexer 115, and a first redundant memory 116. In this example, the memory chip 11 is a dynamic random access memory (DRAM), and multiple memory chips 11 can be stacked to increase the density of DRAM, which helps to improve the performance of the memory unit 10. Furthermore, by stacking multiple memory chips 11, it is not necessary to design a single memory chip 11 as a high-density DRAM, which helps to reduce production costs.

The first data register 111 is coupled to the application-specific integrated circuit (ASIC) unit 20 through the inter-chip interface 30. The memory array 112 is coupled to the input/output gate 113 for bidirectional transmission, and the input/output gate 113 is coupled to the first data register 111 for bidirectional transmission. That is, the first data register 111 and the memory array 112 are coupled to each other through the input/output gate 113 for bidirectional transmission. The column decoder 114 is coupled to the input/output gate 113 for unidirectional transmission. The row address multiplexer 115 is coupled to the memory array 112 for unidirectional transmission. The first redundant memory 116 is coupled to the first data register 111 for bidirectional transmission. It can automatically detect whether the memory unit 10 is faulty and automatically isolate the fault, using redundant backup memory to maintain operation.

The special application integrated circuit unit 20 includes a special application integrated circuit chip 21, which has a second data register 211, a repair circuit 212, a second redundant memory 213, a programmable memory 214, and a row and column decoder 215. In one example, the application-specific integrated circuit chip 21 has a redundant memory (such as the second redundant memory 213) and a memory 216 for recording faulty memory cell addresses. The redundant memory is a dynamic random access memory, a static random access memory, or a magnetoresistive random access memory, used to repair the memory cell 10. The memory 216 for recording faulty memory cell addresses is a non-volatile memory, such as a magnetoresistive random access memory, resistive random access memory, or high-density one-time programmable memory. This memory unit (OTP) or high-density multiple-time programmable memory (MTP) is used to record bad bit address records. The memory unit 216 is used to record bad bit address records and can also be called bad bit address record memory.

The first data register 111 is coupled to the second data register 211 of the special application integrated circuit chip 21 through the inter-chip interface 30, and the repair circuit 212 is coupled to the second data register 211. Therefore, the repair circuit 212 is coupled to one or more memory chips 11 through the inter-chip interface 30 to receive error signals from the memory chips 11. After the error is repaired by the repair circuit 212, it can be sent back to the memory chip 11, which helps to improve the function of the memory unit 10, or the repaired data can be directly transmitted to the application end through the output interface. In one example, the repair circuit 212 may be, but is not limited to, an error repair circuit, a column repair circuit, a bit-by-bit repair circuit, or a dynamic random access memory repair circuit.

The second redundant memory 213 is coupled to the second data register 211 for unidirectional transmission. In this example, the second redundant memory 213 is a dynamic random access memory (DRAM), a static random access memory (SRAM), or a magnetoresistive random access memory (MRAM). The programmable memory 214 is coupled to the repair circuit 212 for unidirectional transmission. The programmable memory 214 can be a single-programmable memory or a multiple-programmable memory. The row and column decoder 215 is coupled to the repair circuit 212 for unidirectional transmission. The second redundant memory 213 is coupled to the second data register 211 for bidirectional transmission. It can automatically detect whether the special application integrated circuit unit 20 is faulty and automatically isolate the fault, using redundant backup memory to maintain operation.

The memory unit 10 and the special application integrated circuit unit 20 disclosed in this invention transmit data through the chip interface 30, which can improve the performance of data transmission. Furthermore, the interfaces of the memory unit 10 and the special application integrated circuit unit 20 can be developed independently, so they can be optimized based on their respective characteristics, which helps to improve performance and product yield.

In this embodiment, the high data bandwidth interface 40 is disposed on the application-specific integrated circuit chip 21, and the memory chip integrated structure 1 performs a data transmission 41 to the outside through the high data bandwidth interface 40. The high data bandwidth interface 40 is one or more interfaces that conform to the protocols of peripheral component interconnect high-speed bus (PCIe), high bandwidth memory (HBM), double data rate (DDR), and computing high-speed link (CXL), while the memory unit 10 does not have an interface for external transmission.

Referring to Figure 4, which is a schematic diagram of the architecture of the second embodiment of the present invention, a memory chip integrated structure 1 is disclosed. The difference between the memory chip integrated structure 1 disclosed in the first embodiment of the present invention is that the high data bandwidth interface 40 is disposed on the memory unit 10. The memory chip integrated structure 1 performs data transmission 41 to the outside through the high data bandwidth interface 40. In this embodiment, the special application integrated circuit unit 20 does not have an interface for external transmission.

In summary, the chip integration structure disclosed in this invention couples the first data register and the second data register through the chip interface, providing data transmission between the memory unit and the application-specific integrated circuit (ASIC). This allows the interfaces of the memory unit and the ASIC to be developed independently, thereby achieving optimized design, which helps improve performance and product yield. Furthermore, since the memory unit and the ASIC are developed independently, higher density memory units can be selected, or multiple memory units can be stacked to achieve better performance and reduce production costs. On the other hand, enabling the special application integrated circuit unit to recognize and repair errors in the connected memory unit and send the information back to the memory unit can help improve the functionality of the memory unit.

1: Integrated Memory Chip Architecture

10: Memory Unit

11: Memory Chip

111: First Data Register

112: Memory Array

113: Input/Output Gate

114: Column decoder

115: Address Multiplexer

116: First Redundant Memory

20: Special Application Integrated Circuit Unit

21: Application-Specific Integrated Circuit Chips

211: Second Data Register

212: Circuit Repair

213: Second Redundant Memory

214: Programmable Memory

215: Row and Column Decoders

216: Bad bit address recording memory

30: Inter-chip interface

40: High Data Bandwidth Interface

41: Data Transmission

Figure 1 is a schematic diagram of the structure of one embodiment of the present invention. Figure 2 is a schematic diagram of the structure of another embodiment of the present invention. Figure 3 is a schematic diagram of the structure of the first embodiment of the present invention. Figure 4 is a schematic diagram of the structure of the second embodiment of the present invention.

1: Integrated Memory Chip Architecture

10: Memory Units

11: Memory Chip

111: First Data Register

112: Memory Array

113: Input/Output Gate

114: Column decoder

115: Address Multiplexer

116: First Redundant Memory

20: Application-Specific Integrated Circuit Units

21: Application-Specific Integrated Circuit Chips

211: Second Data Register

212: Circuit Repair

213: Second Redundant Memory

214: Programmable Memory

215: Row and Column Decoders

216: Bad bit address recording memory

30: Inter-chip interface

40: High Data Bandwidth Interface

41: Data Transmission

Claims (7)

A chip-integrated memory architecture includes: a memory unit comprising one or more stacked memory chips, each memory chip having a first data register; and an application-specific integrated circuit (ASIC) chip having a second data register, wherein the first data register of the memory unit and the second data register of the ASIC chip are coupled through an inter-chip interface; wherein the chip-integrated architecture performs data transmission externally through one or more high-bandwidth interfaces disposed on the ASIC chip. The special application integrated circuit chip has a redundant memory and a defective bit address recording memory. The redundant memory is a dynamic random access memory, a static random access memory, or a magnetoresistive random access memory, used to repair the memory cell. The defective bit address recording memory is a non-volatile memory, such as magnetoresistive random access memory, resistive random access memory, high-density OTP, or high-density MTP. The chip-integrated memory structure as described in claim 1, wherein the memory unit does not have an interface for external transmission. A chip-integrated memory architecture includes: a memory unit comprising one or more stacked memory chips, each memory chip having a first data register; and a special application integrated circuit (ASIC) chip having a second data register, wherein the first data register of the memory unit and the second data register of the ASIC chip are coupled through an inter-chip interface; wherein the chip-integrated architecture performs data transmission externally through a high data bandwidth interface disposed in the memory unit. The special application integrated circuit chip has a redundant memory and a defective bit address recording memory. The redundant memory is a dynamic random access memory, a static random access memory, or a magnetoresistive random access memory, used to repair the memory cell. The defective bit address recording memory is a non-volatile memory, such as magnetoresistive random access memory, resistive random access memory, high-density OTP, or high-density MTP. The chip-on-chip architecture of memory as described in claim 1 or 3, wherein the high data bandwidth interface is one or more interfaces conforming to protocols such as Peripheral Component Interconnect High-Speed Bus (PCIe), High Bandwidth Memory (HBM), Double Data Rate (DDR), and Computing High-Speed Link (CXL). The chip-on-chip architecture of memory as described in claim 1 or 3, wherein the application-specific integrated circuit chip has a repair circuit that is coupled to the first data register of the memory cell via the second data register to repair the memory cell. The chip-integrated memory structure as described in claim 1 or 3, wherein the memory chip is a dynamically randomized access memory. The chip-integrated structure of memory as described in claim 1 or 3, wherein the inter-chip interface connection is micro-bump bunding, hybrid bunding, or wire-bounding.