US20040164304A1 - Insulated gate planar integrated power device with co-integrated schottky diode and process - Google Patents

Insulated gate planar integrated power device with co-integrated schottky diode and process Download PDF

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US20040164304A1
US20040164304A1 US10/713,778 US71377803A US2004164304A1 US 20040164304 A1 US20040164304 A1 US 20040164304A1 US 71377803 A US71377803 A US 71377803A US 2004164304 A1 US2004164304 A1 US 2004164304A1
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region
aperture
drain
layer
conductivity
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Angelo Magri
Ferruccio Frisina
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STMicroelectronics SRL
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Assigned to STMICROELECTRONICS S.R.L. reassignment STMICROELECTRONICS S.R.L. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FRISINA, FERRUCCIO, MAGRI, ANGELO
Publication of US20040164304A1 publication Critical patent/US20040164304A1/en
Priority to US11/520,210 priority Critical patent/US7560368B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0293—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using formation of insulating sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor
    • H10D64/647—Schottky drain or source electrodes for IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/141—VDMOS having built-in components
    • H10D84/146—VDMOS having built-in components the built-in components being Schottky barrier diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
    • H10P30/221—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks characterised by the angle between the ion beam and the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0295—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the source electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H10D64/2527—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies

Definitions

  • the invention relates generally to insulated gate planar integrated power devices and in particular to devices to which are associated a power diode integrated on the same chip.
  • Insulated gate devices such as MOSFETs in particular, are used in many applications as synchronous rectifiers.
  • the insulated gate device operates as a diode: it is turned on when the equivalent diode must be in conduction and is turned off when the diode must stop conducting.
  • a known approach is that of using a Schottky diode of the same voltage and of appropriate area, in parallel to the internal PN junction diode of the integrated structure of the insulated gate device (for example a power MOS transistor or briefly PMOS).
  • the Schottky diode Because of the absence of minority carriers, the Schottky diode is characterized by a fast recovery and, because of the different barrier heights, it has lower conduction voltages. In fact, for voltages lower than 0.9V the Schottky diode conducts a larger current than a PN junction diode; for higher voltages, the characteristics become similar and the PN diode finally conducts a larger current, because of the modulation of its conductivity.
  • FIG. 1 illustrates the advantage of a combined diode MPS (Merged PN Schottky) in respect to a normal junction diode.
  • a more efficient solution depicted in FIG. 4, consists in “distributing” the Schottky diode uniformly over the whole active area of the PMOS by integrating it in the elementary cells of the MOS. It has been demonstrated that by using a uniform distribution of Schottky diodes, it is possible to improve the dynamic performances (trr and softness) while using a reduced total area dedicated to the diode.
  • a Schottky diode is realized in the elementary cell of the MOSFET by a dedicated step of photolithography for realizing a Schottky diode through a certain aperture produced through a first deposited polysilicon layer, that is in the area destined to the realization of the integrated structure of an elementary cell of the insulated gate power device and on which the relative source contact will be established.
  • Schottky diodes are realized by contacting with a metal layer the monocrystalline semiconducting substrate, the doping level of which determines the voltage class.
  • the technique of forming, around the Schottky contact region in the semiconductor, a more or less dense array of juxtaposed diffuse regions (tubs) of opposite type of conductivity to that of the substrate (Lateral Merged PiN Schottky). The distance of separation among adjacent tubs is chosen so that under conditions of inverse polarization, the electric field is partially shielded by the depleted zones that form around the tubs.
  • a further aspect of the present invention is that of limiting the number of photolithographic steps in the sequence of process steps of an insulated gate integrated power device with co-integrated Schottky diode in parallel thereto.
  • the photolithographic step for defining the Schottky contact area inside the aperture of a discrete or of an elementary cell of an integrated structure of the insulated gate power device is eliminated by carrying out:
  • an embodiment of the invention provides a method for integrating a Schottky contact inside the apertures of the elementary cells that constitute the integrated structure of the insulated gate power device in a totally self-alignment manner without requiring a dedicated masking step. This overcomes the above indicated limits to the possibility of increasing the packing density of the cellular structure of the integrated power device, while permitting improved performances of the co-integrated Schottky diode under inverse polarization of the device and producing other advantages that will be mentioned in the ensuing description.
  • An implanted and diffused source region is formed in the cell area within the body region.
  • a drain region of the semiconductor substrate is coupled to the invertible channel region and the current is eventually collected through a drain contact.
  • a trench is formed, in self-alignment to spacers formed on definition edge surfaces of the aperture, in the semiconductor crystal in a portion of the area of the aperture that includes a central “window” that is defined in a shade pattern by purposely implanting with different tilt and twist angles the body dopants, for a depth extending from the crystal surface through the source region and the body region that surrounds the central zone of said window not implanted with the body dopants, reaching down into the drain semiconductor under the source diffusion in correspondence of said window.
  • a deposited metal layer contacts on at least a portion of the side walls of the trench, the source, and the body region, constituting a source contact, and, on the bottom of the trench, the drain semiconductor substrate thus establishing a Schottky contact with the drain region, electrically in parallel to the insulated gate device.
  • said trench is formed in a central zone of the area of the cell aperture and of the diffused body region, for a depth sufficient to reach into the semiconductor beyond the bottom profile of the source diffusion, that is in a region electrically coinciding with the drain region and surrounded by the diffused body region.
  • the source contact metallization fills the trench establishing an electric contact with the source region and with the body region on at least a portion of the surface of the side walls of the trench and a Schottky contact on at least a portion of the bottom surface of the trench.
  • the structure further comprises a diffused deep body region, more heavily doped than the first diffused body region that is contained therein.
  • This second or deep body region besides containing the first body region, extends for a greater depth than the first body region surround a deeper zone under the Schottky contact established on the bottom of the trench.
  • the structure further comprises a buried region having the same type of conductivity of the first body region, geometrically located in the semiconductor crystal at a certain depth under the Schottky contact established on the bottom of the trench and surrounded by a deep body region and/or by the body region.
  • FIG. 1 shows the experimental trade-off curve between the voltage Vf and the inverse current peak of a switching MPS diode, with an irradiated PN junction diode in function of the area reserved to the Schottky diode;
  • FIG. 2 depicts a solution with discrete elements combined in a single package
  • FIG. 3 depicts a monolithic solution with distinct areas for the PMOS and the Schottky diode
  • FIG. 4 depicts an integrated solution of a Schottky diode in each elementary cell of the PMOS, according to the prior art
  • FIGS. from 5 to 14 illustrate the relevant steps of a process of fabrication of an insulated gate power device and characteristics of the structure that is realized, according to a first embodiment of this invention
  • FIGS. from 15 to 21 illustrate the relevant steps of a process of fabrication and characteristics of the structure that is realized, according to an alternative embodiment of this invention
  • FIG. 22 shows leakage characteristics under inverse polarization in function of the area of the Schottky contact in the embodiments of FIGS. 5 - 14 and 15 - 21 ;
  • FIGS. from 23 to 29 illustrate the relevant steps of a process of fabrication and characteristics of the structure that is realized, according to a third alternative embodiment of this invention.
  • FIG. 30 shows the inverse leakage and the direct voltage drop performances in function of the characteristics of a shielding buried region of the Schottky contact in the embodiment of FIGS. 23 - 29 .
  • the process of this invention differs from the known processes for the realization of a structure of an insulated gate device with Schottky diode integrated in the elementary cells that compose the device, because of the way in which the elementary cell structure is realized such to include a Schottky contact between the source metal layer and a region of semiconductor crystal of substrate electrically coinciding with the drain of the integrated power device.
  • the structure of this invention may also be that of a P-channel floating gate device, by simply inverting, in a dual mode, the type of conductivity of the semiconducting crystal substrate and of the dopants used for realizing the various diffused regions.
  • ion implantation first body implant
  • a P type dopant for example boron or indium with 30° tilt and 90° twist
  • the tilt angle must be chosen such to create a shade zone by the windows opened by the anisotropic (vertical) etching in the stack composed of the polysilicon layer and the insulating layer.
  • the tilt angle to be used will depend from the total height of the etched edge of the hard mask formed by the polysilicon the insulating layer and eventually also of the residual thickness of the photo resist mask, and from the width of the stripes or definition lines.
  • the twist angle must be such to make the impinging ion beam orthogonal to the long side of the stripe segments.
  • the implant dose and energy will be chosen such to obtain the desired concentration and channel length;
  • ion implantation (second body implantation) of the same P type dopant but with tilt and twist angles opposite to the ones of the preceding implantation step (for example boron or indium with ⁇ 30° tilt and 90° twist or 30° tilt and ⁇ 90° twist);
  • ion implantation of a N type dopant (for example 1015 ions/cm2 of arsenic with an implant energy of about 80 keV);
  • metallization of the front side of the wafer with a material capable of establishing a good electrical contact with said exposed surfaces of the body and source diffusions and a good barrier height of the Schottky contact that is established at the bottom of the trench with the silicon of substrate, that is with the drain of the integrated structure of the insulated gate power device (suitable materials may be for example titanium or a silicide thereof);
  • ion implantation first deep body implantation
  • a P type dopant for example boron or indium with 20° tilt and 90° twist
  • the tilt angle must be chosen such to create a shade zone in the windows opened by the anisotropic (vertical) etching through the stack composed of the polysilicon layer and the insulating layer.
  • the tilt angle to be used will depend from the total height of the etched edge of the mask formed by the polysilicon layer, the insulating layer and the residual thickness of the photo resist mask, and from the width of the stripes or definition lines.
  • the twist angle must be such that the ionic stream be orthogonal to the long side of the stripes.
  • the dose and the implant energy must be chosen such to obtain the desired concentration;
  • ion implantation (second deep body implant) of the same P type dopant but with tilt and twist angles opposite to those of the preceding implantation step (for example boron or indium with ⁇ 20° tilt and 90° twist or 20° tilt and ⁇ 90° twist);
  • ion implantation first body implant
  • a P type dopant for example boron or indium with 40° tilt and 90° twist.
  • the tilt angle must be chosen such to create a shade zone by the windows opened by the anisotropic (vertical) etching in the stack composed of the polysilicon layer and the insulating layer.
  • the tilt angle to be used will depend from the total height of the etched edge of the hard mask formed by the polysilicon the insulating layer and from the width of the stripes or definition lines.
  • the twist angle must be such to make the impinging ion beam orthogonal to the long side of the stripe segments.
  • the implant dose and energy will be chosen such to obtain the desired concentration and channel length;
  • ion implantation (second body implantation) of the same P type dopant but with tilt and twist angles opposite to those of the preceding implantation step (for example boron or indium with ⁇ 40° tilt and 90° twist or 40° tilt and ⁇ 90° twist);
  • ion implantation of a N type dopant (for example 1015 ions/cm2 of arsenic with an implant energy of 80 keV);
  • an implantation (which hereinafter will be referred to as “drain engineering” or D.E.) is included in the process sequence for increasing the resistivity of the semiconductor of substrate (drain) of the device under the Schottky contact region.
  • the semiconductor substrate or drain may be in practice an expitaxial layer grown on a semiconductor crystal that may have electrical characteristics different from those of the epitaxial layer grown thereon.
  • An implanted buried region of “drain engineering” will be electrically tied to the body or, where they exists, to the deep body diffusions, such to effectively shield the Schottky contact also in a vertical direction, with the result of decisively reducing the leakage current.
  • the realized integrated structure may be defined as “Lateral & Vertical Merged PiN Schottky (LVMPS)”.
  • ion implantation Drain Engineering implant
  • a P type dopant for example boron at 200-400 keV.
  • the dose to be implanted must be such to compensate slightly the epitaxial layer and it is thus a function of the voltage class of the power device being fabricated;
  • ion implantation first body implant
  • a P type dopant for example boron or indium with 30° tilt and 90° twist.
  • the tilt angle must be chosen such to create a shade zone by the windows opened by the anisotropic (vertical) etching in the stack composed of the polysilicon layer and the insulating layer.
  • the tilt angle to be used will depend from the total height of the etched edge of the hard mask formed by the polysilicon the insulating layer and eventually also of the residual thickness of the photo resist mask, and from the width of the stripes or definition lines.
  • the twist angle must be such to make the impinging ion beam orthogonal to the long side of the stripe segments.
  • the implant dose and energy will be chosen such to obtain the desired concentration and channel length;
  • ion implantation (second body implant) of the same P type dopant but with tilt and twist angles opposite to those of the preceding implantation (for example boron or indium with ⁇ 30° tilt and 90° twist or 30° tilt and ⁇ 90° twist);
  • ion implantation of a N type dopant (for example 1015 ions/cm2 of arsenic with an implant energy of about 80 keV);
  • the composite basic cell structure MOS+Schottky of this invention is realized without any additional dedicated masking step.
  • the width of the stripes is thus limited only by the resolution of the photoexposition equipment and by the ability to precisely implant the dopants (to this end it is convenient to use dopants with low diffusivity such as indium and arsenic);
  • stripe layout is not mandatory, other cellular layouts may be used, eventually performing several pairs of body implantations each with appropriate tilts and twist angles in order to realize the body diffusions in each channel zone while defining a Shottky contact window there between.
  • the graph of FIG. 30 shows the leakage current and the direct voltage drop obtained on test structures for different doses of drain engineering dopant. Near the dose of 2*1012 ions/cm2 there is enough room for reducing the leakage by an order of magnitude without burdening excessively the direct voltage drop. By doubling the dose, the drain engineering diffusion creates a junction that shields the Schottky contact but reduces the direct characteristic to become practically similar to that of a PN junction diode.
  • the insulated gate planar power devices avcording to the above embodiments may be used in a variety of different types of electronic systems, such as a DC-DC converter and other types of rectifying systems.

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EP02425695A EP1420457B1 (fr) 2002-11-14 2002-11-14 Procédé de fabrication d'un dispositif semi-conducteur de puissance à grille isolée et diode Schottky

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US20080169517A1 (en) * 2005-07-08 2008-07-17 Stmicroelectronics S.R.L. Method for manufacturing electronic devices integrated in a semiconductor substrate and corresponding devices
US20080296636A1 (en) * 2007-05-31 2008-12-04 Darwish Mohamed N Devices and integrated circuits including lateral floating capacitively coupled structures
US20090035910A1 (en) * 2007-07-31 2009-02-05 Intersil Americas, Inc. Method of Forming The NDMOS Device Body With The Reduced Number of Masks
CN102088021A (zh) * 2009-12-03 2011-06-08 达尔科技股份有限公司 具有肖特基二极管的沟槽mos装置及其制造方法
US20110151636A1 (en) * 2004-09-28 2011-06-23 Sandisk Corporation Method For Angular Doping Of Source And Drain Regions For Odd And Even NAND Blocks
US20110193142A1 (en) * 2010-02-05 2011-08-11 Ring Matthew A Structure and Method for Post Oxidation Silicon Trench Bottom Shaping
US8193565B2 (en) 2008-04-18 2012-06-05 Fairchild Semiconductor Corporation Multi-level lateral floating coupled capacitor transistor structures
US20130313570A1 (en) * 2012-05-24 2013-11-28 Microsemi Corporation Monolithically integrated sic mosfet and schottky barrier diode
CN103700587A (zh) * 2012-09-27 2014-04-02 意法半导体股份有限公司 用于制造诸如超势垒sbr整流器之类的半导体器件的方法
US8736013B2 (en) 2012-04-19 2014-05-27 Fairchild Semiconductor Corporation Schottky diode with opposite-polarity schottky diode field guard ring
US8835934B2 (en) 2009-09-15 2014-09-16 Kabushiki Kaishia Toshiba Semiconductor device
CN104518006A (zh) * 2014-07-01 2015-04-15 重庆中科渝芯电子有限公司 一种耗尽型沟道超势垒整流器及其制造方法
CN104718627A (zh) * 2012-10-19 2015-06-17 日产自动车株式会社 半导体装置及其制造方法
CN106098752A (zh) * 2016-07-25 2016-11-09 吉林华微电子股份有限公司 一种igbt器件及其制造方法
WO2016179025A1 (fr) * 2015-05-01 2016-11-10 The Regents Of The University Of California Réalisation de modèles de couche de circuit intégré par implantation d'ions inclinée
CN107634001A (zh) * 2016-11-18 2018-01-26 成都芯源系统有限公司 一种ldmos器件的制造方法
US9954093B2 (en) * 2016-06-29 2018-04-24 Infineon Technologies Austria Ag Method of manufacturing a super junction semiconductor device and super junction semiconductor device
US10056457B2 (en) 2016-05-23 2018-08-21 General Electric Company Electric field shielding in silicon carbide metal-oxide-semiconductor (MOS) device cells using channel region extensions
CN110212026A (zh) * 2019-05-06 2019-09-06 上海功成半导体科技有限公司 超结mos器件结构及其制备方法
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US7560368B2 (en) 2009-07-14
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