US3585464A - Semiconductor device fabrication utilizing {21 100{22 {0 oriented substrate material - Google Patents

Semiconductor device fabrication utilizing {21 100{22 {0 oriented substrate material Download PDF

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US3585464A
US3585464A US676451A US3585464DA US3585464A US 3585464 A US3585464 A US 3585464A US 676451 A US676451 A US 676451A US 3585464D A US3585464D A US 3585464DA US 3585464 A US3585464 A US 3585464A
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substrate
region
semiconductor
layer
devices
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Paul P Castrucci
Martin S Hess
George Maheras
William D North
Edward G Grochowski
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International Business Machines Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H10W15/01—Manufacture or treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/037—Diffusion-deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/049—Equivalence and options
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/115—Orientation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/91—Controlling charging state at semiconductor-insulator interface
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/973—Substrate orientation

Definitions

  • the device has a low defect density and few dopant precipitate sites even at high dopant levels.
  • a monolithic integrated circuit structure composed of the monocrystalline semiconductor substrate having a surface crystallographic orientation substantially parallel to a 100 plane with a plurality of semiconductor devices within the substrate is described. The devices are isolated from one another by PN junctions. The tolerance in a given isolated device, between the PN junction and the nearest region having a different conductivity is less than approximately 0.3 mils. This very close spacing allows substantially greater compactness of semiconductor devices within a monocrystalline semiconductor body than has ever been previously accomplished.
  • the invention relates to semiconductor devices and, more particularly, to semiconductor devices and methods for obtaining more uniformly diffused PN junctions at very high surface concentrations, semiconductor devices having increased beta or transistor gain at both high and at low current levels, and better crystallographic perfection in the semiconductor devices.
  • Monocrystalline semiconductor material can be grown in many different crystallographic directions. Silicon, for example, has been grown in several crystallographic directions to produce monocrystals substantially free from dislocations.
  • the article entitled, Growth of Silicon Crystals Free From Dislocation by William C. Dash in the Journal of Applied Physics, pages 459-474, Volume 30, No. 4, Apr. i959, procedures for the growth of silicon monocrystals of the various crystallographic directions are given.
  • the l00 and the 1ll axes are generally the orientations which can be used.
  • the article states that the 11I orientation is preferredover the- 100 orientation.
  • the lll orientation monocrystalline silicon has been the only material used.
  • an epitaxial layer is generally formed over the substrate monocrystalline body.
  • the epitaxial film growth is dependent upon the crystallographic characteristics of the starting substrate.
  • diffused regions are often formed in the substrate body of monocrystalline material. These regions can, for example, result in the subcollector for the subsequently fabricated transistor device.
  • the monocrystalline body is silicon
  • a preepitaxial oxidation diffusion is commonly used in the formation in this region.
  • silicon dioxide is removed before the epitaxial layer is deposited on the surface of the substrate.
  • the result of the process is a surface which exhibits a high defect density where the l 11 crystallographic direction substrate is utilized.
  • This substratecondition then nucleates epitaxial growth defects, such as stacking faults, that extend into the epitaxial film. These epitaxial defects have been shown to act as nucleation sites for dopant precipitates for local regions of enhanced diffusion. The result is greater variation in device quality over the entire semiconductor chip than is desirable and resultant loss of electrical characteristics in certain of the semiconductor devices in the affected areas.
  • the circuit density lower limit for 111 oriented material is in the order of one circuit per 200 square mils where an epitaxial layer is required over the surface of the substrate semiconductor monocrystalline material and a subcollector or similar structure is utilized in the substrate material.
  • a circuit is defined as having about transistors, 2 diodes and 2 resistors. The reason for this is that the 1 I l oriented semiconductor epitaxially grows at a substantial angle of about 45 from theptfi-pendicular which results in the effective shifting of the resulting semiconductor device in relation to the diffused region in the substrate. This effect, together with the out-diffusion effect from the region in the substrate and from the PN junction isolation region, can reduce the tolerance between the PN junction region and the region in the substrate to zero. The result is the electrical joining of these two regions and a defective semiconductor device.
  • a semiconductor device which is composed of a body of monocrystalline semiconductor material, such as silicon, having a surface crystallographic orientation substantially parallel to the l00 plane.
  • a PN junction is formed in the body and an insulator coating, such as silicon dioxide, is formed over the surface of the body containing the PN junction.
  • the resulting density of interface states is very low. In the case of silicon dioxide-silicomthe density of interface states in the proximity of the silicon and the insulator silicon dioxide layer is less than approximately 2X10 per cm.*.
  • the formed semiconductor 100 body composed of a substrate and an epitaxial layer thereover is so defect free that substantially higher concentrations of dopants can be diffused into the body without the objectional precipitate of the dopants as sites, such as the PN junctions in the devices.
  • greater concentrations of phosphorus can be used as the dopant to form the N region of the PN junction semiconductor device wherein the phosphorus source concentration is between about 2.5 l0 ppm. and 4.0)(10 p.p.m.
  • the junction is free of phosphorus precipitation sites and is not ragged as is the case if a 1l1 crystallographic orientated monocrystalline semiconductor material would have been used.
  • Monolithic integrated circuits can be produced which are composed of the l00 oriented material.
  • the monolithic integrated circuit is composed of the monocrystalline substrate and a substantially defect-free epitaxial semiconductor layer grown from the substrate wherein the layer is of the l00 orientation.
  • a plurality of semiconductor devices are provided within the substrate and the layer wherein the devices are isolated from one another with PN junctions.
  • the tolerance between the PN junction and the nearest region having a different conductivity in the semiconductor devices is less than approximately 0.3 mils.
  • Devices composed of lll oriented material can not reach this close a tolerance because of the epitaxial layer growth at an angle of about 45 from the perpendicular.
  • the l00 material epitaxial growth is substantially perpendicular to the substrate.
  • FIG. 1 is a sectional illustration of a discrete transistor device which illustrates one form of the invention
  • FIG. 2 is a PN junction isolated transistor device within a monolithic integrated circuit structure which is a second form of the invention
  • FIG. 3 is a field effect transistor device which is a third form of the invention.
  • FIG. 4A and 4B are graphical representations showing the density of silicon dioxide-silicon interface states versus energy in eV;
  • FIG. 5 is a graphical illustration of beta versus normalized collector current comparing monolithic integrated circuit devices fabricated in l00 material and lll material;
  • FIG 6 is a Gummel plot of collector and base current versus applied voltage.
  • FIG. 1 there is shown a discrete semiconductor device.
  • the device is fabricated by starting with a wafer or substrate 10 of N+ silicon monocrystalline material. It should, however, be evident to those skilled in the art that the conductivity type shown in the drawing is selected for illustrative purposes only and that the opposite conductivity type can be used. Further, the concentration of impurities can be increased or decreased as desired.
  • the substrate 10 is fabricated, for example, by pulling a monocrystalline rod from a suitable melt containing a N-type material such as phosphorus or arsenic and using a seed crystal having a l00 crystallographic orientation. The resulting pulled monocrystalline rod has a l00 orientation.
  • the rod is then sliced into very thin wafers which also have the surface crystallographic orientation of l00
  • the substrate 10 is then positioned in an epitaxial growth reactor and the epitaxial layer 12 is grown on the substrate 10.
  • the epitaxial growth reaction is made according to standard practices and is doped with suitable N-type dopants to produce an N-type epitaxial layer 12.
  • the epitaxial layer 12 is also oriented in the l00 crystallographic orientation. Since the epitaxial growth is along the l00 plane, the growth is substantially perpendicular to the substrate.
  • the semiconductor transistor device is then formed in the epitaxial layer 12 by base and emitter diffusions to form, respectively, the base region 14 and the emitter region 16.
  • An insulator layer 18 covers the surface of the semiconductor device with openings to allow the electrical contact 20 to ohmically contact the elements of the transistor.
  • the layer 18 can be any of the well-known insulators such as silicon dioxide or silicon nitride and may be formed thereon by any of the conventional techniques known to those in the art.
  • the FIG. 2 illustrates a portion of a monolithic integrated circuit device which contains hundreds of junction isolated semiconductor devices of the type illustrated. Other devices such as diodes, resistors and capacitors (not shown) can and are formed in monolithic integrated circuits of this type along with the illustrated type device.
  • the substrate material for substrate is preferably composed of P-silicon which could preferably have a resistivity of from 10 to 20 ohms-cms.
  • the substrate is again oriented in the l00 crystallographic orientation and is produced in a similar manner as described relative to FIG. 1.
  • a Ptype material such as boron is used as the dopant in the melt.
  • a region of a conductivity different than the substrate is then formed in the substrate 30 which will ultimately result in the subcollector structure 32.
  • the region is normally formed by standard diffusion techniques but could be formed by other techniques such as ion implantation and etch and refill.
  • This region is formed by first, in the case of a silicon substrate, forming an insulating or silicon dioxide layer on the semiconductor surface by thermal oxidation. An opening is then formed in the silicon dioxide layer by conventional photolithographic masking and etching techniques. An N+ region is formed in the substrate 30 beneath the opening in the insulating layer.
  • All insulating coating is then removed from the surface of the substrate 30 by use of suitable etching solutions.
  • the epitaxial layer 34 is then grown on top of the substrate 30 in a conventional epitaxial reactor.
  • the epitaxial layer 34 will be oriented in the l00 orientation since the substrate 30 is monocrystalline semiconductor having a l00 orientation.
  • the N+ region in the substrate 30 out-diffuses into the epitaxial layer 34 to produce the N+ subcollector 32.
  • the entire surface of the epitaxial layer 34 is then coated with an insulator material such as by a thermal oxidation of the silicon to silicon dioxide to provide a silicon dioxide layer 36.
  • P+ type isolation regions 37 are provided, for example, by diffusing boron in the appropriate concentration, through the openings, into the epitaxial layer to a depth that extends into the substrate to fully PN junction isolate designated regions of semiconductor within the epitaxial layer.
  • the tolerance T between the opening for the PN junction region 37 diffusion and the subcollector 32 may be less than 0.3 mils when l00 oriented material is used and provides for greater circuit density.
  • the lower possible limit for 1II oriented material is approximately 0.5 mils.
  • the openings are then reoxidized and another photolithographic masking and etching procedure is accomplished to open holes in the oxide layer above selected area of the epitaxially grown layer 34.
  • the P-type base, diode and resistor regions are then diffused into the appropriate isolated epitaxially grown regions. In that portion of the monolithic circuit illustrated in FIG. 2, it is the base region 38 which is diffused through the suitable opening.
  • the exposed surface of the epitaxial layer is then oxidized in a suitable oxidizing atmosphere. During the oxidation the impurities are caused to be driven-in to thereby completely form the base region 38.
  • the emitter region 40 is then obtained by photolithographic and etching to open holes in the desired areas of the silicon dioxide layer and diffusing N-type impurities into the desired portion of the base region 38,
  • the surface of the epitaxial layer is again oxidized and the impurities are driven in to form the complete emitter region 40.
  • the surface is again masked and holes are etched in the oxide for forming the contact openings to the desired semiconductor regions.
  • a suitable contact metal is then evaporated or deposited by other means onto the semiconductor regions through the openings in the insulating coating 36.
  • the contacts are illustrated as elements 42.
  • a typical contact material is aluminum; however, other well-known metals in the art can be used such as platinum, palladium and so forth.
  • FIG. 3 shows a unipolar transistor whose electrical characteristics are substantially improved by using the l00 oriented material.
  • the unipolar transistor is composed of a silicon semiconductor body 50 having a crystallographic orientation substantially parallel to l00 plane.
  • a layer of silicon dioxide 52 covers the surface of the body 50.
  • Diffused P+ source-drain regions 54 are formed in the body 50.
  • Electrical contacts 56 ohmically connect the regions 54 to external connectors.
  • the gate electrode 58 regulates the flow of carriers in the channel 60 between the two source-drain region 54.
  • the low donor surface state density of the l00 oriented siliconsilicon dioxide interface is a particular advantage in field effect transistors.
  • a specific value of gate bias applied to the electrode 58 is necessary to deplete carriers in channel 60 with respect to the source-drain electrodes 54.
  • the threshold voltage required to invert this channel is substantially less for l00 than 1l1 oriented material due to the surface state density. Larger values for transconductance can be, therefore, obtained as
  • a more perfect substrate in the 100 instance yields a defect-free epitaxial film, which in turn can produce diffused junctions of very high electrical quality.
  • the collector/base junctions and the emitter/base junctions are formed by dopant diffusion, the junction quality, characterized by breakdown voltage, leakage currents, may be adversely affected by these high defect densities.
  • the epitaxial film oriented in the l00 direction exhibits stacking fault densities below lOO/centimeter for a like epitaxially grown material. Diffusions with maximum surface concentrations of, for example, atoms/centimeter are desired for the shallow junctions depths used in high speed monolithic integrated device structures. Increased dopant concentration yields lower contact resistances at emitter and base contacts, thereby producing low forward voltage drops. With l00 oriented material semiconductor devices, these high dopant concentrations yield good junction quality without inducing crystallographic imperfections characterized by ragged junctions as is obtained when using identical dopant concentration in the lll oriented material.
  • Ragged junctions yield uneven base widths which limit beta (transistor gain) control.
  • the worst case situation is a shorting at the emitter/collector region at low biasing potentials (punchthrough").
  • a large emitter and base area junction is required in the case of a discrete semiconductor device or in a monolithic integrated circuit application for high voltage and high current devices.
  • the l00 oriented device structures yield large area junctions free of crystallographic defect thereby exhibiting a good junction quality.
  • the probability of including a crystallographic defect in the junction area has increased probabilities due to the large area.
  • the value of substantially defect-free material of the l00 orientation is greater since it will produce substantially higher device yields than the presently used lll oriented material.
  • Silicon wafers of l00 oriented material and lll oriented material were produced by identical procedures as to produce the FIG. 2 device as described above. The difference in the process involved only the diffusion source concentration for the emitter region. Source concentrations of phosphorus of 1.5, 2.5, and 4f l0 p.p.m. were diffused into wafers of both l00 oriented and 1 11 oriented material. The results showed substantial phosphorus precipitation at 2.5 and 4.0 l0 p.p.m. for the lll oriented material. No precipitation was detected on the l00 oriented material except that for a small amount detected at 4X10 p.p.m.
  • FIGS. 4A and 4B illustrate that the l00 oriented material has a lower surface-charge than lll and l10 material. This fact is true regardless of type of semiconductor material utilized.
  • the FIGS. 4A and 48 illustrate the case where l ohm-centimeter silicon is used as a substrate and a silicon dioxide layer is thermally grown on the substrate in oxygen with 80 p.p.m. H O at lOO0C. The density of silicon dioxide-silicon interface states versus energy is given for the conduction band edge. I5, in
  • FIG. 4A and the valence band edge E in FIG. 4B The base recombination current is directly related to the surface state charge and will control the low current beta of a transistor.
  • EXAMPLE Fifty wafers each of lll and l00 oriented material were obtained by the process of separately growing rods of monocrystalline silicon by pulling material from a melt containing the desired impurity concentration and then slicing the pulled member into the plurality of wafers. The fifty wafers each were divided into five runs of 10 wafers per run. Each run then consisted of ten wafers of lll material and 10 wafers of l00 material. Monolithic integrated circuit devices were formed in each of the wafers according to the fabrication method and the 1 monolithic integrated circuit structure described in the U.S. Pat. application Ser. No. 539,210 of B. Agusta et al. filed Mar. 31, 1966, now U.S. Pat.
  • FIG. 2 of the present patent application illustrates the sectional structure of a transistor device within the monolithic integrated circuit structure. Ten test sites were formed in each wafer. Single transistors which can be electrically contacted for obtaining the electrical characteristics of the transistors located in the monolithic integrated circuit are located on each test site.
  • the fabrication process briefly involves starting with the ten wafers each of l00 and lll material having a P type conductivity with a resistivity of 10 to 20 ohm-centimeter. A silicon dioxide layer having a thickness of 5,200 Angstroms was then thermally grown on the surface of each of the silicon wafers. Photolithographic masking and etching techniques were used to open holes in the desired areas of the silicon dioxide layer to expose the silicon semiconductor surface. A buffered hydrofluoric acid solution was used as the etchant. A N type region was formed in the silicon semiconductor substrate by diffusion of arsenic. The resulting surface concentration was C of 10 atoms cm of N-type majority carriers in the diffused region. The silicon dioxide layer served as a diffusion mask during the diffusion operation.
  • the silicon dioxide layer was then completely removed with a buffered hydrofluoric acid solution.
  • the wafers were then placed in epitaxial growth chamber and a epitaxial layer of 5.5 to 6.5 microns in thickness having a resistivity of 0.2 ohm per centimeter was formed on the substrate.
  • the epitaxial layer was arsenic doped during the deposition.
  • the wafers were then oxidized to form a silicon dioxide layer on the surface of the epitaxial layer. Photolithographic masking and etching was used to open holes in this silicon dioxide layer at the locations where isolation diffusions are required. P isolation regions were then formed to isolate certain areas of the semiconductor epitaxial layer using a boron dopant to form a C, (surface concentration) of 5 X 10 atoms cm.
  • the diffusion operation was carried out at a temperature of l,200 C for a period of minutes.
  • the epitaxial surface was then reoxidized by thermally heating the surface at a temperature of approximately l,00() C. for a period of five minutes.
  • Photolithographic masking and etching was then used to open holes in the silicon dioxide layer for the base diffusion.
  • the base diffusion used boron as the impurity source and was carried out for a time of 70 minutes at 1,075 C to form the base region having a surface concentration of 5X10 atoms cm.
  • the surface was then reoxidized using a heating cycle of 25 minutes in dry oxygen, 10 minutes in steam, and 15 minutes in dry oxygen at l,l50 C.
  • Photolithographic and etching techniques were used to open holes in the silicon dioxide layer for an emitter diffusion. Phosphorus was diffused into the base regions of the device to form the emitter regions. Following this emitter diffusion, an emitter drive-in and oxidation heat treatment step was accomplished. The drive-in cycle was at 970 C. The cycle involved 5 minutes in dry oxygen, followed by 55 minutes steam and then dry oxygen. The photolithographic masking and etching techniques were used again to open the holes in the silicon dioxide layer. A layer of aluminum was then deposited over the entire wafer surface. Portions of this aluminum layer were then etched away to produce the desired interconnection pattern. The aluminum etchant was a warm solution ofphosphoric acid, nitric acid and water.
  • the test sites for all 50 wafers of both l11 material and l material were used for extensive electrical testing of the monolithic integrated circuit devices formed in the wafers.
  • the following Chart l is the average data for all tests made in HO. is a graphical illustration of Beta or the transistor gain versus the normalized collector current; Ic/Ic peak. It is clear from this graphical illustration that the important electrical characteristic Beta drops off much faster for the ll1 oriented material than for the l00 oriented material. For currents of 0.001 peak value of collector current, the Beta value is five times higher for the l00 material than for the 111 material.
  • the graphical illustration dramatically shows how the l00 oriented material extends the useful current range of the semiconductor devices by as much as two orders of magnitude. The use of l00 material can therefore be used at lower current and lower power operations which allow increased packing density of circuits in a given area without the necessity of liquid cooling techniques to disperse the heat.
  • FIG. 6 is a Gummel plot of collector and base currents versus applied voltage for transistor structures for both the 11 1 and l00 oriented material. This plot was made to insure that the improved effect shown by the l00 material over l11 oriented material is not a base channel phenomenon since the linear slope of the collector and base current versus applied voltage on a semilogarithmic scale represents best case semiconductor junction conduction. If a base channel phenomenon were present, the slope would break away from its linear condition.
  • the structure of the present invention wherein at least one PN junction is formed in a substantially defect-free epitaxial layer of l00 crystallographic orientation may be used in high current, high power devices having a current-carrying capacity of more than about 1 amp.
  • a monolithic integrated circuit structure comprising:
  • a substrate of monocrystalline silicon material having a surface crystallographic orientation substantially parallel to the l00 plane; a substantially defect-free epitaxial semiconductor layer grown from said substrate wherein said layer has a surface crystallographic orientation substantially parallel to the l00 plane;
  • the said devices being so connected to produce desired circuits
  • circuit area density being greater than about one circuit per 200 square mils
  • certain of said devices including a first diffused region partly in said substrate and partly in said epitaxial layer, a second diffused region of opposite conductivity from the first region in the surface of said epitaxial layer opposite to said substrate, a third diffused region of the said conductivity as the first in said second region, a fourth diffused region surrounding said second and third regions, and extending through the said epitaxial layer to the said substrate, and a layer of silicon dioxide over the surface of said epitaxial layer wherein said second, third and fourth diffused regions are formed;
  • the density of interface states at the silicon dioxide to silicon interface between said body and said layer is less than approximately 2X 1 0 per cm.'; and the growth of said epitaxial layer is substantially perpendicular to the surface of said substrate, and the tolerance between said first region and said fourth region of said certain devices being less than approximately 0.3 mils.

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3717515A (en) * 1969-11-10 1973-02-20 Ibm Process for fabricating a pedestal transistor
US3765961A (en) * 1971-02-12 1973-10-16 Bell Telephone Labor Inc Special masking method of fabricating a planar avalanche transistor
US3798513A (en) * 1969-12-01 1974-03-19 Hitachi Ltd Semiconductor device having a surface parallel to the {8 100{9 {11 plane and a channel stopper parallel to the {8 111{9 {11 plane
US3860948A (en) * 1964-02-13 1975-01-14 Hitachi Ltd Method for manufacturing semiconductor devices having oxide films and the semiconductor devices manufactured thereby
US3964089A (en) * 1972-09-21 1976-06-15 Bell Telephone Laboratories, Incorporated Junction transistor with linearly graded impurity concentration in the high resistivity portion of its collector zone
US5159429A (en) * 1990-01-23 1992-10-27 International Business Machines Corporation Semiconductor device structure employing a multi-level epitaxial structure and method of manufacturing same
US5198692A (en) * 1989-01-09 1993-03-30 Kabushiki Kaisha Toshiba Semiconductor device including bipolar transistor with step impurity profile having low and high concentration emitter regions
US20050156284A1 (en) * 2003-12-16 2005-07-21 Infineon Technologies Ag Semiconductor component having a pn junction and a passivation layer applied on a surface

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Publication number Priority date Publication date Assignee Title
JPS58179174U (ja) * 1982-05-24 1983-11-30 有限会社大川工芸 玉廻し玩具

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NL6501818A (de) * 1964-02-13 1965-08-16 Hitachi Ltd
NL6607547A (de) * 1965-06-01 1966-12-02
US3380153A (en) * 1965-09-30 1968-04-30 Westinghouse Electric Corp Method of forming a semiconductor integrated circuit that includes a fast switching transistor
US3437890A (en) * 1963-05-10 1969-04-08 Ibm Diffused-epitaxial scanistors
US3461003A (en) * 1964-12-14 1969-08-12 Motorola Inc Method of fabricating a semiconductor structure with an electrically isolated region of semiconductor material

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US3200001A (en) * 1961-04-22 1965-08-10 Siemens Ag Method for producing extremely planar semiconductor surfaces
US3437890A (en) * 1963-05-10 1969-04-08 Ibm Diffused-epitaxial scanistors
NL6501818A (de) * 1964-02-13 1965-08-16 Hitachi Ltd
US3461003A (en) * 1964-12-14 1969-08-12 Motorola Inc Method of fabricating a semiconductor structure with an electrically isolated region of semiconductor material
NL6607547A (de) * 1965-06-01 1966-12-02
US3380153A (en) * 1965-09-30 1968-04-30 Westinghouse Electric Corp Method of forming a semiconductor integrated circuit that includes a fast switching transistor

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3860948A (en) * 1964-02-13 1975-01-14 Hitachi Ltd Method for manufacturing semiconductor devices having oxide films and the semiconductor devices manufactured thereby
US3717515A (en) * 1969-11-10 1973-02-20 Ibm Process for fabricating a pedestal transistor
US3798513A (en) * 1969-12-01 1974-03-19 Hitachi Ltd Semiconductor device having a surface parallel to the {8 100{9 {11 plane and a channel stopper parallel to the {8 111{9 {11 plane
US3765961A (en) * 1971-02-12 1973-10-16 Bell Telephone Labor Inc Special masking method of fabricating a planar avalanche transistor
US3964089A (en) * 1972-09-21 1976-06-15 Bell Telephone Laboratories, Incorporated Junction transistor with linearly graded impurity concentration in the high resistivity portion of its collector zone
US5198692A (en) * 1989-01-09 1993-03-30 Kabushiki Kaisha Toshiba Semiconductor device including bipolar transistor with step impurity profile having low and high concentration emitter regions
US5159429A (en) * 1990-01-23 1992-10-27 International Business Machines Corporation Semiconductor device structure employing a multi-level epitaxial structure and method of manufacturing same
US20050156284A1 (en) * 2003-12-16 2005-07-21 Infineon Technologies Ag Semiconductor component having a pn junction and a passivation layer applied on a surface
US7187058B2 (en) * 2003-12-16 2007-03-06 Infineon Technologies Ag Semiconductor component having a pn junction and a passivation layer applied on a surface

Also Published As

Publication number Publication date
DE1802849B2 (de) 1972-10-19
JPS5141555B1 (de) 1976-11-10
FR1582686A (de) 1969-10-03
BE720739A (de) 1969-02-17
NL6814919A (de) 1969-04-22
ES359297A1 (es) 1970-06-01
CH484523A (de) 1970-01-15
SE352781B (de) 1973-01-08
DE1802849A1 (de) 1969-04-30
GB1241057A (en) 1971-07-28

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