CH484523A - Verfahren zur Herstellung von monolithischen Schaltungen - Google Patents

Verfahren zur Herstellung von monolithischen Schaltungen

Info

Publication number
CH484523A
CH484523A CH1539468A CH1539468A CH484523A CH 484523 A CH484523 A CH 484523A CH 1539468 A CH1539468 A CH 1539468A CH 1539468 A CH1539468 A CH 1539468A CH 484523 A CH484523 A CH 484523A
Authority
CH
Switzerland
Prior art keywords
production
monolithic circuits
monolithic
circuits
Prior art date
Application number
CH1539468A
Other languages
English (en)
Inventor
Philip Castrucci Paul
George Grochowski Edward
Steven Hess Martin
Maheras George
David North William
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of CH484523A publication Critical patent/CH484523A/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H10W15/01—Manufacture or treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/037—Diffusion-deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/049—Equivalence and options
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/115—Orientation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/91—Controlling charging state at semiconductor-insulator interface
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/973—Substrate orientation
CH1539468A 1967-10-19 1968-10-15 Verfahren zur Herstellung von monolithischen Schaltungen CH484523A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US67645167A 1967-10-19 1967-10-19

Publications (1)

Publication Number Publication Date
CH484523A true CH484523A (de) 1970-01-15

Family

ID=24714587

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1539468A CH484523A (de) 1967-10-19 1968-10-15 Verfahren zur Herstellung von monolithischen Schaltungen

Country Status (10)

Country Link
US (1) US3585464A (de)
JP (1) JPS5141555B1 (de)
BE (1) BE720739A (de)
CH (1) CH484523A (de)
DE (1) DE1802849B2 (de)
ES (1) ES359297A1 (de)
FR (1) FR1582686A (de)
GB (1) GB1241057A (de)
NL (1) NL6814919A (de)
SE (1) SE352781B (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3860948A (en) * 1964-02-13 1975-01-14 Hitachi Ltd Method for manufacturing semiconductor devices having oxide films and the semiconductor devices manufactured thereby
US3717515A (en) * 1969-11-10 1973-02-20 Ibm Process for fabricating a pedestal transistor
JPS4813572B1 (de) * 1969-12-01 1973-04-27
US3765961A (en) * 1971-02-12 1973-10-16 Bell Telephone Labor Inc Special masking method of fabricating a planar avalanche transistor
US3964089A (en) * 1972-09-21 1976-06-15 Bell Telephone Laboratories, Incorporated Junction transistor with linearly graded impurity concentration in the high resistivity portion of its collector zone
JPS58179174U (ja) * 1982-05-24 1983-11-30 有限会社大川工芸 玉廻し玩具
US5198692A (en) * 1989-01-09 1993-03-30 Kabushiki Kaisha Toshiba Semiconductor device including bipolar transistor with step impurity profile having low and high concentration emitter regions
US5159429A (en) * 1990-01-23 1992-10-27 International Business Machines Corporation Semiconductor device structure employing a multi-level epitaxial structure and method of manufacturing same
DE10358985B3 (de) * 2003-12-16 2005-05-19 Infineon Technologies Ag Halbleiterbauelement mit einem pn-Übergang und einer auf einer Oberfläche aufgebrachten Passivierungsschicht

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL277330A (de) * 1961-04-22
US3437890A (en) * 1963-05-10 1969-04-08 Ibm Diffused-epitaxial scanistors
GB1100124A (en) * 1964-02-13 1968-01-24 Hitachi Ltd Semiconductor devices and methods for producing the same
US3461003A (en) * 1964-12-14 1969-08-12 Motorola Inc Method of fabricating a semiconductor structure with an electrically isolated region of semiconductor material
USB460009I5 (de) * 1965-06-01
US3380153A (en) * 1965-09-30 1968-04-30 Westinghouse Electric Corp Method of forming a semiconductor integrated circuit that includes a fast switching transistor

Also Published As

Publication number Publication date
GB1241057A (en) 1971-07-28
FR1582686A (de) 1969-10-03
ES359297A1 (es) 1970-06-01
NL6814919A (de) 1969-04-22
US3585464A (en) 1971-06-15
DE1802849A1 (de) 1969-04-30
JPS5141555B1 (de) 1976-11-10
BE720739A (de) 1969-02-17
DE1802849B2 (de) 1972-10-19
SE352781B (de) 1973-01-08

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Legal Events

Date Code Title Description
PL Patent ceased