US4514754A - Digital color television signal processing circuit - Google Patents

Digital color television signal processing circuit Download PDF

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US4514754A
US4514754A US06/469,545 US46954583A US4514754A US 4514754 A US4514754 A US 4514754A US 46954583 A US46954583 A US 46954583A US 4514754 A US4514754 A US 4514754A
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output
signal
input
circuit
detection circuit
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Antonius H. H. J. Nillesen
Petrus W. G. Welles
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US Philips Corp
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US Philips Corp
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Assigned to U.S. PHILIPS CORPORATION reassignment U.S. PHILIPS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: NILLESEN, ANTONIUS H.H.J., WELLES, PETRUS W.G.
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/44—Colour synchronisation
    • H04N9/455—Generation of colour burst signals; Insertion of colour burst signals in colour picture signals or separation of colour burst signals from colour picture signals

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  • the invention relates to a digital colour television signal processing circuit comprising an analogue-to-digital converter which is controlled by a pulse generator producing a pulse signal of four times the chrominance subcarrier frequency, a comparison circuit being coupled to the output of the analogue-to-digital converter for comparing different digital burst samples and for obtaining therefrom a control signal for a phase control loop of the pulse generator.
  • a digital colour television signal processing circuit of the type described in the opening paragraph is characterized in that the burst samples to be compared are obtained from an input and an output of a delay circuit having such a delay that at a correct pulse generator phase the difference between the burst samples at the input and at the output thereof becomes zero, while the comparison circuit is an inequality detection circuit for detecting, independently of the amplitude value of the burst samples, inequality of the amplitude values of the burst samples at the input and at the output of the delay line and for converting that inequality, if present, into a control signal.
  • FIG. 1 illustrates by means of a block circuit diagram a digital colour television signal processing circuit in accordance with the invention
  • FIG. 2 illustrates by means of a more detailed circuit diagram a portion of the circuit of FIG. 1, and
  • FIG. 3 illustrates the operation of the circuit diagram of FIG. 1 by means of a number of waveforms.
  • FIG. 1 there is applied to an input 1 of an analogue-to-digital converter 3 a colour television signal comprising a quadrature-modulated chrominance subcarrier signal, the zero phase component of which is illustrated in FIG. 3 by the waveform 301.
  • the chrominance subcarrier signal is a PAL-signal.
  • the signal comprises a burst which during a horizontal blanking period x has a phase of 135°, as illustrated by the waveform 302 of FIG. 3 and during the subsequent horizontal blanking period x+1 has a phase of 225° as illustrated by the waveform 304 of FIG. 3.
  • a pulse signal from an output 7 of a pulse generator 9 is applied to an input 5 of the analogue-to-digital converter 3.
  • This pulse signal has a frequency which is four times the chrominance subcarrier frequency and will be denoted 4f hereinafter.
  • the signal 4f is illustrated in FIG. 3 by means of the waveform 307.
  • the signal at the input 1 is sampled by the analogue-to-digital converter 3 and converted into a digital signal which in the period which the instant initiates is supplied from an output 11 of the analogue-to-digital converter 3 and applied to an input 13 of an inequality detection circuit 15.
  • the digital signal is applied to an input 17 of a comparator 19 and to an input 23 of this comparator 19 via a delay circuit formed by the delay line 21 having a time delay equal to one sampling period 1/4 f .
  • the signal at the input 17 of the comparator 19 corresponds to the samples at the instants t o , t 1 , . . . of the waveform 302 and 304, alternately and at the said instants the signal at the input 23 corresponds to the samples of waveforms 306 and 308, alternately, of FIG. 3.
  • the output 25 of the comparator 19 is connected to inputs of an AND-gate 29 and an AND-gate 31, while the output 27 of the comparator 19 is connected to inputs of an AND-gate 33 and an AND-gate 35.
  • the other inputs of the AND-gates 31 and 35 are inverting inputs and, as are also the other inputs of the AND-gates 29 and 33, are connected to an input 37 of the inequality detection circuit 15.
  • the outputs of the AND-gates 29 and 35 are connected to the inputs of an OR-gate 39 and the outputs of the AND-gates 31 and 33 are connected to the inputs of an OR-gate 41.
  • the output of the OR-gate 39 is connected to a D-input of a D-flip-flop 43 and the output of the OR-gate 41 is connected to the D-input of a D-flip-flop 45.
  • the D-flip-flops 43 and 45 receive a clock signal from an input 47 and a reset signal from an input 49 of the inequality detection circuit 15. The reset signal maintains the D-flip-flop in the zero state in the period of time between two consecutive chrominance subcarrier bursts.
  • the non-inverting output of the D-flip-flop 43 is connected via a diode 51, and the inverting output of the D-flip-flop 45 via a diode 53, which is reverseconnected compared with the diode 51, to an output 55 of the inequality detection circuit 15.
  • the input 37 of the inequality detection circuit 15 is connected to the output of an OR-gate 57, the inputs of which are connected to the outputs of two AND-gates 59 and 61.
  • the input 47 of the inequality detection circuit 15 is connected to the output of an OR-gate 63, the inputs of which are connected to the outputs of two AND-gates 65 and 67.
  • a switching signal m of half the horizontal deflection frequency is applied from an output 69 of a state detection circuit 71 to an input of the AND-gates 59 and 65 and to an inverting input of the AND-gates 61 and 67.
  • the other inputs of the AND-gates 59, 61, 65 and 67 are connected to outputs 73, 75, 77 and 79, respectively, of the pulse generator 9, further outputs 81 and 83 of which are connected to inputs 82 and 84, respectively, of the state detection circuit 71.
  • the waveforms of the signals at the outputs 73, 75 77, 79, 81 and 83, respectively, of the pulse generator 9 are illustrated in FIG. 3 and denoted by the reference numerals 373, 375, 377, 379, 381 and 383, respectively.
  • the signals at the inputs 17 and 23, respectively, of the comparator 19 will be denoted by r and s, respectively, and the signals at the outputs 7, 77, 79, 83, 73, 75 and 81, respectively, of the pulse generator 9 by 4f, 2A, 2B, A, B, C and D, respectively.
  • the output 69 thereof becomes one during the horizontal blanking period x and zero during the horizontal blanking period x+1.
  • the signal B is applied to the input 37 of the inequality detection circuit 15 during the blanking period x and the signal C during the blanking period x+1.
  • phase of the signal 4f lags or leads, respectively, somewhat the zero phase 301 of the chrominance subcarrier, then the sampling instants t o , t 1 . . . shift in FIG. 3 to the right or to the left, respectively.
  • the sampling instants t 1 , t 3 , t 5 , t 7 are of importance and in the period x+1 the sampling instants t o , t 2 , t 4 , t 6 , as at these instants, with a correct phase of 4f, the difference between r x and s x or r x+1 and s x+1 , respectively, is zero.
  • the output of the flip-flop 43 becomes zero, as does also the output of the flip-flop 45.
  • the diode 51 is then cutoff and the diode 53 conducts, as a result of which a capacitor 89 connected to the output 55 of the inequality detection circuit 15 discharges via resistors 85 and 87.
  • the other side of the capacitor 89 is connected to ground via a resistor 90.
  • phase of the signal 4f leads somewhat, it can be demonstrated in the same way that the outputs of the flip-flops 43 and 45 become logic one, causing the diode 51 to conduct and the diode 53 to become nonconductive and the capacitor 89 to be charged.
  • a control signal is obtained from the capacitor 89 which is applied to a control signal input 91 of the pulse generator 9, as a result of which the phase of the signal 4f is adjusted to zero again.
  • the switching signal at the output 69 of the state detection circuit 71 becomes zero in the period x and one in the period x+1, then the signal at the output 55 of the inequality detection circuit 15 will alternately become zero and one, and the control loop comprising the analogue-to-digital converter 3, the inequality detection circuit 15, the filter 85, 87, 89, 90 and the pulse generator 9 will not be capable of operation in the correct phase until the correct switching signal occurs again. Further details will be given in the description of the state detection circuit 71.
  • the alternately occurring zero and one signals at the output 55 are applied via a filter formed by a resistor 92 and a capacitor 93, and via a Schmitt-trigger circuit 95 to an EXCLUSIVE-OR gate 97 and to a delay circuit 99, which has a time delay of one horizontal deflection period, the output of which is connected to a further input of the EXCLUSIVE-OR gate 97.
  • the delay circuit 99 is in the form of a D-flip-flop which, by way of clock signal, receives from an input 100 the same signal which is applied to the input 49 of the inequality detection circuit 15 and has a value 0 only during the occurrence of the burst and the value 1 between two consecutive bursts, also in the field blanking period if no burst is present.
  • the inequality detection circuit output signal which is somewhat delayed by the filter 92, 93 and the Schmitt-trigger circuit 95 is stored in the D-flip-flop 99 until the next burst period.
  • the EXCLUSIVE-OR gate 97 applies a one-signal at the occurrence of a zero and a one value which alternate from deflection period to deflection period, to an input 101 of the state detection circuit 71.
  • the signal at this input 101 will be designated signal e.
  • the input 100 of the circuit is connected to an input 103 of the state detection circuit 71 and applies thereto the above-described signal which will be designated g' hereinafter.
  • the state detection circuit 71 supplies a signal k at an output 107, which is applied to a colour killer signal output 109 of the circuit and to a switching signal input 111 of a switch 113. Consequently, in the non-pulled-in state of the control loop, the resistor 85 is by-passed by means of the switch 113.
  • a pulse signal h, of the horizontal deflection frequency, which has the value one during the horizontal blanking period, is applied to an input 115 of the state detection circuit 71.
  • FIG. 2 which illustrates a possible embodiment of a state detection circuit 71
  • the same reference numerals are used for components corresponding to those of FIG. 1.
  • the inputs 101, 103 and 105 also form the inputs of a counter input circuit 201, which comprises an AND-gate 203 an input of which is connected to the input 101, an AND-gate 205 an inverting input of which is connected to the input 103 and an OR-gate 207 an inverting input of which is connected to the input 105 of the state detection circuit.
  • a further, inverting input of the AND-gate 205 is connected to the output of a divide-by-two divider 208 to which also the output 69 which supplies the switching signal m is connected.
  • the inverting output of the AND-gate 205 is connected to a further input of the OR-gate 207 and to a preset input 210 of an extension circuit which is formed by a counter 211, a preset memory 213 and an AND-gate 215.
  • An output of the counter 211 which becomes one if its counting position differs from zero, supplies from an output 217 of the counting input circuit 201 a signal n which is also applied to an input of the AND-gate 215.
  • the signal A coming from the input 84 of the state detection circuit 71 is applied to the other input of the AND-gate 215.
  • the output of the AND-gate 215 is connected to a counting signal input 218 of the counter 211.
  • the signal g'+m at the output of the AND-gate 205 which will be designated b' hereinafter, becomes low every alternate deflection period during the burst and causes the counter 211 to take over its presetting value from the preset memory 213, as a result of which the output signal n becomes one. After the burst period has ended, the counter returns to zero in response to the signal nA at its input 218. The signal n at its output 217 then becomes zero again.
  • a third input of the OR-gate 207 and an inverting input of the AND-gate 203 are connected to an output 219 of a threshold circuit 221 from which a signal t is supplied.
  • a further output 223 of the threshold circuit 221 applies a signal p to a further inverting input of the AND-gate 203 and to an input of an AND-gate 225 a further input of which is connected to the output of the OR-gate 207.
  • the outputs of the AND-gates 203 and 225 are connected to the inputs of an OR-gate 227, the output of which is connected to the input of a D-flip-flop 229 to which the signal A, obtained from the input 84 of the state detection circuit 71, is applied as a clock signal.
  • An output 231 of the D-flip-flop 229 forms an output of the counter input circuit 201 from which a signal u is supplied.
  • the output signal of the OR-gate 227 is equal to p't'e+p(c'+t+b').
  • This signal is written into the D-flip-flop 229 by the clock signal A. It comprises information about the accurate state of the switching signal m which is included in the signal e and about the pulled-in state of the control loop present in the signal c.
  • the information in the signal c if it plays a part in the above-mentioned formula, is stored in the D-flip-flop 229 at the instants t 4 , t 8 . . . in response to the signal A.
  • These instants are the instants at which the result of the comparison of r with s at the instant t 3 , t 7 . . . becomes available at the output 27 of the comparator 19. In the period x+1 this result is one as then, the control loop being pulled-in, r x >s x at t 3 and t 7 .
  • the signals u and n are applied from the output 231 and 217, respectively, of the counter input circuit 201 to an input 233 and 235, respectively, of a counter 237.
  • the signal u at the input 233 determines whether the counter 237 counts up or down, if the signal has the value one the counter 237 counts down, if it has the value zero the counter counts up.
  • the counter 237 is only capable of counting if the signal n at its input 235 is one.
  • the signal D coming from the input 82 and acting as a clock signal is applied to an input 239 of the counter 237 and a signal which causes the counter 237 to assume a position determined by a preset memory 243 is applied to a preset signal input 241.
  • an output combination 245 Connected to an output combination 245 is an input combination 247 of the threshold circuit 221, which input combination at the same time forms an input combination of a level selection circuit 251.
  • the level selection circuit 251 supplies a signal t, i, p, k 1 and k 2 , resectively, from an output 253, 255, 257, 259 and 261, respectively.
  • the output 253 and 257, respectively, of the level selection circuit 251 is connected to the output 219 and 223, respectively, of the threshold circuit 221.
  • the output 255 of the level selection circuit 251 is connected to the input of a D-flip-flop 263, which receives a signal A as a clock signal from an input 265 which is connected to the input 84 of the state detection circuit 71.
  • the outputs 259 and 261 of the level selection circuit 251 are connected to the j and k inputs of a jk flip-flop 267 which also receives the signal A as a clock signal from the input 265 of the threshold circuit.
  • the output of the flip-flop 263 is connected to the preset signal input 241 of the counter 237 and to an input of an AND-gate 269 to a further input of which the signal h coming from the input 115 of the state detection circuit 71 is applied.
  • the output of the AND-gate 269 is connected to the input of the divide-by-two divider 208, which acts as a change-over signal generator.
  • the output of the flip-flop 267 is connected to the output 107 of the state detection circuit 71 and supplies the colour killer and time-constant switching signal k.
  • the position of the counter 237 at which p changes from 0 to one corresponds to the position stored in the preset memory 243.
  • the signal is p't'e+p(c'+t+b').
  • the counter 237 can only count if the signal n at the output 217 of the counter 211 has the value one.
  • the below schematic survey indicates when this is the case.
  • the threshold k 2 is then passed and the j-k flip-flop 267 changes state, causing the signal k to become 1 and a colour kill to be eliminated and the time constant of the control loop to be increased because the switch 113 cancels the short-circuit of the resistor 85.
  • the counter 237 now proceeds to its maximum position.
  • the counting position of the counter 237 decreases again and, when the threshold k 1 is passed, the j-k flip-flop 267 changes state again, so that the time constant of the control loop is reduced again and the colour killing state is reinstated.
  • the state detection circuit 71 has two functions: to detect the state of the control loop and the state of the divide-by-two divider 208, which are realized by means of only one counter 237 acting as an integrator.
  • an integrator in the form of, for example, a counter may of course be used for each of these functions.
  • the colour killing signal can then be taken from an AND-gate connected to the output of the integrators.
  • the state detection circuit 71 may, if so desired, be made operative for each burst by applying, in response to the signal m, alternately the signals A and D to the input 84 and alternately the signals D and C to the input 82.
  • the m input of AND-gate 205 must then be adjusted to the low state so that the AND-gate 205 only functions as a buffer and b' becomes equal to g'.
  • the operation of the state detection circuit can be improved by having the signal e influence the preset value of the preset memory 213.
  • the inequality detection circuit 15 is operative for t 1 , t 5 , . . . in the period x and t 0 , t 4 , . . . in the period x+1 as well as for t 3 , t 7 . . . in the period x and t 2 , t 6 , . . . in the period x+1. If less stringent requirements are imposed on the insensitivity to noise, the inequality detection for, for example, t 3 , t 7 . . . in the period x and t 2 , t 6 . . . in the period x+1 may be omitted.
  • the noise insensitivity of the circuit 95, 97, 99 can be improved by using a hysteresis-free circuit, for example a comparator, instead of the Schmitt-trigger circuit 95 and to apply the output signal of the D-flip-flop 99 to a further D-flip-flop, which is clocked by the signal g' and whose input and output are connected to the inputs of a further EXCLUSIVE-OR-gate.
  • the signal e is then taken via a D-flip-flop clocked by the signal g' from an AND-gate whose inputs are connected to the outputs of the EXCLUSIVE-OR-gate 97 and the additional EXCLUSIVE-OR-gate.
  • the circuit is used to process a NTSC-signal the resistor 92, the capacitor 93, the Schmitt-trigger circuit 95, the flip-flop 99, the EXCLUSIVE-OR-gate 97, the input 101 of the AND-gate 203 and consequently also the AND-gate 203 and the OR-gate 227, the divide-by-two divider 208 and the AND-gate 269 are omitted.
  • the input 115 of the state detection circuit 71 is omitted as well as the output 69.
  • the input m of the AND-gate 205 is adjusted to its low state, so that it only serves as a buffer. The time delay of the delay line 21 must then be made equal to an even number of periods of the signal 4f instead of an odd number as with PAL.
  • the gates 57, 59, 61, 63, 65 and 67 are then omitted, and the signal A is applied to the input 37 of the inequality detection circuit 15 and the signal 2B to the input 47 and the signal C to the input 84 of the state detection circuit 71 and the signal B to the input 82.
  • a signal p' is applied to the input of the D-flip-flop 263.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Processing Of Color Television Signals (AREA)
  • Color Television Systems (AREA)
US06/469,545 1982-03-05 1983-02-25 Digital color television signal processing circuit Expired - Fee Related US4514754A (en)

Applications Claiming Priority (2)

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NL8200901 1982-03-05
NL8200901A NL8200901A (nl) 1982-03-05 1982-03-05 Digitale kleurentelevisiesignaalverwerkingsschakeling.

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EP (1) EP0088464B1 (nl)
JP (1) JPS58164391A (nl)
DE (1) DE3360335D1 (nl)
NL (1) NL8200901A (nl)

Cited By (7)

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Publication number Priority date Publication date Assignee Title
US4558348A (en) * 1983-12-30 1985-12-10 Rca Corporation Digital video signal processing system using asynchronous a-to-d encoding
US4625232A (en) * 1982-12-22 1986-11-25 U.S. Phillips Corporation Demodulation circuit for a digitized chrominance signal having a sampling signal oscillator coupled to a chrominance signal oscillator
US4707729A (en) * 1985-03-14 1987-11-17 U.S. Philips Corporation System for the line-wise compression of binary data of a picture field in a compression device, decompression device for use in such a system, and display device including such a decompression device
US5298798A (en) * 1991-07-31 1994-03-29 Matsushita Electric Industrial Co., Ltd. Amplitude control device
US20040176181A1 (en) * 2000-04-18 2004-09-09 Meyer Jeffrey W. Composite metal wood club
US20080303564A1 (en) * 2002-04-18 2008-12-11 International Business Machines Corporation On chip timing adjustment in multi-channel fast data transfer
US20090135302A1 (en) * 2005-10-11 2009-05-28 Kazuya Miyashita Chroma killer detection circuit

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JPS5972814A (ja) * 1982-10-20 1984-04-24 Sanyo Electric Co Ltd 遅延回路
US4620219A (en) * 1984-08-06 1986-10-28 Rca Corporation Apparatus for detecting a chrominance reference burst component to develop a burst gate pulse

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US4122487A (en) * 1977-01-28 1978-10-24 Ampex Corporation Precision phase controlled clock for sampling television signals
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US4122487A (en) * 1977-01-28 1978-10-24 Ampex Corporation Precision phase controlled clock for sampling television signals
US4291332A (en) * 1980-04-10 1981-09-22 Tokyo Shibaura Denki Kabushiki Kaisha Phase-locked circuit

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4625232A (en) * 1982-12-22 1986-11-25 U.S. Phillips Corporation Demodulation circuit for a digitized chrominance signal having a sampling signal oscillator coupled to a chrominance signal oscillator
US4558348A (en) * 1983-12-30 1985-12-10 Rca Corporation Digital video signal processing system using asynchronous a-to-d encoding
US4707729A (en) * 1985-03-14 1987-11-17 U.S. Philips Corporation System for the line-wise compression of binary data of a picture field in a compression device, decompression device for use in such a system, and display device including such a decompression device
US5298798A (en) * 1991-07-31 1994-03-29 Matsushita Electric Industrial Co., Ltd. Amplitude control device
US20040176181A1 (en) * 2000-04-18 2004-09-09 Meyer Jeffrey W. Composite metal wood club
US20080303564A1 (en) * 2002-04-18 2008-12-11 International Business Machines Corporation On chip timing adjustment in multi-channel fast data transfer
US8122395B2 (en) * 2002-04-18 2012-02-21 International Business Machines Corporation On chip timing adjustment in multi-channel fast data transfer
US20090135302A1 (en) * 2005-10-11 2009-05-28 Kazuya Miyashita Chroma killer detection circuit
EP1947867A4 (en) * 2005-10-11 2010-09-29 Panasonic Corp CHROMA KILLER DETECTION CIRCUIT
US8031269B2 (en) 2005-10-11 2011-10-04 Panasonic Corporation Chroma killer detection circuit

Also Published As

Publication number Publication date
EP0088464B1 (en) 1985-07-03
NL8200901A (nl) 1983-10-03
JPH0351160B2 (nl) 1991-08-05
EP0088464A1 (en) 1983-09-14
JPS58164391A (ja) 1983-09-29
DE3360335D1 (en) 1985-08-08

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