US4982361A - Multiple loop parallel pipelined logic simulation system - Google Patents

Multiple loop parallel pipelined logic simulation system Download PDF

Info

Publication number
US4982361A
US4982361A US06/789,832 US78983285A US4982361A US 4982361 A US4982361 A US 4982361A US 78983285 A US78983285 A US 78983285A US 4982361 A US4982361 A US 4982361A
Authority
US
United States
Prior art keywords
status
values
activated
output
logic element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US06/789,832
Other languages
English (en)
Inventor
Shinichiro Miyaoka
Akira Muramatsu
Motohisa Funabashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Assigned to HITACHI, LTD. reassignment HITACHI, LTD. ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: FUNABASHI, MOTOHISA, MIYAOKA, SHINICHIRO, MURAMATSU, AKIRA
Application granted granted Critical
Publication of US4982361A publication Critical patent/US4982361A/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Definitions

  • the present invention relates to a logic circuit simulator, particularly, to a special purpose processor suitable for high speed simulation of a large scale gate level circuit.
  • the purpose of the present invention is to provide a special purpose processor for high speed and precise simulation of a large scale logic circuit containing MOS elements.
  • Logic simulation is divided into four processes, (1) registration and read out of activated logical elements, (2) read out of the type of elements (AND, OR, etc) and the state the input pins, (3) logical operation of the elements and decision of output status change, (4) read out of the output side elements and of a delay time. These are effected by special purpose hardware, and data or operating instructions are circulated according to the sequence of (1) ⁇ (2) ⁇ (3) ⁇ (4) ⁇ (1)--for high speed logic simulation.
  • FIG. 1 is a structural drawing of an embodiment of a logic simulator based on the present invention
  • FIG. 2 is a block diagram of circuits 1 to 3 shown in FIG. 1;
  • FIG. 3 is a block diagram of circuits 4 to 6 shown in FIG. 1;
  • FIG. 4 is a block diagram of circuits 7 to 9 shown in FIG. 1;
  • FIG. 5 is a block diagram of circuits 13 to 15 shown in FIG. 1;
  • FIG. 6 is an operating explanatory drawing of the present invention.
  • an overall operating processor is composed of a triple loop.
  • the first (or the second or the third, read the numbers in this order in parentheses hereinafter) loop 17 (18, 19) is composed of a registration and read out CKT 1 (2, 3) for registering and reading out the activated element; an element input side read out CKT 4 (5, 6) for reading out the kind of the element and the state of the input pin; a decision CKT 7 (8, 9) for a logical operation of the element and for deciding the presence of output status change; a FIFO data buffer 10 (11, 12); an element output side read out CKT 13 (14, 15) for reading out the element to be output and the delay time; and an exchange network 16.
  • a logic simulation circuit is divided into as many sub-circuits as the number of loops.
  • the data for the kind of element, the connecting structure, and the delay time are divided corresponding to the subgraph, assigned to each one of the loops, and stored in the processor of the corresponding loop.
  • Each of the circuits 1 to 3 is composed of an event processor 20 and an event memory 21, as shown in FIG. 2.
  • the event memory 21 comprises a time wheel 22 which is individually accessible and an event list 23.
  • a head pointer H and a tail pointer T of the event list is stored, corresponding to each time.
  • the event list 23 the number of the activated element G, the input pin number N showing the status change of the element, and a status value S of the input pin are connected by a pointer P to be stored.
  • the circuits 4 to 6 are composed of a fan in processor 30 and an element memory 31, as shown in FIG. 3.
  • the element memory 31 is composed of an activated element list 32, which is individually accessible, an element kind table 33, and an input value table 34.
  • the element number G is stored in the activated element list
  • the element kind OP and the pointer P of the input table are stored in the element kind table
  • the status of the input pins of all the element S 1 , S 2 , . . . are stored in the input value table.
  • the circuits 7 to 9 are composed of an evaluation unit 40 and a status memory 44, as shown in FIG. 4.
  • the evaluation unit 40 is composed of a data compression CKT for compressing the data of the input signal, a memory 42 for storing a true value for each element, and a decision circuit 43 for deciding the presence of the status change of output.
  • the data compression CKT is provided for excluding a combination of a redundancy or meaningless input and for decreasing the memory capacity required for the true value table.
  • the status of the output pin of the element is stored in the status memory 44, corresponding to the element number.
  • the circuits 13 to 15 are composed of a fan-out processor 50 and a connecting structure memory 51, as shown in FIG. 5.
  • the connecting structure memory 51 is composed of a pointer table 52, which is individually accessible, and a table to be output 53.
  • the pointer P of the table to be outputted is stored in the pointer table and the number of elements to be output, the input pin number of the element, and the delay time d are stored in the table to be output.
  • propagation delay time is also considered as the delay time to provide a value such that the propagation delay time is added to the delay time of the element to be output.
  • the output is complicated, and termination of the reading out of the table to be output is decided by an END flag in the stored data.
  • the exchange network 16 distributes the input data according to the address in a header part, and is composed of a multiple step network or a crossbar switch.
  • phase I only the event processor and the fan-in processor are operated and the evaluation unit and the fan-out processor are in an idling state.
  • phase II all the processors operate at the same time.
  • phase I The operations in phase I will be described according to FIGS. 2 and 3.
  • the event processor 20 in FIG. 2 reads out the number of element G activated at the current time t, the input pin number N, and the input pin state S and feeds out the combination of (G,. N, S) to the fan-in processor.
  • the fan-in processor 30 receives the combination of (G, N, S) and writes G in the activated element list 32 and S in the input value table 34. When this operation terminates for all the input pins of the activated element, phase I is complete.
  • the fan-in processor 30 reads out the element number G for the element registered in the activated element list, the kind OP, and the status of all the input pins of the element S 1 , S 2 , . . . from the element memory 31 and feeds out the combination of (G, OP, S 1 , S 2 , . . .). When there are many input points, it is preferable to provide a function that enables sending them separately.
  • the evaluation unit 40 receives the combination of (G, OP, S 1 , S 2 , . . . ) and inputs them to the data compression circuit 41.
  • the values read out from the status memory 44 are simultaneously inputted when the internal states are required for logical operations such as a flip-flop.
  • the output of the data compression circuit 41 becomes the address of the true value table memory 42 and the value read out from the memory 42 becomes a new output of the element. Accordance or discordance of the present output and the previous output is checked by the decision circuit 43, and if there is a change, a new output value S is stored in the status memory 44, while the combination of (G, S) is sent to the data buffer.
  • the exchange network 16 decodes the element number G and sends out the combination of (G, N, S, d) to any one of the three event processors. That is to say, the data is sent out to the event processor connected to the event memory which stores the information related to G.
  • the event processor 20 of FIG. 2 receives the combination of (G, N, S, d), calculates the estimated time of activation t+d from the present time t and the delay time d, and then registers (G, N, S) with the event list of this time.
  • the calculation device is connected to a host computer, for example, (a micro-computer) which loads data into memory, reads out results, and controls exchanges between phases I and II.
  • a host computer for example, (a micro-computer) which loads data into memory, reads out results, and controls exchanges between phases I and II.
  • the present invention can resolve the problems inherent in parallel processing to effect maximum calculation so that it can effect high speed logic simulation.
  • a large computer corresponding to the M200-H class effects simulation at 5 ⁇ 10 4 elements/ second.
  • the present invention can effect simulation at 1.2 ⁇ 10 7 element/second four loops and at 4.8 ⁇ 10 7 element/second 16 loops, provided that the machine cycle is 100 ns.
  • the well-known example can process only a unit delay, whereas the present invention can process a standard delay containing a propagation delay. Furthermore, precise simulation becomes possible because the present invention can process many statuses.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Tests Of Electronic Circuits (AREA)
US06/789,832 1984-10-26 1985-10-21 Multiple loop parallel pipelined logic simulation system Expired - Fee Related US4982361A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59223918A JPS61102569A (ja) 1984-10-26 1984-10-26 高速論理シミユレ−シヨン装置
JP59-223918 1984-10-26

Publications (1)

Publication Number Publication Date
US4982361A true US4982361A (en) 1991-01-01

Family

ID=16805751

Family Applications (1)

Application Number Title Priority Date Filing Date
US06/789,832 Expired - Fee Related US4982361A (en) 1984-10-26 1985-10-21 Multiple loop parallel pipelined logic simulation system

Country Status (2)

Country Link
US (1) US4982361A (ja)
JP (1) JPS61102569A (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991010954A1 (en) * 1990-01-19 1991-07-25 Alliant Computer Systems Corporation A risc vectorization system
US5345450A (en) * 1993-03-26 1994-09-06 Vlsi Technology, Inc. Method of compressing and decompressing simulation data for generating a test program for testing a logic device
US5369594A (en) * 1992-06-18 1994-11-29 International Business Machines Corporation Conjugate gradient method in computer-aided circuit design
US5384720A (en) * 1993-06-10 1995-01-24 Hitachi Micro Systems Inc. Logic circuit simulator and logic simulation method having reduced number of simulation events
US5519848A (en) * 1993-11-18 1996-05-21 Motorola, Inc. Method of cell characterization in a distributed simulation system
US5856933A (en) * 1994-06-03 1999-01-05 University Of South Florida System and method for digital simulation of an electrical circuit
US6370493B1 (en) 1998-09-10 2002-04-09 Lsi Logic Corporation Simulation format creation system and method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0624072U (ja) * 1992-08-26 1994-03-29 株式会社ノーリツ 防水パンの結合構造

Citations (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4070705A (en) * 1975-11-20 1978-01-24 The Singer Company Simulation apparatus
US4087794A (en) * 1973-01-02 1978-05-02 International Business Machines Corporation Multi-level storage hierarchy emulation monitor
US4229790A (en) * 1978-10-16 1980-10-21 Denelcor, Inc. Concurrent task and instruction processor and method
US4247941A (en) * 1979-06-28 1981-01-27 Honeywell Information Systems Inc. Simulator for bit and byte synchronized data network
US4306286A (en) * 1979-06-29 1981-12-15 International Business Machines Corporation Logic simulation machine
US4308616A (en) * 1979-05-29 1981-12-29 Timoc Constantin C Structure for physical fault simulation of digital logic
US4342093A (en) * 1979-05-15 1982-07-27 Hitachi, Ltd. Method of digital logic simulation
US4351025A (en) * 1979-07-06 1982-09-21 Hall Jr William B Parallel digital computer architecture
US4365297A (en) * 1980-12-29 1982-12-21 Forney Engineering Company Industrial control system with distributed computer implemented logic
US4396978A (en) * 1979-02-19 1983-08-02 U.S. Philips Corporation Multiprocessor system with switchable address space
US4466063A (en) * 1979-11-07 1984-08-14 U.S. Philips Corporation System intercommunication processor used in distributed data processing system
US4584642A (en) * 1982-10-21 1986-04-22 Tokyo Shibaura Denki Kabushiki Kaisha Logic simulation apparatus
US4587625A (en) * 1983-07-05 1986-05-06 Motorola Inc. Processor for simulating digital structures
US4590581A (en) * 1983-05-09 1986-05-20 Valid Logic Systems, Inc. Method and apparatus for modeling systems of complex circuits
US4604718A (en) * 1983-04-25 1986-08-05 Simulated Designs, Ltd. Computer simulation system
US4635218A (en) * 1983-05-09 1987-01-06 Valid Logic Systems Method for simulating system operation of static and dynamic circuit devices
US4644487A (en) * 1983-04-09 1987-02-17 International Computers Limited Method and apparatus for verifying the design of digital electronic components
US4656580A (en) * 1982-06-11 1987-04-07 International Business Machines Corporation Logic simulation machine
US4656632A (en) * 1983-11-25 1987-04-07 Giordano Associates, Inc. System for automatic testing of circuits and systems
US4751637A (en) * 1984-03-28 1988-06-14 Daisy Systems Corporation Digital computer for implementing event driven simulation algorithm
US4763288A (en) * 1985-12-31 1988-08-09 Schlumberger Systems & Services, Inc. System for simulating electronic digital circuits
US4783741A (en) * 1983-08-08 1988-11-08 Bernhard Mitterauer Computer system for simulating reticular formation operation
US4785416A (en) * 1984-01-06 1988-11-15 Stringer Philip J Microprocessor timing emulator having a "Wait" state
US4788683A (en) * 1986-01-14 1988-11-29 Ibm Corporation Data processing system emulation with microprocessor in place
US4873630A (en) * 1985-07-31 1989-10-10 Unisys Corporation Scientific processor to support a host processor referencing common memory

Patent Citations (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4087794A (en) * 1973-01-02 1978-05-02 International Business Machines Corporation Multi-level storage hierarchy emulation monitor
US4070705A (en) * 1975-11-20 1978-01-24 The Singer Company Simulation apparatus
US4229790A (en) * 1978-10-16 1980-10-21 Denelcor, Inc. Concurrent task and instruction processor and method
US4396978A (en) * 1979-02-19 1983-08-02 U.S. Philips Corporation Multiprocessor system with switchable address space
US4342093A (en) * 1979-05-15 1982-07-27 Hitachi, Ltd. Method of digital logic simulation
US4308616A (en) * 1979-05-29 1981-12-29 Timoc Constantin C Structure for physical fault simulation of digital logic
US4247941A (en) * 1979-06-28 1981-01-27 Honeywell Information Systems Inc. Simulator for bit and byte synchronized data network
US4306286A (en) * 1979-06-29 1981-12-15 International Business Machines Corporation Logic simulation machine
US4351025A (en) * 1979-07-06 1982-09-21 Hall Jr William B Parallel digital computer architecture
US4466063A (en) * 1979-11-07 1984-08-14 U.S. Philips Corporation System intercommunication processor used in distributed data processing system
US4365297A (en) * 1980-12-29 1982-12-21 Forney Engineering Company Industrial control system with distributed computer implemented logic
US4656580A (en) * 1982-06-11 1987-04-07 International Business Machines Corporation Logic simulation machine
US4584642A (en) * 1982-10-21 1986-04-22 Tokyo Shibaura Denki Kabushiki Kaisha Logic simulation apparatus
US4644487A (en) * 1983-04-09 1987-02-17 International Computers Limited Method and apparatus for verifying the design of digital electronic components
US4604718A (en) * 1983-04-25 1986-08-05 Simulated Designs, Ltd. Computer simulation system
US4590581B1 (ja) * 1983-05-09 1987-06-09
US4590581A (en) * 1983-05-09 1986-05-20 Valid Logic Systems, Inc. Method and apparatus for modeling systems of complex circuits
US4635218A (en) * 1983-05-09 1987-01-06 Valid Logic Systems Method for simulating system operation of static and dynamic circuit devices
US4587625A (en) * 1983-07-05 1986-05-06 Motorola Inc. Processor for simulating digital structures
US4783741A (en) * 1983-08-08 1988-11-08 Bernhard Mitterauer Computer system for simulating reticular formation operation
US4656632A (en) * 1983-11-25 1987-04-07 Giordano Associates, Inc. System for automatic testing of circuits and systems
US4785416A (en) * 1984-01-06 1988-11-15 Stringer Philip J Microprocessor timing emulator having a "Wait" state
US4751637A (en) * 1984-03-28 1988-06-14 Daisy Systems Corporation Digital computer for implementing event driven simulation algorithm
US4873630A (en) * 1985-07-31 1989-10-10 Unisys Corporation Scientific processor to support a host processor referencing common memory
US4763288A (en) * 1985-12-31 1988-08-09 Schlumberger Systems & Services, Inc. System for simulating electronic digital circuits
US4788683A (en) * 1986-01-14 1988-11-29 Ibm Corporation Data processing system emulation with microprocessor in place

Non-Patent Citations (12)

* Cited by examiner, † Cited by third party
Title
19th Design Automation Conference, 1982 IEEE, The Yorktown Simulation Engine: Introduction, Gregory F. Pfister, pp. 51 59. *
19th Design Automation Conference, 1982 IEEE, The Yorktown Simulation Engine: Introduction, Gregory F. Pfister, pp. 51-59.
20th Design Automation Conference, 1983 IEEE, HAL; A Block Level Hardware Logic Simulator, by Tohru Sasaki, et al., pp. 150 156. *
20th Design Automation Conference, 1983 IEEE, HAL; A Block Level Hardware Logic Simulator, by Tohru Sasaki, et al., pp. 150-156.
Gurd et al, "Data Driven System for High Speed Parallel Computing-Part 1: Structuring Software for Parallel Execution", Computer Design, Jun. 1980, pp. 91-100.
Gurd et al, "Data Driven System for High Speed Parallel Computing-Part 2: Hardware Design", Computer Design, Jul. 1980, pp. 97-106.
Gurd et al, Data Driven System for High Speed Parallel Computing Part 1: Structuring Software for Parallel Execution , Computer Design, Jun. 1980, pp. 91 100. *
Gurd et al, Data Driven System for High Speed Parallel Computing Part 2: Hardware Design , Computer Design, Jul. 1980, pp. 97 106. *
Kai Hwang, "Computer Architecture and Parallel Processing", McGraw-Hill, 1984, pp. 32-35, 374-375, 396-399, 448-449, 452-453, 762-763.
Kai Hwang, Computer Architecture and Parallel Processing , McGraw Hill, 1984, pp. 32 35, 374 375, 396 399, 448 449, 452 453, 762 763. *
R. Barto et al., A Computer Architecture for Digital Logic Simulation, Electronic Engineering (vol. 52, No. 642, Sep. 1980), pp. 35 36, 41, 45, 47, 50, 54, 56, 60, 63, 66. *
R. Barto et al., A Computer Architecture for Digital Logic Simulation, Electronic Engineering (vol. 52, No. 642, Sep. 1980), pp. 35-36, 41, 45, 47, 50, 54, 56, 60, 63, 66.

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991010954A1 (en) * 1990-01-19 1991-07-25 Alliant Computer Systems Corporation A risc vectorization system
US5369594A (en) * 1992-06-18 1994-11-29 International Business Machines Corporation Conjugate gradient method in computer-aided circuit design
US5345450A (en) * 1993-03-26 1994-09-06 Vlsi Technology, Inc. Method of compressing and decompressing simulation data for generating a test program for testing a logic device
US5384720A (en) * 1993-06-10 1995-01-24 Hitachi Micro Systems Inc. Logic circuit simulator and logic simulation method having reduced number of simulation events
US5519848A (en) * 1993-11-18 1996-05-21 Motorola, Inc. Method of cell characterization in a distributed simulation system
US5856933A (en) * 1994-06-03 1999-01-05 University Of South Florida System and method for digital simulation of an electrical circuit
US6131081A (en) * 1994-06-03 2000-10-10 University Of South Florida System and method for digital simulation of an electrical circuit
US6370493B1 (en) 1998-09-10 2002-04-09 Lsi Logic Corporation Simulation format creation system and method

Also Published As

Publication number Publication date
JPS61102569A (ja) 1986-05-21

Similar Documents

Publication Publication Date Title
Nanya et al. TITAC: Design of a quasi-delay-insensitive microprocessor
US4787062A (en) Glitch detection by forcing the output of a simulated logic device to an undefined state
US5721953A (en) Interface for logic simulation using parallel bus for concurrent transfers and having FIFO buffers for sending data to receiving units when ready
JPH04227574A (ja) ロジック・シミュレーション・マシンのための全イベント・トレース・ギャザラ
US4584642A (en) Logic simulation apparatus
US7054802B2 (en) Hardware-assisted design verification system using a packet-based protocol logic synthesized for efficient data loading and unloading
US4982361A (en) Multiple loop parallel pipelined logic simulation system
Agrawal et al. A hardware logic simulation system
JP3285430B2 (ja) データ駆動型情報処理装置
US3997771A (en) Apparatus and method for performing an arithmetic operation and multibit shift
US20050283690A1 (en) Wrapper serial scan chain functional segmentation
KR900008804B1 (ko) 선견 터미날 카운터 및 터미날 카운트 신호 발생 방법
JPS6141017B2 (ja)
Myers et al. The design of an asynchronous memory management unit
JP2638613B2 (ja) プログラマブル アクセラレータ及びその方法
CN119583232B (zh) PCIe交换节点INT中断处理方法及系统
US5018092A (en) Stack-type arithmetic circuit
JP2781081B2 (ja) 並列演算機構による論理演算方法
JPS6173075A (ja) Ｌｓｉ論理状態抽出方式
JPH0195365A (ja) クリティカルパスの解析処理方式
Joshua Review of Patents Issued to Computer Architecture Companies in 2021—Part II
JP2629359B2 (ja) 論理シミュレータ
JPH0668055A (ja) ディジタル信号処理装置
JP2756143B2 (ja) 多出力演算処理方式
JP2806459B2 (ja) フリップフロップが評価可能な論理シミュレーション装置

Legal Events

Date Code Title Description
AS Assignment

Owner name: HITACHI, LTD., A CORP. OF JAPAN, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:MIYAOKA, SHINICHIRO;MURAMATSU, AKIRA;FUNABASHI, MOTOHISA;REEL/FRAME:005371/0154

Effective date: 19851007

Owner name: HITACHI, LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MIYAOKA, SHINICHIRO;MURAMATSU, AKIRA;FUNABASHI, MOTOHISA;REEL/FRAME:005371/0154

Effective date: 19851007

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20030101