US5287480A - Cache memory for independent parallel accessing by a plurality of processors - Google Patents

Cache memory for independent parallel accessing by a plurality of processors Download PDF

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Publication number
US5287480A
US5287480A US07/765,818 US76581891A US5287480A US 5287480 A US5287480 A US 5287480A US 76581891 A US76581891 A US 76581891A US 5287480 A US5287480 A US 5287480A
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Prior art keywords
cache memory
ports
words
read
buses
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US07/765,818
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Alfons-Josef Wahr
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Siemens AG
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Siemens AG
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible

Definitions

  • the present invention relates to computers and is more particularly concerned with a cache memory structure that has a plurality of reading ports for reading data therefrom and a plurality of ports for writing data thereinto.
  • Cache memories are well-known in the art in computer architecture. Such memories serve as buffers between operational units that have different data flow rates within a data processing system and communicate with one another.
  • a command computer can be considered as an example, the command computer having the commands to be processed made available thereto from a main memory. These commands must be offered to the computer with shorter access time than is possible given a main memory having comparatively-great memory capacity.
  • the cache memory is operated such that data and commands requested by the command computer during a program run are located in the cache memory with high probability and can therefore be made available with a short access time.
  • the cache memory is increasingly being integrated on a chip next to the computer hardware core in computer implementation. It should, therefore, be noted that the capacity of the cache memory is being increasingly expanded. This leads to the fact that a cache memory can no longer be economically fully used by a single central processing unit (CPU).
  • CPU central processing unit
  • the object of the present invention is to provide a cache memory structure having a cache memory, whereby the cache memory can be used not only by one CPU, but by a plurality of CPUs.
  • a cache memory structure having m bus terminals and which comprises a cache memory having k (where k ⁇ m) cache memory ports for reading data from the cache memory and p (where p ⁇ m) cache memory ports for writing data into the cache memory.
  • a switching matrix network has controllable switch elements for producing a connection of the cache memory ports to the bus terminals and a cache memory controller for controlling the switch elements of the switching matrix network.
  • the cache memory can be composed of a cache memory bank or a plurality of cache memory banks.
  • the access to the cache memory bank or banks occurs via internal cache memory ports that can be realized either as unidirectional ports or as bidirectional ports.
  • the number of these ports can be selected smaller than the number of bus terminals that are connected to buses that lead, for example, to units of a computer, such as a CPU or processor elements, to a command unit or to a main memory. What is then achieved with the assistance of the switching matrix network is that each bus terminal can be connected to ports of the cache memory.
  • the switching matrix network can be realized in a standard manner as a connection network, crossbar distributor or crossbar switch. It contains switch elements by way of which a respective bus terminal can be connected to a port of the cache memory. It is, therefore, advantageous to select the ports of the cache memory to have i words in width, so that a plurality of bus terminals can be connected in parallel to one or more cache memory ports via an appropriate control of the switch elements.
  • FIG. 1 is a block circuit diagram of a processor comprising a plurality of processing elements
  • FIG. 2 is a schematic representation of a first realization of a cache memory structure constructed in accordance with the present invention
  • FIG. 3 is a schematic representation of a second realization of a cache memory structure constructed in accordance with the present invention.
  • FIG. 4 is a schematic representation of a third realization of a cache memory structure constructed in accordance with the present invention.
  • a computer (processor) P comprises n processor elements (also referred to as arithmetic units or CPUs), four such processors PE0-PE3 being illustrated, a cache memory CA, an instruction unit IU, a register bank RG and, potentially, a storage memory CS.
  • the computer P is connected to a main memory MM via the cache memory CA.
  • the processors PE0-PE3 are connected via a plurality of data buses DB0-DB3 to the cache memory device CA. These processors are also connected via instruction buses IB0-IB3 to the instruction unit IU, to the register bank RG via register buses RB and to the storage control CS via control lines MI0-MI3.
  • the microprograms that are required for the operation of the processors PE0-PE3 can reside in the storage memory CS.
  • the instruction unit IU can likewise be connected to the cache memory CA, just as the main memory MM, via a bus PI-MM. It is also possible that the instruction unit IU is connected to the register bank RG via a bus RBI.
  • the structure of the cache memory CA of the computer P shall be set forth below. Referring to FIG.
  • the cache memory structure CA comprises a cache memory CSB, a switching matrix network KF and a cache memory controller CCU.
  • the cache memory CSB can be composed of a memory bank or of a plurality of memory banks and has a known structure.
  • the cache memory CSB provides cache memory ports WP0, RP0, RP1, RP2 that are unidirectionally realized in this exemplary embodiment.
  • the port WP0 (there can also be a plurality of write ports) serves the purpose of writing into the cache memory; the ports RP0-RP2 serve the purpose of reading from the cache memory.
  • the cache memory ports form the interface of the cache memory CSB with the switching matrix network KF.
  • the switching matrix network KF is composed of switch elements BK that are arranged at the matrix points MP of the switching matrix network KF.
  • port terminal lines PAS meet bus terminal lines BAS to whose bus terminals BA the data buses DB of the processor elements PE are connected.
  • the bus PI-MM to the main memory MM, and the instruction bus DBI is connected to the instruction unit IU.
  • the buses can, therefore, be connected to the ports with the assistance of the switch elements BK.
  • the buses can have the width of a word or the width of a plurality of words.
  • the analogous case applies for the cache memory ports. These can also have the width of a word or the width of a plurality of words. It is assumed, for example, in the exemplary embodiment of FIG. 2 that the buses DB0-DB3 are one word wide, whereas the buses DBI and PI-MM as well as the ports are four words wide. In general, the buses are i words wide and the ports are j words wide, where i and j are whole numbers.
  • the control of the switch elements BK occurs with the assistance of the cache memory controller CCU.
  • the cache memory controller CCU generates control signals S-KF that are supplied to the switching matrix network KF and drive the individual switch elements BK located therein.
  • the cache memory controller CCU receives control signals (request signals) S-RE via the buses DB, DBI, PI-MM that it then acknowledges with signals S-AC when an access to the cache memory CSB can be implemented.
  • the control of the cache memory CSB required for this purpose occurs via control signals S-CSB.
  • FIG. 2 illustrates a first realization of a switching matrix network KF.
  • a plurality of switch elements BK that is the same in number as the word width of the cache memory ports are located at the matrix crosspoints MP of the switching matrix network KF. Since the cache memory ports are four words wide in this exemplary embodiment, four switch elements BK are, respectively, arranged at the matrix points MP. Since the switch elements can be separately selected per matrix point MP, it is possible that up to four words can be transmitted in parallel via a cache memory port to the cache memory CSB or, respectively, can be read therefrom.
  • the cache memory port WP0 is thereby used for writing, and the cache memory ports RP0-RP2 are used for reading.
  • the plurality p of write ports WP needed for the processor elements PE can be estimated with the assistance of the relationship.
  • p denotes the number of write ports at the cache memory CSB
  • w w represents the write access probability
  • W w-miss represents the probability of a cache memory miss
  • t w-La denotes the write access time to the main memory MM
  • W PBi denotes the mean access probability of the external bus DB
  • n denotes the number of connected processor elements PE
  • f denotes a parallelism factor, i.e. how many accesses are possible on average, in parallel, per port.
  • the plurality k of read ports RP can be calculated in a corresponding manner according to the following relationship.
  • k is the plurality of read ports at the cache memory CSB
  • w r is the read access probability
  • w r-Miss is the probability of a cache memory miss
  • t r-La is the read access time to the main memory
  • w PBi is the main access probability of the data bus DB
  • n is the number of connected processor elements PE
  • f denotes the parallelism factor.
  • FIG. 3 A further realization of the switching matrix network KF results from FIG. 3.
  • the switch element BK is capable of connecting the bus terminal lines BAS to the cache memory ports.
  • the divisions of the words to be transmitted onto the cache memory ports that are several words wide occurs with the assistance of multiplexers (demultiplexers) WM.
  • a savings in the number of switch elements BK is achieved with this construction and, therefore, the expense is considerably reduced.
  • FIG. 4 A further possible solution can be seen in FIG. 4.
  • Two switch elements BK by way of which each bus terminal line BAS can be coupled to two port terminal lines are provided here per matrix point MP of the switching matrix KF.
  • the instruction unit IU has its own read port available, for example the read port RBI (FIG. 1).
  • the processor elements PE can then not access this read port or can only access the same with a low priority.
  • An analogous case also applies to the main memory MM.
  • an independent read port for example the read port RPO, is beneficial.
  • a separate write port can also be provided.
  • the cache memory controller CCU controls the switching matrix network KF with the assistance of the control signals S-KF and controls the cache memory CSB with the assistance of the control signals S-CSB. Furthermore, the control signals supplied to the cache memory controller CCU by the buses DB are processed, like the request signals S-RE and possible access collisions are thereby localized and eliminated.
  • the request signals S-RE arriving from the processor elements PE are processed according to the declared priority.
  • By driving the switch elements BK two or more accesses with a maximum of i accesses can occur in parallel onto a port that is i words wide.
  • the word addresses for each word are connected through from the buses to the cache memory ports.
  • the requests S-RE are acknowledged by the cache memory controller (CCU, FIG. 2) with the signals S-AC. In case of a miss, a necessary main memory access is triggered, and the new datum is transmitted into the cache memory CSB.
  • Control signals are transmitted on the buses DB or PI-MM to the cache memory controller CCU or, respectively, from the cache memory controller to the switching matrix network KF, to the cache memory CSB or to the data buses DB, PI-MM.
  • the control signals are therefore provided for the operation of the cache memory controller CCU.
  • the corresponding control signals can be triggered with the assistance of a microprogram contained in the cache memory controller.
  • the switch elements can be bus couplers having a known structure.
  • the switch elements must be suitable for connecting through a datum that is i words wide on the buses.
  • the buses are one word wide, as in the exemplary embodiment, and, for example, the word comprises 36 bits, the switch element must be capable of switching 36 bits.
  • the switch elements KE for the instruction bus DBI and for the memory bus PI-MM can be arranged as shown on the drawings. Therefore, it is possible to read an information word that is i words wide from the cache memory CSB or, respectively, to write the same thereinto.
  • the cache memory ports can be constructed, therefore, in a standard manner.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
US07/765,818 1990-09-26 1991-09-26 Cache memory for independent parallel accessing by a plurality of processors Expired - Fee Related US5287480A (en)

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Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557768A (en) * 1993-07-28 1996-09-17 International Business Machines Corporation Functional pipelined virtual multiport cache memory with plural access during a single cycle
US5636358A (en) * 1991-09-27 1997-06-03 Emc Corporation Method and apparatus for transferring data in a storage device including a dual-port buffer
US5689729A (en) * 1991-12-06 1997-11-18 Hitachi, Ltd. Storage subsystem having plurality of access paths permitting independent access to cache memory from host and independent access to the cache from rotating storage device
US5752066A (en) * 1992-01-06 1998-05-12 International Business Machines Corporation Data processing system utilizing progammable microprogram memory controller
US5802580A (en) * 1994-09-01 1998-09-01 Mcalpine; Gary L. High performance digital electronic system architecture and memory circuit thereof
US5893147A (en) * 1994-12-22 1999-04-06 Intel Corporation Method and apparatus for distinguishing system memory data from alternative memory data in a shared cache memory
US5940466A (en) * 1997-10-29 1999-08-17 Micron Electronics, Inc. Apparatus for counting parts in a tray
US6161153A (en) * 1998-07-30 2000-12-12 Micron Technology, Inc. Method for sharing data buffers from a buffer pool
US6282589B1 (en) 1998-07-30 2001-08-28 Micron Technology, Inc. System for sharing data buffers from a buffer pool
US6647439B1 (en) * 1999-08-31 2003-11-11 Koninklijke Philips Electronics N.V. Arrangement with a plurality of processors sharing a collective memory
US20040093465A1 (en) * 2002-10-28 2004-05-13 Quicksilver Technology, Inc. Cache for instruction set architecture
US20060004942A1 (en) * 2004-06-30 2006-01-05 Sun Microsystems, Inc. Multiple-core processor with support for multiple virtual processors
US7685354B1 (en) * 2004-06-30 2010-03-23 Sun Microsystems, Inc. Multiple-core processor with flexible mapping of processor cores to cache banks

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3784766B2 (ja) 2002-11-01 2006-06-14 株式会社半導体理工学研究センター 多ポート統合キャッシュ

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4158235A (en) * 1977-04-18 1979-06-12 Burroughs Corporation Multi port time-shared associative buffer storage pool
US4449183A (en) * 1979-07-09 1984-05-15 Digital Equipment Corporation Arbitration scheme for a multiported shared functional device for use in multiprocessing systems
EP0214718A2 (de) * 1985-07-22 1987-03-18 Alliant Computer Systems Corporation Digitalrechner
EP0284751A2 (de) * 1987-04-03 1988-10-05 International Business Machines Corporation Cache-Speicher
US4905114A (en) * 1985-12-28 1990-02-27 Hewlett-Packard Company Disk drive compatible tape cartridge with device for positioning the tape relative to the disk drive
US4975872A (en) * 1988-11-17 1990-12-04 Matsushita Electric Industrial Co., Ltd. Dual port memory device with tag bit marking
US5056015A (en) * 1988-03-23 1991-10-08 Du Pont Pixel Systems Limited Architectures for serial or parallel loading of writable control store

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4158235A (en) * 1977-04-18 1979-06-12 Burroughs Corporation Multi port time-shared associative buffer storage pool
US4449183A (en) * 1979-07-09 1984-05-15 Digital Equipment Corporation Arbitration scheme for a multiported shared functional device for use in multiprocessing systems
EP0214718A2 (de) * 1985-07-22 1987-03-18 Alliant Computer Systems Corporation Digitalrechner
US4905114A (en) * 1985-12-28 1990-02-27 Hewlett-Packard Company Disk drive compatible tape cartridge with device for positioning the tape relative to the disk drive
EP0284751A2 (de) * 1987-04-03 1988-10-05 International Business Machines Corporation Cache-Speicher
US5056015A (en) * 1988-03-23 1991-10-08 Du Pont Pixel Systems Limited Architectures for serial or parallel loading of writable control store
US4975872A (en) * 1988-11-17 1990-12-04 Matsushita Electric Industrial Co., Ltd. Dual port memory device with tag bit marking

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, "Shared Instruction and/or Data Caches in a Multiprocessing System," vol. 27, No. 12, May 1985 pp. 6845-6846.
IBM Technical Disclosure Bulletin, Shared Instruction and/or Data Caches in a Multiprocessing System, vol. 27, No. 12, May 1985 pp. 6845 6846. *

Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5636358A (en) * 1991-09-27 1997-06-03 Emc Corporation Method and apparatus for transferring data in a storage device including a dual-port buffer
US20040010640A1 (en) * 1991-12-06 2004-01-15 Hitachi, Ltd. External storage subsystem
US7010623B2 (en) 1991-12-06 2006-03-07 Hitachi, Ltd. External storage subsystem
US5689729A (en) * 1991-12-06 1997-11-18 Hitachi, Ltd. Storage subsystem having plurality of access paths permitting independent access to cache memory from host and independent access to the cache from rotating storage device
US7702819B2 (en) 1991-12-06 2010-04-20 Hitachi, Ltd. External storage subsystem
US7330909B2 (en) 1991-12-06 2008-02-12 Hitachi, Ltd. External storage subsystem
US7243166B2 (en) 1991-12-06 2007-07-10 Hitachi, Ltd. External storage subsystem
US7219166B2 (en) 1991-12-06 2007-05-15 Hitachi, Ltd. External storage subsystem
US5951655A (en) * 1991-12-06 1999-09-14 Hitachi, Ltd. External storage subsystem having independent access paths for permitting independent access from a host and a storage device to respective cache memories
US7099960B2 (en) 1991-12-06 2006-08-29 Hitachi, Ltd. External storage subsystem
US20040010642A1 (en) * 1991-12-06 2004-01-15 Hitachi, Ltd. External storage subsystem
US6981066B2 (en) 1991-12-06 2005-12-27 Hitachi, Ltd. External storage subsystem
US20040010659A1 (en) * 1991-12-06 2004-01-15 Hitachi, Ltd. External storage subsystem
US20040010658A1 (en) * 1991-12-06 2004-01-15 Hitachi, Ltd. External storage subsystem
US20040010639A1 (en) * 1991-12-06 2004-01-15 Hitachi, Ltd. External storage subsystem
US6981067B2 (en) 1991-12-06 2005-12-27 Hitachi, Ltd. External storage subsystem
US20040010641A1 (en) * 1991-12-06 2004-01-15 Hitachi, Ltd. External storage subsystem
US6745261B2 (en) 1991-12-06 2004-06-01 Hitachi, Ltd. Method for connecting caches in external storage subsystem
US5752066A (en) * 1992-01-06 1998-05-12 International Business Machines Corporation Data processing system utilizing progammable microprogram memory controller
US5557768A (en) * 1993-07-28 1996-09-17 International Business Machines Corporation Functional pipelined virtual multiport cache memory with plural access during a single cycle
US5561781A (en) * 1993-07-28 1996-10-01 International Business Machines Corporation Port swapping for improved virtual SRAM performance and processing of concurrent processor access requests
US5802580A (en) * 1994-09-01 1998-09-01 Mcalpine; Gary L. High performance digital electronic system architecture and memory circuit thereof
US5893147A (en) * 1994-12-22 1999-04-06 Intel Corporation Method and apparatus for distinguishing system memory data from alternative memory data in a shared cache memory
US5940466A (en) * 1997-10-29 1999-08-17 Micron Electronics, Inc. Apparatus for counting parts in a tray
US6161153A (en) * 1998-07-30 2000-12-12 Micron Technology, Inc. Method for sharing data buffers from a buffer pool
US6282589B1 (en) 1998-07-30 2001-08-28 Micron Technology, Inc. System for sharing data buffers from a buffer pool
US6647439B1 (en) * 1999-08-31 2003-11-11 Koninklijke Philips Electronics N.V. Arrangement with a plurality of processors sharing a collective memory
US20040093465A1 (en) * 2002-10-28 2004-05-13 Quicksilver Technology, Inc. Cache for instruction set architecture
US7340562B2 (en) * 2002-10-28 2008-03-04 Nvidia Corporation Cache for instruction set architecture
US20060004942A1 (en) * 2004-06-30 2006-01-05 Sun Microsystems, Inc. Multiple-core processor with support for multiple virtual processors
US7685354B1 (en) * 2004-06-30 2010-03-23 Sun Microsystems, Inc. Multiple-core processor with flexible mapping of processor cores to cache banks
US7873776B2 (en) 2004-06-30 2011-01-18 Oracle America, Inc. Multiple-core processor with support for multiple virtual processors

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JPH04257949A (ja) 1992-09-14
EP0477595A3 (en) 1992-11-19
EP0477595A2 (de) 1992-04-01

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