US5565698A - IC protection structure having n-channel MOSFET with n-type resistor region - Google Patents

IC protection structure having n-channel MOSFET with n-type resistor region Download PDF

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Publication number
US5565698A
US5565698A US08/498,822 US49882295A US5565698A US 5565698 A US5565698 A US 5565698A US 49882295 A US49882295 A US 49882295A US 5565698 A US5565698 A US 5565698A
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region
drain
recited
drain contact
contact region
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Expired - Fee Related
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US08/498,822
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English (en)
Inventor
Cornelius Obermeier
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TDK Micronas GmbH
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Deutsche ITT Industries GmbH
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/911—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using passive elements as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs

Definitions

  • the present invention relates generally to a semiconductor device, and more particularly to an integrated circuit protection structure.
  • Electrostatic discharge currents may reach the pins during handling of the IC as a result of discharge of charged objects, e.g. through a person, through metal tools, through a case, etc.
  • a protective circuit typically is connected between an internal circuit and a bonding pad to which a signal is applied. The protective circuit blunts the abnormal input energy by.
  • a protection arrangement for integrated circuits utilizes an n-channel MOS field-effect transistor (transistor) which is designed to protect the inputs or the outputs of the IC against electrostatic discharge overloading.
  • transistor which is connected to the pin via the bonding pad, i.e., to the respective input or output of the IC, and which always contains a parasitic bipolar transistor, is changed to the bipolar state, in which it can be operated with a high current at a lower voltage.
  • This operation in the bipolar state is referred to as "snapback". Because of the voltage reduction in the bipolar mode, the transistor can absorb more power. To provide further protection for the transistor, the change to the bipolar state should be as fast as possible and the bipolar state should be kept as stable as possible, since a second "snapback", a "second breakdown" of the bipolar transistor, would destroy the latter.
  • the present invention is a protection structure for integrated circuits with an n-channel MOS field-effect transistor having a more stable bipolar state, with the change to the bipolar state occurring fast.
  • an n-type resistor region doped more lightly than the drain region and the drain contact region is formed to provide the electrically conductive connection between the drain region and the drain contact region.
  • the n-channel MOS transistor When a positive voltage pulse is applied to the drain contact region, the n-channel MOS transistor will go into a bipolar operating state upon reaching the drain-source or drain-substrate breakdown voltage.
  • the conductor paths are typically connected to ground.
  • the n-well forms a series resistor between the drain region and the drain contact region of the respective transistor. It also forms a pn junction between the drain region and the channel, the collector pn junction, which extends deep into the substrate. Because of the series resistance of this n-well, during the change to the bipolar state, contractions of the current occurring at the pn junction are prevented.
  • the transistor In the bipolar state, the transistor can absorb more power than with conventional arrangements. By connecting two or more transistors in parallel, the current is distributed even further, so that the power can be absorbed by both transistors, since the dissipation is distributed over an even larger area.
  • FIG. 1 is a top view of an arrangement of two parallel-connected transistors in accordance with the invention
  • FIG. 2 is a is a cross section of the arrangement of FIG. 1 through cut B--B;
  • FIG. 3 is a schematic of the present invention used in the input portion of an IC
  • FIG. 4 is a schematic of the present invention used in the output portion of an IC.
  • a protection arrangement for integrated circuits (ICs) with an n-channel MOS field-effect transistor (transistor) which is designed to protect the inputs or the outputs of the IC against electrostatic discharge overloading is described in an article entitled "A Synthesis Of ESD Input Protection Scheme" by Charvaka Duvvury et al., published in EOS/ESD Symposium Proceedings 1991.
  • the transistor which is connected to the pin, i.e., to the respective input or output of the IC, and which always contains a parasitic bipolar transistor is changed to the bipolar state, in which it can be operated with a high current at a lower voltage. This operation in the bipolar state is referred to as "snapback".
  • the transistor can absorb more power.
  • the change to the bipolar state should be as fast as possible and the bipolar state should be kept as stable as possible, since a second "snapback", a "second breakdown" of the bipolar transistor, would destroy the latter.
  • the present invention achieves this improvement by providing below the drain region and the drain contact region an n-type resistor region doped more lightly than the drain region and the drain contact region so as to provide the electrically conductive connection between the drain region and the drain contact region.
  • the drain-gate edge is formed by a shallow, heavily doped pn junction. This ensures a low breakdown voltage for the change to the bipolar mode, i.e., for snapback, which this occurs fast. Because of the n-type resistor region provided in accordance with the invention, this more lightly doped resistor region extends further into the interior of the substrate near the drain edge. This eliminates the risk of thermal overloading during the change to the bipolar state. This is explained by the fact that at the breakdown voltage, current contractions occur at the pn junction which now distribute along the drain/gate edge.
  • n-type resistor region which is not bridged with the n-type dopants of the drain region and the drain contact region.
  • the drain region and the drain contact region may be n-type doped at the same level.
  • the n-channel transistor can be fabricated without additional steps and without additional masks by the normal MOS process for manufacturing the IC.
  • the resistor region does not extend farther than the gate/drain edge of the drain region. This provides good coupling of the resistor region to the drain region and makes it possible to cover as large an area of the drain region as possible, the drain region being limited by the fact that the size of the channel formed below the gate electrode between the source region and the drain region is not affected.
  • the resistor region extends below the entire drain contact region, so that good contact is ensured between the resistor region and the drain contact region.
  • the width of the resistor region is greater than 10 ⁇ m, preferable 100 ⁇ m. Compared with the usual dimensions of high-performance n-channel MOS transistors, this provides a good value.
  • the width of the resistor region is then slightly greater than the width of the transistors. It is advantageous to use the n-well of the CMOS process as the resistor region.
  • the depth of the resistor region is substantially greater than the depth of the drain region or drain contact region, by a factor of at least 1.5 and preferably by a factor of 3 to 5.
  • the depth can be chosen in accordance with the desired function of the individual transistors.
  • an n-type region below the source region which is doped more lightly than the source region.
  • the drain region may be connected via a contact directly to an input element, particularly a gate electrode, of an input transistor of the IC to be protected.
  • the protection against electrostatic charging provided by the arrangement of the present invention is also effective with transistors having very shallow source and drain contacts, which are used in high-speed circuits.
  • Such transistors can also be implemented and used to advantage in silicided technologies. This applies both if only one of the gate, source, and drain regions is silicided and if all of these regions are silicided.
  • a transistor designed in accordance with the invention is particularly advantageous, because silicided regions have very low resistivity, so that normally such transistors are particularly vulnerable under electrostatic conditions.
  • the protection provided by the resistor region is particularly effective.
  • the present invention can be used to protect the output of an IC. It may then itself form the output stage of the IC, so that no separate component is required for the protection device. Space can thus be saved in the chip technology used.
  • the present invention finds use, for example, as open-drain output, as part of a push-pull stage, and in combined outputs and inputs in CMOS technology.
  • the terminal of the drain region of the protection structure is connected via a low-resistivity path to an input element, such as a gate electrode of a transistor, with the gate electrode connected to the source potential, commonly ground potential.
  • the protection structure according to the invention is also used between supply leads, particularly between the positive supply lead and ground, of an IC or of a subcircuit of an IC.
  • a drain region 2 and a source region 3 are provided for each of the two n-channel transistors. Also provided is a drain contact region 4, which is separate from the drain regions 2 and can be used for both transistors together.
  • the drain contact region 4 is provided with drain contacts 5 for both transistors.
  • the source contacts 6 are provided on the respective source regions 3 of the two transistors.
  • a gate electrode 7 is provided between the drain region 2 and the source region 3 of each of the transistors.
  • a field-oxide layer 9 disposed between the drain region 2 and the drain contact region 4 of each transistor isolates the drain region 2 from the drain contact region 4.
  • the arrangement of the two transistors is symmetrical about the axis of symmetry A.
  • conducting paths 15 and 16 are deposited on the drain and source regions, respectively.
  • the conducting paths are typically of aluminum, and lead to a pad.
  • FIG. 2 there is shown a cross section of the present invention through cut B--B.
  • n-well 10 which is doped more lightly than the drain regions 2 and the drain contact region 4. Since the drain regions 2 are isolated from the drain contact region 4 by the field-oxide layer 9, electrical conduction between the drain regions 2 and the drain contact region 4 takes place via the n-well 10.
  • the n-well 10 extends below the entire drain contact region 4 to the vicinity of the respective gate/drain edges of the drain regions 2. This ensures good contact between the n-well and the drain regions 2 as well as the drain contact region 4.
  • the n-well 10 does not quite reach to the gate/drain edge, so that the channel 11 existing in each transistor between the drain region 2 and the source region 3 below the gate electrode 7 is not narrowed by the n-well 10.
  • the n-well 10 further extends into the substrate 1 by a multiple of the depth of the drain region 2, so that the pn junction is moved further into the interior of the substrate. This creates a deeper, but more lightly doped pn junction than that between the drain region 2 and the channel region 11.
  • the protective arrangement is connected to an input element of the IC, such as a gate electrode of an input transistor.
  • FIG. 3 shows the use of the protection structure according to the invention in the input portion of an IC.
  • the protection structure 17 shows a transistor 18 connected in series with the resistor formed by the resistor region 10.
  • a conductor path 15 connected to thee drain contact region leads to an external pad 19, via which the IC can be connected to external connections.
  • the transistor 18 is connected as a diode, with a conductor path 16 from the source terminal and the gate electrode 7 connected to a first fixed potential V ss , preferably ground.
  • the drain region of the transistor 18 has its terminal 12 connected to an input element 21 of the IC, i.e., of the internal part of the IC which is connected to a first fixed potential V ss and a second fixed potential V cc .
  • the input element is a CMOS inverter stage.
  • FIG. 4 shows a further use of the protection structure according the invention.
  • the protection structure 17 is used here as part of a push-pull output stage 22 of an IC. It consists of several parallel-connected transistors 18 having a resistor connected in series with its drain, the resistor being formed by the resistor region 10.
  • the drain terminal 15 is connected to a pad 19, which is an input/output pad.
  • the parallel-connected transistors 18 with their resistor regions 10 correspond to a protection structure as shown in FIG. 1, with several terminals connected in parallel.
  • the terminal 12 of the drain regions of the protection structure 17 is connected through a resistor 20 to an input 23 of the internal part of the IC.
  • the gate electrodes are driven by a signal line 24 coming from the internal part of the IC.
  • the gate electrodes of p-channel transistors 25 forming the second branch of the push-pull stage are driven by a signal line 26, which also comes from the internal part of the IC.
  • the w/l ratio of the transistors 25 of the second branch of the push-pull stage is substantially greater than the w/1 ratio of the transistors 18 of the first branch.
  • the operation of the transistor arrangement according to the invention is as follows. If, for example, a positive voltage pulse is applied via a pin of the IC to the drain contact region connected to this pin, the n-channel MOS transistor will go into a bipolar operating state upon reaching the drain-source or drain-substrate breakdown voltage. This operating state is also called "npn state".
  • the conductor paths 16 are typically connected to ground.
  • the n-well 10 forms a series resistor between the drain region 2 and the drain contact region 4 of the respective transistor. It also forms a pn junction between the drain region 2 and the channel 11, the collector pn junction, which extends deep into the substrate 1.
  • the transistor can absorb more power than with conventional arrangements. By connecting two or more transistors in parallel, the current is distributed even further, so that the power can be absorbed by both transistors, since the dissipation is distributed over an even larger area.

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
US08/498,822 1994-07-04 1995-07-06 IC protection structure having n-channel MOSFET with n-type resistor region Expired - Fee Related US5565698A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4423591A DE4423591C2 (de) 1994-07-06 1994-07-06 Schutzstruktur für integrierte Schaltungen
DE4423591.7 1994-07-06

Publications (1)

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US5565698A true US5565698A (en) 1996-10-15

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US (1) US5565698A (ja)
EP (1) EP0691683B1 (ja)
JP (2) JPH0855984A (ja)
DE (2) DE4423591C2 (ja)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997020348A1 (en) * 1995-11-30 1997-06-05 Micron Technology, Inc. Structure for esd protection in semiconductor chips
US5663678A (en) * 1996-02-02 1997-09-02 Vanguard International Semiconductor Corporation ESD protection device
US5808343A (en) * 1996-09-20 1998-09-15 Integrated Device Technology, Inc. Input structure for digital integrated circuits
US6137664A (en) * 1995-08-16 2000-10-24 Micron Technology, Inc. Well resistor for ESD protection of CMOS circuits
EP1091397A2 (en) 1999-10-08 2001-04-11 Nec Corporation Input/output buffer with silicide layer and method of manufacturing
US6507074B2 (en) 1995-11-30 2003-01-14 Micron Technology, Inc. Structure for ESD protection in semiconductor chips
EP0994510A3 (en) * 1998-09-25 2003-03-26 Fairchild Semiconductor Corporation LDD structure for electrostatic discharge (ESD) protection device and method of fabrication
US6635930B1 (en) * 1998-09-25 2003-10-21 Infineon Technologies Ag Protective circuit
US20040119142A1 (en) * 2002-09-30 2004-06-24 Alessandro Grossi Process for manufacturing integrated resistive elements with silicidation protection
KR100482362B1 (ko) * 1997-10-14 2005-08-01 삼성전자주식회사 정전기보호용반도체장치및그제조방법
US20070252231A1 (en) * 2006-04-27 2007-11-01 Shiro Usami Semiconductor integrated circuit and system LSI including the same
US8299531B1 (en) * 2001-12-27 2012-10-30 National Semiconductor Corporation CMOS ESD clamp with input and separate output voltage terminal for ESD protection

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6071768A (en) * 1996-05-17 2000-06-06 Texas Instruments Incorporated Method of making an efficient NPN turn-on in a high voltage DENMOS transistor for ESD protection
DE10103297A1 (de) * 2001-01-25 2002-08-22 Infineon Technologies Ag MOS-Transistor
DE10222306B4 (de) * 2002-05-18 2010-11-25 Micronas Gmbh Schutzstruktur gegen elektrostatische Entladungen

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US4246592A (en) * 1979-01-02 1981-01-20 Texas Instruments Incorporated High density static memory cell
US4691217A (en) * 1984-07-25 1987-09-01 Hitachi, Ltd. Semiconductor integrated circuit device
US4902640A (en) * 1987-04-17 1990-02-20 Tektronix, Inc. High speed double polycide bipolar/CMOS integrated circuit process
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US5270565A (en) * 1989-05-12 1993-12-14 Western Digital Corporation Electro-static discharge protection circuit with bimodal resistance characteristics
US5371395A (en) * 1992-05-06 1994-12-06 Xerox Corporation High voltage input pad protection circuitry
US5426322A (en) * 1992-04-07 1995-06-20 Shiota; Philip Diodes for electrostatic discharge protection and voltage references
US5440162A (en) * 1994-07-26 1995-08-08 Rockwell International Corporation ESD protection for submicron CMOS circuits

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JPH03272180A (ja) * 1990-03-22 1991-12-03 Toshiba Corp 半導体集積回路
US5838033A (en) * 1993-09-08 1998-11-17 Lucent Technologies Inc. Integrated circuit with gate conductor defined resistor

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US4246592A (en) * 1979-01-02 1981-01-20 Texas Instruments Incorporated High density static memory cell
US4691217A (en) * 1984-07-25 1987-09-01 Hitachi, Ltd. Semiconductor integrated circuit device
US4987465A (en) * 1987-01-29 1991-01-22 Advanced Micro Devices, Inc. Electro-static discharge protection device for CMOS integrated circuit inputs
US4902640A (en) * 1987-04-17 1990-02-20 Tektronix, Inc. High speed double polycide bipolar/CMOS integrated circuit process
US5270565A (en) * 1989-05-12 1993-12-14 Western Digital Corporation Electro-static discharge protection circuit with bimodal resistance characteristics
US5426322A (en) * 1992-04-07 1995-06-20 Shiota; Philip Diodes for electrostatic discharge protection and voltage references
US5371395A (en) * 1992-05-06 1994-12-06 Xerox Corporation High voltage input pad protection circuitry
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Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6137664A (en) * 1995-08-16 2000-10-24 Micron Technology, Inc. Well resistor for ESD protection of CMOS circuits
WO1997020348A1 (en) * 1995-11-30 1997-06-05 Micron Technology, Inc. Structure for esd protection in semiconductor chips
US5767552A (en) * 1995-11-30 1998-06-16 Micron Technology, Inc. Structure for ESD protection in semiconductor chips
US6507074B2 (en) 1995-11-30 2003-01-14 Micron Technology, Inc. Structure for ESD protection in semiconductor chips
US6586290B1 (en) 1995-11-30 2003-07-01 Micron Technology, Inc. Structure for ESD protection in semiconductor chips
US5663678A (en) * 1996-02-02 1997-09-02 Vanguard International Semiconductor Corporation ESD protection device
US5808343A (en) * 1996-09-20 1998-09-15 Integrated Device Technology, Inc. Input structure for digital integrated circuits
KR100482362B1 (ko) * 1997-10-14 2005-08-01 삼성전자주식회사 정전기보호용반도체장치및그제조방법
US6635930B1 (en) * 1998-09-25 2003-10-21 Infineon Technologies Ag Protective circuit
EP0994510A3 (en) * 1998-09-25 2003-03-26 Fairchild Semiconductor Corporation LDD structure for electrostatic discharge (ESD) protection device and method of fabrication
US6600210B1 (en) 1999-10-08 2003-07-29 Nec Electronics Corporation Semiconductor device and method of manufacturing the same
EP1091397A3 (en) * 1999-10-08 2002-01-09 Nec Corporation Input/output buffer with silicide layer and method of manufacturing
EP1091397A2 (en) 1999-10-08 2001-04-11 Nec Corporation Input/output buffer with silicide layer and method of manufacturing
US8299531B1 (en) * 2001-12-27 2012-10-30 National Semiconductor Corporation CMOS ESD clamp with input and separate output voltage terminal for ESD protection
US20040119142A1 (en) * 2002-09-30 2004-06-24 Alessandro Grossi Process for manufacturing integrated resistive elements with silicidation protection
US20060141730A1 (en) * 2002-09-30 2006-06-29 Stmicroelectronics S.R.I. Process for manufacturing integrated resistive elements with silicidation protection
US7176553B2 (en) * 2002-09-30 2007-02-13 Stmicroelectronics S.R.L. Integrated resistive elements with silicidation protection
US7566610B2 (en) 2002-09-30 2009-07-28 Alessandro Grossi Process for manufacturing integrated resistive elements with silicidation protection
US20070252231A1 (en) * 2006-04-27 2007-11-01 Shiro Usami Semiconductor integrated circuit and system LSI including the same
US7821096B2 (en) * 2006-04-27 2010-10-26 Panasonic Corporation Semiconductor integrated circuit and system LSI including the same
US20110001218A1 (en) * 2006-04-27 2011-01-06 Panasonic Corporation Semiconductor integrated circuit and system lsi including the same
US8102024B2 (en) * 2006-04-27 2012-01-24 Panasonic Corporation Semiconductor integrated circuit and system LSI including the same

Also Published As

Publication number Publication date
DE59508413D1 (de) 2000-07-06
EP0691683A3 (de) 1996-06-05
JPH0855984A (ja) 1996-02-27
JP2007235151A (ja) 2007-09-13
EP0691683A2 (de) 1996-01-10
EP0691683B1 (de) 2000-05-31
DE4423591A1 (de) 1996-01-11
DE4423591C2 (de) 1996-08-29

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