US5714399A - Semiconductor device having insulation film whose breakdown voltage is improved and its manufacturing method - Google Patents

Semiconductor device having insulation film whose breakdown voltage is improved and its manufacturing method Download PDF

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US5714399A
US5714399A US08/571,674 US57167495A US5714399A US 5714399 A US5714399 A US 5714399A US 57167495 A US57167495 A US 57167495A US 5714399 A US5714399 A US 5714399A
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film
oxide film
forming
silicon oxide
polysilicon layer
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Kiyoshi Hisatomi
Yuuichi Mikata
Sakae Funo
Katsunori Ishihara
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Toshiba Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/416—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H10P32/1414—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering

Definitions

  • the present invention relates to a semiconductor device having an insulation film whose breakdown voltage is improved and its manufacturing method, and more particularly to a gate insulation film of a MOS transistor, a dielectric layer of a capacitor, and an inter-insulation film formed between a floating gate and a control gate in a cell transistor of a nonvolatile memory such as an EPROM, and their suitable manufacturing method.
  • a thermal oxide film which is formed by thermally oxidizing a surface of a silicon substrate, has been used as a gate insulation film of a MOS transistor.
  • BMD Bit Micro Defect
  • insulation breakdown voltage defect of B mode caused by BMD accounts for about 30% of the manufactured device, so that yield of the manufacture is reduced.
  • the breakdown voltage defect of the gate insulation film caused by BMD accounts for 5 to 7% of the defectiveness of the manufacture.
  • MOS transistor having a gate insulation film having an ONO structure in which a bottom oxide film, a silicon nitride film, and a top oxide film are stacked, and a MOS capacitor having a dielectric layer having an ONO structure.
  • EPROM cell of a nonvolatile memory such as an EPROM
  • ONO structure as an inter-insulation film formed between a control gate and a floating gate similar to the gate insulation film of the MOS transistor described in the latter document.
  • the EPROM cell having the inter-insulation film of the ONO structure is formed as follows.
  • a surface of a P type silicon substrate is selectively thermally oxidized so as to form a field oxide film by LOCOS.
  • the surface of the substrate of a device area surrounded with the field oxide film is thermally oxidized so as to form a first thermal oxide film having a thickness of about 200 ⁇ .
  • a first polysilicon layer having a thickness of about 1000 ⁇ is formed on the first thermal oxide film.
  • Phosphorus is doped to the first polysilicon layer by thermal diffusion.
  • the polysilicon is selectively etched. Sequentially, thermal oxidization is performed at temperature of 950° to 1000°C., so that a second thermal oxide film having a thickness of about 60 ⁇ is formed on the surface of the first polysilicon layer.
  • a silicon nitride layer (Si 3 N 4 film) having a thickness of about 150 ⁇ is deposited thereon by low-pressure CVD method, and thermal oxidization is performed again at temperature of about 1000°C., so that a third thermal oxide film having a thickness of about 60 ⁇ is formed on the surface.
  • a second polysilicon layer is deposited on the resultant structure, and phosphorus is doped thereto by thermal diffusion.
  • the second polysilicon layer, the third thermal oxide film, the Si 3 N 4 film, the second thermal oxide film, the first polysilicon layer, and the first thermal oxide film are sequentially etched by photoetching.
  • a control gate a second gate insulation film (SiO 2 film/Si 3 N 4 film/SiO 2 film), a floating gate, and a first gate insulation film are sequentially stacked.
  • the above stacked gate structure is used as a mask, and N type impurities are ion-implanted to the silicon substrate, and thermal treatment is provided thereto, so that an N + drain region and a N + source region formed. Also, an oxide film is formed on an upper surface of the stacked gate structure and a side wall portion, and an exposed surface of the silicon substrate.
  • an inter-level insulation film e.g., PSG film
  • an inter-level insulation film e.g., PSG film
  • Al--Si--Cu film is formed on the entire surface of the inter-level insulation film and patterned. As a result, a drain electrode and a source electrode are formed, and an EPROM cell is formed.
  • the above-mentioned EPROM cell is a device in which a positive high voltage is applied to the N+ drain region and the control gate and electrons are injected to the floating gate, thereby writing is performed.
  • the injected electrons are needed to be stored in the floating gate for a long period of time.
  • the bottom oxide film is formed by oxidizing the surface of the polysilicon layer to which impurities are doped.
  • the formed bottom oxide film becomes weak by influence of dopant (phosphorus) and that of grain of polysilicon.
  • the top oxide film is formed by thermally oxidizing the surface of Si 3 N 4 film.
  • dust is present on the surface of the Si 3 N 4 film, the portion where dust present is first oxidized. Due to this, a pin hole is generated on the top oxide film, and insulation breakdown voltage is reduced.
  • the voltage of the inter-insulation film of the ONO structure is reduced, the electrons stored in the floating gate are absorbed by the control gate through the bottom oxide film, the Si 3 N 4 film, and the top oxide film, so that there is possibility that stored data will be erased.
  • the emission of the electrons stored in the floating gate is a fatal defectiveness in the EPROM cell even if the frequency of the generation is rare.
  • a first object of the present invention is to a semiconductor device having an insulation film whose breakdown voltage is improved and its manufacturing method.
  • a second object of the present invention is to provide a semiconductor device, which can prevent a breakdown voltage of an insulation film from being reduced by influence of a substrate BMD, and its manufacturing method.
  • a third object of the present invention is to provide a semiconductor device, which can prevent a breakdown voltage of an insulation film from being reduced by dopant, influence of grain of polysilicon, and presence of dust, and its manufacturing method.
  • the first and second objects can be achieved by a semiconductor device comprising a silicon substrate having an impurity diffusion layer and a field oxide film; a CVD silicon oxide film, containing Cl, formed on the silicon substrate, Cl of the CVD silicon oxide film having concentration of more than 1 ⁇ 10 18 atoms/cm 3 and less than 2 ⁇ 10 20 atoms/cm 3 ; and a polysilicon layer formed on the CVD silicon oxide film.
  • the CVD silicon oxide film containing Cl having concentration of more than 1 ⁇ 10 18 atoms/cm 3 and less than 2 ⁇ 10 20 atoms/cm 3 , is formed on the silicon substrate. Due to this, the insulation breakdown voltage of the silicon oxide film can be prevented from being reduced by BMD, and the breakdown voltage can be improved as compared with the case in which a thermal oxide film is formed on the silicon substrate.
  • the first and third objects can be achieved by a semiconductor device comprising a patterned polysilicon layer; a first CVD silicon oxide film, containing Cl, formed on the polysilicon substrate, Cl of the first CVD silicon oxide film having concentration of more than 1 ⁇ 10 18 atoms/cm 3 and less than 2 ⁇ 10 20 atoms/cm 3 ; an SiN film formed on the first CVD silicon oxide film; and a second CVD silicon oxide film, containing Cl, formed on the SiN film, Cl of the second CVD silicon oxide film having concentration of more than 1 ⁇ 10 18 atoms/cm 3 and less than 2 ⁇ 10 20 atoms/cm 3 .
  • the first CVD silicon oxide film containing Cl having concentration of more than 1 ⁇ 10 18 atoms/cm 3 and less than 2 ⁇ 10 20 atoms/cm 3 , is formed on the polysilicon substrate. Due to this, the reduction of the insulation breakdown voltage of the first CVD silicon oxide film can be prevented without being influenced by dopant to the polysilicon layer or grain of polysilicon. Also, the first CVD silicon oxide film, containing Cl having concentration of more than 1 ⁇ 10 18 atoms/cm 3 and less than 2 ⁇ 10 20 atoms/cm 3 , is formed on the SiN film. Due to this, even if dust is present on the SiN film, the generation of a pin hole can be prevented. Thereby, the insulation breakdown voltage of the second CVD silicon oxide film can be prevented from being reduced. Therefore, the breakdown voltage of ONO film can be improved.
  • the above first and second objects can be achieved by a method for manufacturing a semiconductor device comprising the steps of forming a field oxide film on a silicon substrate; forming a silicon oxide film, containing Cl having concentration of more than 1 ⁇ 10 18 atoms/cm 3 and less than 2 ⁇ 10 20 atoms/cm 3 , on the silicon substrate by CVD; and forming a polysilicon layer formed on the silicon oxide film.
  • the silicon oxide film containing Cl having concentration of more than 1 ⁇ 10 18 atoms/cm 3 and less than 2 ⁇ 10 20 atoms/cm 3 , on the silicon substrate by CVD. Due to this, BMD is not introduced to the silicon oxide film, and the insulation breakdown voltage of the silicon oxide film can be prevented from being reduced by BMD, and the breakdown voltage can be improved as compared with the case in which the silicon oxide film is formed by thermally oxidizing the silicon substrate.
  • the above first and third object can be achieved by a method for manufacturing a semiconductor device comprising the steps of patterning a first polysilicon layer; forming a first silicon oxide film, containing Cl having concentration of more than 1 ⁇ 10 18 atoms/cm 3 and less than 2 ⁇ 10 20 atoms/cm 3 , on the patterned first polysilicon layer by CVD; forming an SiN film on the first silicon oxide film; and forming a second silicon oxide film, containing Cl having concentration of more than 1 ⁇ 10 18 atoms/cm 3 and less than 2 ⁇ 10 20 atoms/cm 3 , on the SiN film by CVD.
  • the first silicon oxide film containing Cl having concentration of more than 1 ⁇ 10 18 atoms/cm 3 and less than 2 ⁇ 10 20 atoms/cm 3 , on the polysilicon layer by CVD. Due to this, the reduction of the insulation breakdown voltage of the first silicon oxide film can be prevented without being influenced by dopant to the polysilicon layer or grain of polysilicon.
  • the second silicon oxide film containing Cl having concentration of more than 1 ⁇ 10 18 atoms/cm 3 and less than 2 ⁇ 10 20 atoms/cm 3 , is formed on the SiN film by CVD. Due to this, even if dust is present on the surface of the SiN film, dust can be covered with the second silicon oxide film, and the insulation breakdown voltage of the second silicon oxide film can be prevented from being reduced. Therefore, the breakdown voltage of ONO film can be improved.
  • FIG. 1 is a cross sectional view of a MOS transistor to explain a semiconductor device and its manufacturing method in accordance with a first embodiment of the present invention
  • FIG. 2 is a cross sectional view of a capacitor to explain a semiconductor device and its manufacturing device in accordance with a second embodiment of the present invention
  • FIG. 3 is a characteristic view showing a comparison between the capacitor formed by the manufacturing method of the present invention and the capacitor manufactured by the conventional manufacturing method in I-V characteristic;
  • FIG. 4 is a characteristic view showing a result of the measurement of TDDB characteristic by use of the capacitor formed by the manufacturing method of the present invention
  • FIGS. 5A and 5B are cross sectional views of an EPROM cell to explain a semiconductor device and its manufacturing device in accordance with a third embodiment of the present invention.
  • FIGS. 6A to 6C are graphs each showing a result of analysis performed to find out an optimum value of Cl contained in a CVD silicon oxide film in each of the above embodiments.
  • FIG. 1 is a cross sectional view of a MOS transistor to explain a semiconductor device in accordance with a first embodiment of the present invention.
  • an impurity diffusion layer serving as a drain region 12, and an impurity diffusion layer, serving as source region 13, are formed to be separated from each other.
  • a gate insulation film 20 is formed on the substrate 11 between the drain and source regions 12 and 13.
  • a gate electrode 15 is formed on the gate insulation film 20.
  • An inter-level insulation film 16 is formed on the resultant structure, and contact holes 16a and 16b are formed on the drain and source regions 12 and 13 of the inter-level insulation film 16, respectively.
  • a drain electrode 17 is formed on the inter-level insulation film 16, and connected to the drain region 12 through the contact hole 16a.
  • a source electrode 18 is formed on the inter-level insulation film 16, and connected to the source region 13 through the contact hole 16b.
  • the gate insulation film 20 is formed of a CVD silicon oxide film containing Cl whose concentration is more than 1 ⁇ 10 18 atoms/cm 3 and less than 2 ⁇ 10 20 atoms/cm 3 .
  • the field oxide film is formed on the surface of the silicon substrate 11 by LOCOS (not shown).
  • silicon chloride compound (SiCl 4 , SiHCl 3 , SiH 2 Cl 2 ) gas is reacted with combustion supporting gas (N 2 O), so that the CVD silicon oxide film 20 is deposited on the surface exposed on the element region of the substrate 11 under a low-pressure condition that reaction temperature is 750° to 950° C. and reaction pressure is 0.2 to 1.0 Torr.
  • a polysilicon layer is deposited on the CVD silicon oxide film 20, impurities are doped thereto, and the resultant structure is patterned to form a gate electrode 15. Then, the field oxide film and the gate electrode 15 are used as a mask, and impurities are implanted to the substrate 11. Then, impurity diffusion layers, serving as the drain region 12 and the source region 13, are formed by thermal treatment.
  • the inter-level insulation film (e.g., PSG film) 16 is deposited on the resultant structure, selectively etched, and contact holes 16a and 16b are formed on the drain region 12 and the source region 13, respectively.
  • Al or an Al alloy film is vapor-deposited on the entire surface of the inter-level film 16, patterned to form a drain electrode 17 and a source electrode 18, so that the MOS transistor shown in FIG. 1 is formed.
  • the gate insulation film is formed by CVD
  • BMD Bit Micro Defect
  • insulation breakdown voltage defect of the gate insulation film caused by BMD accounts for 5 to 7% of the defectiveness of the manufacture.
  • the defect caused by BMD can be reduced to substantially 0%, and products having high reliability can be manufactured with high yield.
  • the oxide film 20 is nitrided with NH 3 at temperature of 850° to 1000°C., so that an SiON film, serving as gate insulation film 20, may be formed. Then, the polysilicon layer is deposited on the SiON film, impurities are doped to the resultant structure, and patterned to form the gate electrode 15. Regarding the following steps, similar to the above-mentioned steps, the drain, source regions 12 and 13, the inter-level insulation film 16, and the drain and source electrodes 17 and 18 are sequentially formed.
  • the CVD silicon oxide film 20 is nitrided so as to form the SiON film, so that the breakdown voltage of the gate insulation film can be further improved (Q BD is increased).
  • FIG. 2 is a cross sectional view of a capacitor to explain a semiconductor device of the present invention.
  • FIG. 2 shows the capacitor comprising an insulation film 34 is formed on the silicon substrate 33, and a dielectric film 36 having an ONO structure on the insulation film 34.
  • the dielectric film 36 is formed on a first polysilicon layer 35, serving as one of electrodes of the capacitor.
  • the dielectric film 36 is formed by layering a first CVD silicon oxide film 36-1 containing Cl whose concentration is more than 1 ⁇ 10 18 atoms/cm 3 and less than 2 ⁇ 10 20 atoms/cm 3 , an SiN film 36-2, and a second CVD silicon oxide film 36-3 containing Cl whose concentration is more than 1 ⁇ 10 18 atoms/cm 3 and less than 2 ⁇ 10 20 atoms/cm 3 .
  • a second polysilicon layer 37 serving as the other electrode of the capacitor, is formed on the dielectric film 36.
  • the insulation film 34 (thermal oxide film) having a thickness of about 500 ⁇ is formed on the surface of the silicon substrate 33.
  • silane gas is thermally decomposed at reaction temperature of 600° C. by low-pressure CVD, so as to form the first polysilicon layer 35 having a thickness of about 1000 ⁇ .
  • phosphorus is doped to the polysilicon layer 35 to reduce the resistance value.
  • dichloro silane gas gas flow: 90 sccm
  • N 2 O gas gas flow: 180 sccm
  • Each of the above-formed silicon oxide film 36-1, the silicon nitride film 36-2, and the silicon oxide film 36-3 forms the dielectric layer 36 of the capacitor.
  • the second polysilicon layer 37 is deposited on the dielectric layer 36 similar to the first polysilicon layer 35, and phosphorus is thermally diffused to reduce the resistance value. Then, the polysilicon layer 37, the silicon oxide film 36-3, the silicon nitride film 36-2, the silicon oxide film 36-1, and the polysilicon layer 35 (oxide film 35 as necessary) are sequentially etched and patterned by photoetching, thereby forming the capacitor of FIG. 2.
  • the capacitor was formed on the insulation film 34 after the insulation film 34 was formed on the silicon substrate 33.
  • the impurity diffusion layer for forming various kinds of semiconductor elements is formed in the substrate 33.
  • the impurity diffusion layer and interconnection are formed. Thereby, it is possible to form the capacitor and the other semiconductor elements in the substrate 33. Also, it is of course that other semiconductor elements can be formed by use of the part or all of the capacitor manufacturing process.
  • the silicon oxide film 36-1 containing Cl whose concentration is more than 1 ⁇ 10 18 atoms/cm 3 and less than 2 ⁇ 10 20 atoms/cm 3 is formed on the polysilicon layer 35 by CVD, the silicon oxide film 36-1 is not influenced by dopant (phosphorus) of the polysilicon layer 35 or the grain of polysilicon, and the reduction of the insulation breakdown voltage of the silicon oxide film 36-1 can be prevented. Also, the since the silicon oxide film 36-3 containing Cl whose concentration is more than 1 ⁇ 10 18 atoms/cm 3 and less than 2 ⁇ 10 20 atoms/cm 3 is formed on the silicon nitride film 36-2 by CVD.
  • the silicon oxide film 36-1, the silicon nitride film 36-2, and the silicon oxide film 36-3 are formed at the same reaction temperature in the continuous steps. Also, dichloro silane gas continuously flows during the steps, and N 2 O gas and NH 3 gas flow simultaneously for the fixed period time. Thereby, a SiO x N y film is formed on the interface between the silicon oxide film 36-1 and the silicon nitride film 36-2, and the interface between the silicon nitride film 36-2 and the silicon oxide film 36-3, respectively. Moreover, the number of traps of impurity atoms can be reduced. As a result, the number of portions where concentration of an electric field occurs is largely reduced, so that leak current is decreased and the insulation breakdown voltage can be improved.
  • FIG. 3 shows the comparison between the capacitor formed by the above-mentioned manufacturing method and the capacitor formed by the conventional manufacturing method in connection with the I-V characteristic.
  • a vertical line shows a current value flowed between the polysilicon layer 35 and the polysilicon layer 37
  • a horizontal line shows an electric filed due to the voltage applied to the polysilicon 37.
  • the leak current of the dielectric film 36 can be reduced by the manufacturing method of the present invention as compared with the conventional method.
  • FIG. 4 shows the result in which TDDB characteristic is measured by the above-mentioned capacitor.
  • time which is needed to reach to the same defective rate as the conventional case, is increased about double.
  • the silicon oxide film 36-1 is nitrided with NH 3 at temperature of 850° to 1000° C., so that the SiON film is formed.
  • the silicon oxide film 36-1 is nitrided with NH 3 at temperature of 850° to 1000 ° C., so that the SiON film may be formed.
  • dichloro silane gas gas flow: 90 sccm
  • N 2 O gas gas flow: 180 sccm
  • dichloro silane gas gas flow: 90 sccm
  • H 2 O gas gas flow: 180 sccm
  • NH 3 gas is introduced to the reactive tube to nitride the silicon oxide film 36-3, so that the top oxide film formed of SiON is formed.
  • the SiON films are formed as the bottom oxide film 36-1 and the top oxide film 36-3, the dielectric constant can be increased, and the film thinning can be improved. Moreover, since the SiON film is not easily oxidized, the bird's beak formed on the interface between the first polysilicon layer 35 and the bottom oxide film 36-1 and the interface between the top oxide film 36-3 and the second polysilicon layer 37 can be reduced.
  • FIG. 5A explains a semiconductor device of a third embodiment of the present invention, and shows a cell transistor (EPROM cell) in a nonvolatile memory such as an EPROM.
  • EPROM cell the ONO structure as explained as the inter-insulation film is used, and the structure between the control gate and the floating gate is the same as the capacitor shown in FIG. 2.
  • An N + type impurity diffusion layer, serving as a drain region 22, and an N + type impurity diffusion layer, serving as a source region 23, are formed in a main surface area of a P - type silicon substrate 21 to be separated from each other.
  • a first gate insulation film (first thermal oxide film) 24, a floating gate 25, a second gate insulation film (inter-insulation film) 38 having an ONO structure, and a control gate 27 are stacked on the substrate 21 between the drain and source regions 22 and 23.
  • the second gate insulation film 38 is formed by layering a first CVD silicon oxide film (bottom oxide film) 38-1 containing Cl whose concentration is more than 1 ⁇ 10 18 atoms/cm 3 and less than 2 ⁇ 10 20 atoms/cm 3 , a silicon nitride film 38-2, and a second CVD silicon oxide film (top oxide film) 38-3 containing Cl whose concentration is more than 1 ⁇ 10 18 atoms/cm 3 and less than 2 ⁇ 10 20 atoms/cm 3 .
  • an oxide film 28 is formed on the upper surface of the above stacked gate structure, the side wall, and the main surface of the substrate 21.
  • An inter-level insulation film (PSG film) 29 is formed on the resultant structure, and contact holes 29a and 29b are formed on the drain and source regions 22 and 23, respectively.
  • a drain electrode 30 is formed on the inter-level insulation film 29 to be connected to the drain region 22 through the contact hole 29a.
  • a source electrode 31 is formed on the inter-level insulation film 29 to be connected to the source region 23 through the contact hole 29b.
  • a surface of a P-type silicon substrate 21 is selectively oxidized by LOCOS to form a field oxide film 32.
  • the surface of the element region, which is surrounded with the field oxide film 32 in the silicon substrate 21, is thermally oxidized to form a first thermal oxide film 24' having a thickness of about 200 ⁇ .
  • a first polysilicon layer 25' having a thickness of about 1000 ⁇ is formed on the thermal oxide film 24' by CVD.
  • a region (not shown) of the polysilicon layer 25' is selectively etched.
  • dichloro silane gas gas flow: 90 sccm
  • N 2 O gas gas flow: 180 sccm
  • dichloro silane gas gas flow: 70 sccm
  • HN 3 gas gas flow: 700 sccm
  • the above-mentioned step of forming the silicon oxide film 38-1' is repeated at the same reaction temperature by the same device, thereby forming a silicon oxide film 38-3' having a thickness of about 60 ⁇ .
  • each of the above-formed silicon oxide film 38-1', the silicon nitride film 38-2', and the silicon oxide film 38-3' forms an inter-insulation film 38.
  • dichloro silane continuously introduced into the reaction tube in order not to form an interface between the silicon oxide film 38-1' and the silicon nitride film 38-2', and between the silicon nitride film 38-2', and the silicon oxide film 38-3', dichloro silane continuously introduced into the reaction tube, and NH 3 gas is set to flow to the reaction tube two minutes before the flow of N 2 O is ended at the time of changing N 2 O gas to NH 3 gas. Thereafter, the second polysilicon layer 27' is deposited on the the resultant structure, and phosphorus is doped thereto by thermal diffusion.
  • the second polysilicon layer 27', the silicon oxide film 38-3', the Si 3 N 4 film 38-2', the silicon thermal oxide film 38-1', the first polysilicon layer 25', and the thermal oxide film 24' are sequentially etched by photoetching.
  • the control gate 27, the second gate insulation film 38 (SiO 2 film 38-1/Si 3 N 4 film/SiO 2 film 38-3), the floating gate 25, and the first gate insulation film 24 are formed.
  • the above layer gate structure is used as a mask, and N type impurity material is ion-implanted to the silicon substrate 21. Then, thermal treatment is provided thereto, the N + drain region 22 and N + source region 23 are formed, and the oxide film 28 is formed on the upper surface of the stacked gate structure, and the side wall section, and the exposed surface of the substrate 21.
  • the inter-level insulation film e.g., PSG film
  • the inter-level insulation film is formed on the resultant structure, and selectively etched to form contact holes 29a and 29b on the drain region 22 and the source region 23.
  • Al--Si--Cu film is deposited on the entire surface of the inter-level insulation film 29, and patterned to form the drain electrode 30 and the source electrode 31.
  • the EPROM cell as shown in FIG. 5A is formed.
  • impurity diffusion layer for forming various semiconductor elements may be formed in the substrate 21 prior to the the manufacturing process of the cell transistor.
  • the impurity diffusion layer or interconnection are formed, thereby the cell transistor and the other semiconductor elements are formed in the substrate 21.
  • the insulation film of the other semiconductor element or the electrode, the interconnection, and the active region may be formed by use of a part of the manufacturing process of the cell transistor.
  • the silicon oxide film 38-1 containing Cl whose concentration is more than 1 ⁇ 10 18 atoms/cm 3 and less than 2 ⁇ 10 20 atoms/cm 3 is formed on the floating gate 25 by CVD, the silicon oxide film 38-1 is not influenced by dopant (phosphorus) of the floating gate 25 or the grain of polysilicon, and the reduction of the insulation breakdown voltage of the silicon oxide film 38-1 can be prevented. Also, the silicon oxide film 38-3 containing Cl whose concentration is more than 1 ⁇ 10 18 atoms/cm 3 and less than 2 ⁇ 10 20 atoms/cm 3 is formed on the silicon nitride film 38-2 by CVD.
  • the silicon oxide film 38-1, the silicon nitride film 38-2, and the silicon oxide film 38-3 are formed at the same reaction temperature in the continuous steps. Also, dichloro silane gas continuously flows during the continuous steps, and N 2 O gas and ammonia gas flow simultaneously for the fixed period time.
  • a SiO x N y film is formed on the interface between the silicon oxide film 38-1 and the silicon nitride film 38-2, and the interface between the silicon nitride film 38-2 and the silicon oxide film 38-3, respectively.
  • the number of traps of impurity atoms can be reduced.
  • the number of portions where concentration of an electric field occurs is largely reduced, so that leak current is decreased and the insulation breakdown voltage can be improved. Therefore, there is no possibility that the electrons stored in the floating gate of the EPROM cell will be emitted to the control gate 27, and the electron maintaining characteristic can be improved and reliability can be increased.
  • the silicon oxide films 38-1 and 38-3 may be nitrided to from SiON films, respectively.
  • dichloro silane gas gas flow: 90 sccm
  • N 2 O gas gas flow: 180 sccm
  • reaction temperature is 780° C.
  • pressure is 0.1 Torr by low-pressure CVD
  • NH 3 gas is introduced to the reactive tube of CVD device to nitride the silicon oxide film 38-1', so that the bottom oxide film formed of SiON is formed.
  • dichloro silane gas gas flow: 70 sccm
  • HN 3 gas gas flow: 700 sccm
  • dichloro silane gas gas flow: 90 sccm
  • H 2 O gas gas flow: 180 sccm
  • NH 3 gas is introduced to the reactive tube to nitride the silicon oxide film 38-3', so that the top oxide film formed of SiON is formed.
  • the dielectric constant can be increased, and the film thinning can be improved.
  • the bird's beak formed on the interface between the first polysilicon layer 25 and the bottom oxide film 38-1 and the interface between the top oxide film 38-3 and the second polysilicon layer 27 can be reduced.
  • FIGS. 6A to 6C are graphs each showing a result of analysis performed to find out an optimum value of Cl contained in a CVD silicon oxide film in each of the above embodiments.
  • FIG. 6A shows a case in which concentration of Cl is 1 ⁇ 10 18 atoms/cm 3 or less. In the case of using the above concentration, insulation breakdown defectiveness is generated in mode B, and it can be understood that a sufficient effect cannot be obtained when concentration of Cl is 1 ⁇ 10 18 atoms/cm 3 or less.
  • FIG. 6B shows a case in which concentration of Cl is 1 ⁇ 10 19 atoms/cm 3 . In this case, the mode, which is the defectiveness is generated, is only mode C, and the insulation breakdown defectiveness can be surely prevented.
  • FIG. 6A shows a case in which concentration of Cl is 1 ⁇ 10 18 atoms/cm 3 or less. In the case of using the above concentration, insulation breakdown defectiveness is generated in mode B, and it can be understood that a sufficient effect cannot be obtained when concentration of Cl is 1
  • concentration of Cl of the CVD silicon oxide film is 1 ⁇ 10 18 atoms/cm 3 or more and 2 ⁇ 10 20 atoms/cm 3 or less, preferably 1 ⁇ 10 20 atoms/cm 3 or less.
  • the conventional product yield of the nonvolatile memory using the thermal oxide film as an inter-insulation film was about 30%.
  • the product yield of 60% can be obtained, and the product yield can be largely improved.
  • the above second and third embodiments explained the case in which dichloro silane gas is used to form the silicon oxide films 36-1, 38-1, the silicon nitride films 36-2, 38-2, and the silicon oxide films 36-3, and 38-3. However, even if monosilane gas or disilane gas is used, the same effect can be obtained. Moreover, the second and third embodiments explained the case in which favorable reaction temperature is set to 0.1 Torr and 0.5 Torr. However, if the reaction temperature ranges 0.1 to 1.0 Torr, there is no problem in forming the films. Moreover, the second and third embodiments explained the case in which the insulation film (dielectric film) has the ONO structure. However, similar to the first embodiment, this can be applied to one-layer insulation film or one-layer dielectric film is formed.
  • the MOS transistor, the MOS capacitor, and the EPROM transistor are used as the semiconductor device.
  • the present invention can be applied to the other semiconductor device in which the silicon oxide film is formed on the silicon substrate, the polysilicon layer, and the silicon nitride film and the electric field is applied to the silicon oxide film, and its manufacturing method.

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US20080073702A1 (en) * 1997-06-11 2008-03-27 Boaz Eitan NROM fabrication method
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US20080135911A1 (en) * 1997-06-11 2008-06-12 Boaz Eitan Nrom fabrication method
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US8008709B2 (en) 1997-06-11 2011-08-30 Spansion Israel Ltd NROM fabrication method
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US20080230831A1 (en) * 2007-03-23 2008-09-25 Kosei Noda Semiconductor device and manufacturing method thereof
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