US5907190A - Semiconductor device having a cured silicone coating with non uniformly dispersed filler - Google Patents

Semiconductor device having a cured silicone coating with non uniformly dispersed filler Download PDF

Info

Publication number
US5907190A
US5907190A US08/561,472 US56147295A US5907190A US 5907190 A US5907190 A US 5907190A US 56147295 A US56147295 A US 56147295A US 5907190 A US5907190 A US 5907190A
Authority
US
United States
Prior art keywords
filler
semiconductor device
semiconductor
powders
cured silicone
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US08/561,472
Other languages
English (en)
Inventor
Takae Ishikawa
Katsutoshi Mine
Hiroyosi Naito
Kimio Yamakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
DuPont Toray Specialty Materials KK
Original Assignee
Dow Corning Toray Silicone Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP6314185A external-priority patent/JPH08148612A/ja
Priority claimed from JP33903594A external-priority patent/JP3443196B2/ja
Application filed by Dow Corning Toray Silicone Co Ltd filed Critical Dow Corning Toray Silicone Co Ltd
Assigned to DOW CORNING TORAY SILICONE COMPANY, LTD. reassignment DOW CORNING TORAY SILICONE COMPANY, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ISHIKAWA, TAKAE, MINE, KATSUTOSHI, NAITO, HIROYOSI, YAMAKAWA, KIMIO
Priority to US09/237,610 priority Critical patent/US5989942A/en
Application granted granted Critical
Publication of US5907190A publication Critical patent/US5907190A/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/40—Fillings or auxiliary members in containers, e.g. centering rings
    • H10W76/42—Fillings
    • H10W76/47—Solid or gel fillings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
    • H10W74/473—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins containing a filler
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • This invention relates to semiconductor devices and methods for their fabrication. More particularly, this invention relates to semiconductor devices having cured silicone covering the surface of the semiconductor elements. These coatings can be designed to resist swelling when cleaned by solvents such that the semiconductor elements and bonding wires of these devices are neither ruptured nor deformed by such cleaning. The coatings can also be designed to resist failure and faulty operation due to static electricity. This invention also relates to a method for fabricating these semiconductor devices.
  • the surface of semiconductor elements are typically coated with cured silicone to protect them from moisture and external stresses. This is true for both face-up semiconductor devices, in which the semiconductor element and lead frame are electrically connected through bonding wires, and for face-down semiconductor devices, in which the semiconductor element is electrically connected to the lead frame through solder bumps.
  • the art suggests using (a) semiconductor devices in which the surface of the semiconductor element is coated with cured silicone and the element is then additionally sealed in a ceramic or plastic package and (b) semiconductor devices in which the surface of the element is covered with cured silicone containing a high loading of dispersed filler.
  • the former solution results in increased costs and a reduced efficiency in mass production.
  • the latter solution is disadvantageous in that heat cycling causes problems such as damage to the surface of the semiconductor element by the filler and deformation or rupture of the semiconductor element or bonding wires.
  • the present invention takes as its object the introduction of a semiconductor device whose semiconductor element is coated with a cured silicone which resists swelling when cleaned with a solvent.
  • the semiconductor element and bonding wires are, therefore, neither ruptured nor deformed by solvent cleaning.
  • An additional object of the present invention is the introduction of a semiconductor device whose semiconductor element is resistant to the failure and faulty operation which can be caused by static electricity.
  • a final object of the present invention is the introduction of a method for fabricating semiconductor devices having these types of reliability.
  • the present invention relates to a semiconductor device.
  • the device comprises a semiconductor substrate having a semiconductor element mounted thereon.
  • a coating comprising a cured silicone in which there is dispersed a filler having an average particle diameter of 0.01 to 500 micrometers and a specific gravity of 0.01 to 0.95 covers the semiconductor element.
  • the concentration of filler in the cured silicone is higher in the part of the coating remote from the element than in the part of the coating adjoining the element.
  • the invention also relates to a method for fabricating a semiconductor device.
  • the method comprises coating the surface of a semiconductor element with a curable silicone composition comprising a curable silicone polymer and a filler having an average particle diameter of 0.01 to 500 micrometers and a specific gravity of 0.01 to 0.95.
  • a sufficient time is then allowed to elapse for the filler in the part of the curable silicone composition adjoining the element to migrate into the part of the curable silicone composition remote from the element.
  • the curable silicone composition is then cured.
  • FIG. 1 contains the cross section of a semiconductor device according to the present invention as fabricated in Examples 1 and 3.
  • FIG. 2 contains the cross section of a semiconductor device according to the present invention as fabricated in Example 2 and 5.
  • FIG. 3 contains the cross section of a face-down semiconductor device according to the present invention.
  • the present invention is based on the unexpected discovery that the silicone coatings of the present invention on semiconductor devices mounted on circuit substrates can be designed to inhibit swelling when cleaned with a solvent and can be designed to inhibit damage due to static electricity. This inhibits damage to the device itself and also prevents deformation and breakage of its bonding wires.
  • the reason for this improvement is their higher concentration of filler in that part of the coating remote from the element as compared to that part of the coating adjoining the element.
  • the structure of the semiconductor device of the present invention is not critical. Generally, however, the device contains a semiconductor element such as, for example, a transistor, IC, LSI, and so forth, mounted in the semiconductor device. These semiconductor devices are exemplified by face-up semiconductor devices such as those of FIGS. 1 and 2 and face-down semiconductor devices such as those of FIG. 3.
  • This device has a structure in which a semiconductor element 2 mounted on substrate 1 is electrically connected to the lead frame 5 through bonding wires 4.
  • the surface of said element 2 is coated with, a cured silicone 7 in which filler 8 is dispersed.
  • the specific cured silicone 7 is not crucial, and it may be, for example, a gel or rubber.
  • This cured silicone is formed-by curing a curable silicone composition comprising a curable silicone polymer.
  • the curing mechanism of the curable silicone is exemplified by addition reaction-curing, condensation reaction-curing, radical reaction-curing, and ultraviolet-curing mechanisms.
  • the addition reaction-curing mechanism is preferred.
  • the filler 8 is to have an average particle diameter of 0.01 to 500 micrometers and preferably 0.1 to 100 micrometers.
  • the specific gravity of the filler should be 0.01 to 0.95.
  • the filler's specific gravity is preferably 0.01 to 0.95-times and more preferably 0.1 to 0.9-times that of the non-filler components of the curable silicone composition that generates the cured silicone.
  • the characteristic feature of the semiconductor device according to the present invention is that the concentration of filler 8 present in the layer of cured silicone 7 remote from the semiconductor element 2 is higher than the concentration of said filler 8 present in the layer of cured material 7 adjoining the semiconductor element 2. No limitations otherwise apply to either the concentration of filler 8 in the layer of cured silicone 7 remote from the semiconductor element 2 or to the concentration of the filler 8 in the layer of cured material 7 adjoining the element 2.
  • the variation in filler concentration in the silicone may be continuous or discontinuous as one moves from the layer of cured material 7 adjoining the element 2 to the layer of cured material 7 remote from the element 2.
  • the higher concentration of the filler 8 dispersed in the layer of cured silicone 7 remote from the semiconductor device 2 functions to inhibit swelling of the cured silicone 7 when the semiconductor device is subjected to solvent cleaning after mounting on a circuit substrate.
  • the lower concentration of the filler 8 dispersed in the layer of cured material 7 adjoining the element 2 inhibits damage to the surface of the element 2 by the filler 8 dispersed in this layer of the cured material 7 when the device is thermally cycled. Further, the lower concentration inhibits deformation or destruction of the element 2 and deformation or snapping of the bonding wires 5.
  • the higher concentration of the filler 8 dispersed in the layer of cured silicone 7 remote from the semiconductor device 2 functions to prevent the generation of static charge and to dissipate static charge after the semiconductor device has been mounted on a circuit substrate.
  • the lower concentration of the filler 8 dispersed in the layer of cured material 7 adjoining the element 2 prevents electrical short circuiting of the element and inhibits damage to the surface of the element 2 by the filler 8 dispersed in this layer of the cured material 7 when the device is thermally cycled. Further, the lower concentration inhibits deformation or destruction of the element 2 and deformation or snapping of the bonding wires 5.
  • the semiconductor device according to the present invention there is a high concentration of filler 8 in the layer of cured silicone 7 remote from the semiconductor element 2 and the filler 8 is almost completely absent from the layer of the cured material 7 adjoining the element 2.
  • the material constituting the filler 8 is not critical and is exemplified by the powders of organic resins such as nylon resins, polyethylene resins, polypropylene resins, polystyrene resins, acrylic resins, fluororesins, epoxy resins, phenolic resins, polyethylene terephthalate resins, and so forth; by the hollow forms of these organic resin powders; and by hollow inorganic powders such as hollow glass powders, hollow silica powders, hollow alumina powders, hollow ceramic powders, and the like.
  • This filler 8 is preferably a heat-distortable or thermally deformable organic resin powder.
  • a heat-distortable organic resin powder is preferably accompanied by the use of an addition reaction-curing curable silicone composition as the curable silicone composition.
  • curing of the composition at temperatures at or above the heat-distortion temperature of the organic resin powder will cause heat distortion and melt-adhesion of at least a portion of the organic resin powder 8 in the layer of the cured silicone 7 remote from the semiconductor element 2. This will make this layer relatively harder as a result.
  • the material constituting the filler is not crucial as long as the filler is either intrinsically electrically conductive or has a surface that is electrically conductive.
  • the electrically conductive filler is exemplified by powders coated with an electrically conductive material and hollow powders of copper, aluminum, silver, zinc, carbon, and so forth. Examples of coated powders include organic resin powders, hollow organic resin powders, and hollow inorganic powders, in each case having a surface coating of an electrically conductive material such as copper, aluminum, silver, zinc, carbon, etc.
  • the organic resins constituting said organic resin powders and hollow organic resin powders are exemplified by nylon, polyethylene, polypropylene, polystyrene, acrylic resins, fluororesins, epoxy resins, phenolic resins, polyethylene terephthalate, and so forth.
  • the inorganic hollow powders are exemplified by hollow glass powders, hollow silica powders, hollow alumina powders, hollow ceramic powders, and so forth.
  • the electrically conductive filler is also exemplified by the hollow powders of copper, aluminum, silver, zinc, carbon, and so forth.
  • the surface of the cured silicone is preferably grounded in the case of relatively large semiconductor devices.
  • Methods for this are exemplified by grounding the surface of the cured silicone using a conductive trace or lead and by the formation of a dam with a volume resistivity from 1 ⁇ 106 to 1 ⁇ 10 11 ohm-cm around the circumference of the substrate-mounted semiconductor element. The latter method is preferred.
  • This grounding inhibits the accumulation of static electricity on the cured silicone 7 that coats the surface of the semiconductor element 2 and also serves to rapidly dissipate any charge that may accumulate.
  • the quantity of filler addition is not crucial, and the appropriate addition should be selected, for example, based on the average particle diameter and specific gravity of the filler, the application of the obtained semiconductor device, and so forth.
  • the range of 0.1 to 80 wt % in the composition is generally preferred.
  • the cured silicone coating the surface of the semiconductor element resists swelling when the device is cleaned with solvent. This avoids deformation or destruction of the element and deformation or breakage of the bonding wires. As a result, the element need not be sealed in a ceramic or plastic package as with prior-art semiconductor devices. This permits a substantial simplification in the structure of subject semiconductor device.
  • semiconductor devices used in static-prone locations such as image sensors, thermal print heads, etc.
  • resist failure and faulty operation that can be induced by static electricity.
  • the cured silicone that coats the surface of the semiconductor element is resistant to the accumulation of static electricity.
  • the semiconductor devices according to the present invention do not require coating with metal or plastic as is practiced with prior-art semiconductor devices, the structure of the instant device can be substantially simplified and its cost can be reduced.
  • the fabrication method according to the present invention commences with coating the above-described curable silicone composition on the surface of a semiconductor element. This is typically done using a dispenser.
  • the composition is then allowed to stand for a period of time long enough for the filler in the layer of the curable silicone composition adjoining the semiconductor element to migrate into the layer of the composition that is remote from the element.
  • This holding period is followed by curing.
  • the length of this holding period cannot be rigorously specified because it will vary as a function of the difference in specific gravities between the filler and non-filler fraction of the curable silicone composition, the viscosity of the curable silicone composition, the average particle diameter of the filler, the quantity of filler addition, and so forth.
  • the holding period requirement will be satisfied even immediately after the composition has been coated on the surface of the semiconductor element.
  • the use of very long holding times will permit the formation of a discontinuous dispersion of the filler in the cured silicone layers, in which there will be almost no filler dispersed in the cured silicone layer adjoining the semiconductor element and the filler will be dispersed only in the cured material remote from the element.
  • the use of brief but still adequate holding times permits the formation of silicone layers in which the concentration of the filler continuously increases moving from the layer of cured material adjoining the element to the layer of cured material remote from the element.
  • the filler be a heat-distortable or -deformable organic resin powder, and the use of such a filler is preferably accompanied by the use of an addition reaction-curing curable silicone composition as the curable silicone composition.
  • an addition reaction-curing curable silicone composition filled with a heat-distortable organic resin powder is coated on the surface of the semiconductor element and then heated to at least the heat-distortion temperature of the powder, at least a portion of the powder in the cured silicone layer remote from the semiconductor element will be thermally distorted and melt-adhered. This results in a relatively hard layer.
  • the surface of the cured silicone is preferably grounded in the case of relatively large semiconductor devices.
  • Methods for this are exemplified by grounding the surface of the cured silicone using a conductive trace or lead and by the preliminary formation of a dam with a volume resistivity from 1 ⁇ 10 6 to 1 ⁇ 10 11 ohm-cm at the circumference of the substrate-mounted semiconductor element. The latter method is preferred.
  • the surface of the semiconductor element mounted within the dam is preferably coated with the curable silicone composition containing the electrically conductive filler. This grounding inhibits the accumulation of static electricity on the cured silicone that coats the surface of the semiconductor element and also serves to rapidly dissipate any charge that may accumulate.
  • the method according to the present invention makes it unnecessary to additionally seal the semiconductor element with a metal, ceramic or plastic package or coating. This provides for a substantial abbreviation of the process for manufacturing highly reliable semiconductor devices.
  • FIG. 1 contains the cross section of a semiconductor device according to the present invention as fabricated in Examples 1 and 3
  • FIG. 2 contains the cross section of a semiconductor device according to the present invention as fabricated in Example 2 and 5.
  • the reported viscosity values were measured at 25° C.
  • the organopolysiloxane cures through an addition reaction to give a transparent silicone rubber with a durometer (JIS A) of 32.
  • a semiconductor element 2 carrying an aluminum circuit pattern was mounted on the surface of a glass substrate 1, and the bonding pads 3 on the top edges of the element 2 were then electrically connected to the lead frame 5 through gold bonding wires 4.
  • the fabricated semiconductor device was subsequently immersed in 1,1,1-trichloroethane at 25° C. for 30 minutes and then removed and again inspected with the stereoscopic microscope. Almost no swelling of the cured silicone 7 was observed. In addition, neither destruction or deformation of the semiconductor element 2 in the semiconductor device nor deformation or rupture of the bonding wires 4 were observed.
  • a semiconductor device was fabricated as in Example 1, with the exception that in this case the curable organopolysiloxane described in Example 1 was used by itself as the curable silicone composition. Substantial swelling of the cured silicone 7 was observed when this semiconductor device was immersed in 1,1,1-trichloroethane as in Example 1. While the semiconductor element 2 in the semiconductor device was not destroyed or deformed, deformation of some of the bonding wires 4 was observed.
  • a semiconductor element 2 carrying an aluminum circuit pattern was mounted on the surface of a glass circuit substrate 1, and the bonding pads 3 on the top edges of the element 2 were then electrically connected to the lead frame 5 through gold bonding wires 4.
  • the aforementioned curable silicone composition was thereafter coated on the surface of the semiconductor element 2. This was followed by holding at room temperature for 1 hour and then heating in a forced circulation oven at 150° C. for 30 minutes to yield the completed semiconductor device.
  • the fabricated semiconductor device was subsequently immersed in 1,1,1-trichloroethane at 25° C. for 30 minutes and then removed and again inspected with the stereoscopic microscope: almost no swelling of the cured silicone 7 was observed. In addition, neither destruction or deformation of the semiconductor element 2 in the semiconductor device nor deformation or rupture of the bonding wires 4 were observed.
  • a semiconductor element 2 carrying an aluminum circuit pattern was mounted on the surface of a glass substrate 1, and the bonding pads 3 on the top edges of the element 2 were then electrically connected to the lead frame 5 through gold bonding wires 4.
  • Example 3 Twenty semiconductor devices were fabricated as in Example 3, but in this case without using the hollow ceramic powder. These semiconductor devices were subjected to performance testing as in Example 3. Erratic operation was observed in 2 of the semiconductor elements.
  • Example 3 Twenty semiconductor devices were fabricated as in Example 3, but in this case using a silicone rubber dam 6 with a volume resistivity of 1 ⁇ 10 8 ohm-cm. These semiconductor devices were subjected to performance testing as in Example 3. No failure or erratic operation was observed for any of the semiconductor elements.
  • a semiconductor element 2 carrying an aluminum circuit pattern was mounted on the surface of a glass substrate 1, and the bonding pads 3 on the top edges of the element 2 were then electrically connected to the lead frame 5 through gold bonding wires 4.
  • the aforementioned curable silicone composition was thereafter coated on the surface of the semiconductor element 2. This was followed by holding at room temperature for 5 minutes and then heating in a forced circulation oven at 150° C. for 30 minutes to yield the completed semiconductor device. Twenty semiconductor devices were fabricated in this manner. Inspection of these semiconductor devices with a stereoscopic microscope showed that the hollow ceramic powder 9 present in the cured silicone 7 was dispersed only in the layer of cured material 7 remote from the element 2. Almost no powder 9 was observed in the layer of cured silicone 7 adjoining the semiconductor element 2, which as a result was transparent.
  • Example 5 Twenty semiconductor devices were fabricated as in Example 5, but in this case forming a ground by using an electrically conductive adhesive to fix a copper lead wire to the edge of the cured silicone 7 used in Example 5. These semiconductor devices were subjected to performance testing as in Example 5. No failure or erratic operation was observed for any of the semiconductor elements.

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)
US08/561,472 1994-11-24 1995-11-21 Semiconductor device having a cured silicone coating with non uniformly dispersed filler Expired - Fee Related US5907190A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/237,610 US5989942A (en) 1994-11-24 1999-01-25 Method for fabricating semiconductor device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP6314185A JPH08148612A (ja) 1994-11-24 1994-11-24 半導体装置およびその製造方法
JP6-314185 1994-11-24
JP6-339035 1994-12-29
JP33903594A JP3443196B2 (ja) 1994-12-29 1994-12-29 半導体装置およびその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US09/237,610 Division US5989942A (en) 1994-11-24 1999-01-25 Method for fabricating semiconductor device

Publications (1)

Publication Number Publication Date
US5907190A true US5907190A (en) 1999-05-25

Family

ID=26567850

Family Applications (2)

Application Number Title Priority Date Filing Date
US08/561,472 Expired - Fee Related US5907190A (en) 1994-11-24 1995-11-21 Semiconductor device having a cured silicone coating with non uniformly dispersed filler
US09/237,610 Expired - Fee Related US5989942A (en) 1994-11-24 1999-01-25 Method for fabricating semiconductor device

Family Applications After (1)

Application Number Title Priority Date Filing Date
US09/237,610 Expired - Fee Related US5989942A (en) 1994-11-24 1999-01-25 Method for fabricating semiconductor device

Country Status (3)

Country Link
US (2) US5907190A (de)
EP (1) EP0714125B1 (de)
DE (1) DE69514201T2 (de)

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6030854A (en) * 1996-03-29 2000-02-29 Intel Corporation Method for producing a multilayer interconnection structure
US6313514B1 (en) * 1997-06-06 2001-11-06 Infineon Technologies Ag Pressure sensor component
US6373142B1 (en) * 1999-11-15 2002-04-16 Lsi Logic Corporation Method of adding filler into a non-filled underfill system by using a highly filled fillet
US6380557B2 (en) * 1999-12-06 2002-04-30 Oki Electric Industry Co., Ltd. Test chip for evaluating fillers of molding material with dams formed on a semiconductor substrate to define slits for capturing the fillers
US6469086B1 (en) * 1997-12-19 2002-10-22 Infineon Technologies Ag Plastic molding compound, composite body, and filler for a plastic molding compound
US20030106707A1 (en) * 2001-12-11 2003-06-12 Vo Nhat D. Packaged integrated circuit and method therefor
US20030132776A1 (en) * 1998-10-05 2003-07-17 Cobbley Chad A. Method for in-line testing of flip-chip semiconductor assemblies
US6674172B2 (en) 2001-05-08 2004-01-06 International Business Machines Corporation Flip-chip package with underfill having low density filler
US6762508B1 (en) * 1998-02-27 2004-07-13 Canon Kabushiki Kaisha Semiconductor encapsulant resin having an additive with a gradient concentration
US20050003216A1 (en) * 2003-06-30 2005-01-06 Jean-Marc Frances Microparticle containing silicone release coatings having improved anti-block and release properties
US6909179B2 (en) * 1996-03-18 2005-06-21 Renesas Technology Corp. Lead frame and semiconductor device using the lead frame and method of manufacturing the same
US20050218517A1 (en) * 1997-07-21 2005-10-06 M.A. Capote Semiconductor flip-chip package and method for the fabrication thereof
US20050242447A1 (en) * 2004-04-29 2005-11-03 Infineon Technologies Ag Semiconductor device support element with fluid-tight boundary
US20050287350A1 (en) * 2004-06-28 2005-12-29 Crouthamel David L Encapsulating compound having reduced dielectric constant
DE102004049663B3 (de) * 2004-10-11 2006-04-13 Infineon Technologies Ag Kunststoffgehäuse und Halbleiterbauteil mit derartigem Kunststoffgehäuse sowie Verfahren zur Herstellung derselben
DE102004049654B3 (de) * 2004-10-11 2006-04-13 Infineon Technologies Ag Halbleiterbauteil mit Kunststoffgehäuse und Verfahren zur Herstellung desselben
US20090026558A1 (en) * 2004-09-07 2009-01-29 Infineon Technologies Ag Semiconductor device having a sensor chip, and method for producing the same
US20090101279A1 (en) * 1999-08-25 2009-04-23 Motohiro Arifuki Adhesive, method of connecting wiring terminals and wiring structure
US20120081872A1 (en) * 2010-09-30 2012-04-05 Alcatel-Lucent Canada Inc. Thermal warp compensation ic package
US9478473B2 (en) * 2013-05-21 2016-10-25 Globalfoundries Inc. Fabricating a microelectronics lid using sol-gel processing
CN106169462A (zh) * 2015-05-22 2016-11-30 南茂科技股份有限公司 薄膜覆晶封装堆叠结构及其制作方法
CN106169449A (zh) * 2015-05-22 2016-11-30 南茂科技股份有限公司 薄膜覆晶封装体及其散热方法
US20160365328A1 (en) * 2015-06-11 2016-12-15 International Business Machines Corporation Chip-on-chip structure and methods of manufacture
EP3605599A1 (de) * 2018-08-01 2020-02-05 Samsung Electronics Co., Ltd. Halbleitergehäuse und verfahren zur herstellung davon
US20200157348A1 (en) * 2018-11-19 2020-05-21 Shin-Etsu Chemical Co., Ltd. Photosensitive resin composition, pattern forming process, and antireflection film
CN113491009A (zh) * 2019-03-11 2021-10-08 积水化学工业株式会社 涂层剂、以及使用该涂层剂制造模块的制造方法
US12500130B2 (en) 2022-01-07 2025-12-16 Samsung Electronics Co., Ltd. Method of manufacture of fan-out type semiconductor package

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10016380C2 (de) * 2000-03-29 2002-01-24 Infineon Technologies Ag Gehäuse für ein elektrisches Bauteil
SE0101107D0 (sv) * 2001-03-28 2001-03-28 Ericsson Telefon Ab L M Encapsulation arrangement
DE10123232A1 (de) * 2001-05-12 2002-11-21 Infineon Technologies Ag Halbleitermodul
US6940177B2 (en) * 2002-05-16 2005-09-06 Dow Corning Corporation Semiconductor package and method of preparing same
DE10335155B4 (de) * 2003-07-31 2006-11-30 Infineon Technologies Ag Verfahren zum Herstellen einer Anordnung eines elektrischen Bauelements auf einem Substrat
DE102004064150B4 (de) * 2004-06-29 2010-04-29 Osram Opto Semiconductors Gmbh Elektronisches Bauteil mit Gehäuse mit leitfähiger Beschichtung zum ESD-Schutz
TWI393226B (zh) * 2004-11-04 2013-04-11 台灣積體電路製造股份有限公司 基於奈米管之填充物
JP5203575B2 (ja) * 2005-05-04 2013-06-05 ローム・アンド・ハース・エレクトロニック・マテリアルズ，エル．エル．シー． コーティング組成物
DE102009055765A1 (de) * 2009-09-30 2011-03-31 Osram Opto Semiconductors Gmbh Optisches oder optoelektronisches Bauelement und Verfahren zu dessen Herstellung
US9545043B1 (en) * 2010-09-28 2017-01-10 Rockwell Collins, Inc. Shielding encapsulation for electrical circuitry

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1549242A (en) * 1975-04-14 1979-08-01 Gen Electric Organosiloxane gels
JPS6151834A (ja) * 1984-08-20 1986-03-14 Mitsubishi Electric Corp 樹脂封止型半導体装置の製造方法
JPS6311310A (ja) * 1986-07-02 1988-01-18 Nippon Sheet Glass Co Ltd 複合材料
JPH01191056A (ja) * 1988-01-26 1989-08-01 Nippon Sheet Glass Co Ltd ＺｎＳｅ単結晶の転位密度の測定方法
JPH0292344A (ja) * 1988-09-29 1990-04-03 Toshiba Corp 超音波プローブ及び該プローブを備えた超音波診断装置
JPH02311520A (ja) * 1989-05-27 1990-12-27 Toshiba Chem Corp エポキシ樹脂組成物
JPH059270A (ja) * 1991-06-24 1993-01-19 Sumitomo Bakelite Co Ltd 樹脂組成物およびその製造方法
JPH05206325A (ja) * 1992-01-24 1993-08-13 Hitachi Ltd 半導体装置
JPH05283561A (ja) * 1992-03-30 1993-10-29 Nec Corp 樹脂封止型半導体装置
US5391924A (en) * 1992-09-14 1995-02-21 Kabushiki Kaisha Toshiba Plastic package type semiconductor device
US5571851A (en) * 1994-01-28 1996-11-05 J.M. Huber Corporation Reinforcing fillers for plastics systems
US5641997A (en) * 1993-09-14 1997-06-24 Kabushiki Kaisha Toshiba Plastic-encapsulated semiconductor device
US5683806A (en) * 1988-09-29 1997-11-04 Tomoegawa Paper Co., Ltd. Adhesive tapes

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60257546A (ja) * 1984-06-04 1985-12-19 Mitsubishi Electric Corp 半導体装置及びその製造方法
JPH0622265B2 (ja) * 1985-02-20 1994-03-23 株式会社日立製作所 半導体装置
JPS6292344A (ja) * 1985-10-18 1987-04-27 Hitachi Ltd 半導体装置
US5243756A (en) * 1991-06-28 1993-09-14 Digital Equipment Corporation Integrated circuit protection by liquid encapsulation
US5348913A (en) * 1993-08-06 1994-09-20 At&T Bell Laboratories Methods for encapsulating electronic devices
US5436203A (en) * 1994-07-05 1995-07-25 Motorola, Inc. Shielded liquid encapsulated semiconductor device and method for making the same

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1549242A (en) * 1975-04-14 1979-08-01 Gen Electric Organosiloxane gels
JPS6151834A (ja) * 1984-08-20 1986-03-14 Mitsubishi Electric Corp 樹脂封止型半導体装置の製造方法
JPS6311310A (ja) * 1986-07-02 1988-01-18 Nippon Sheet Glass Co Ltd 複合材料
JPH01191056A (ja) * 1988-01-26 1989-08-01 Nippon Sheet Glass Co Ltd ＺｎＳｅ単結晶の転位密度の測定方法
US5683806A (en) * 1988-09-29 1997-11-04 Tomoegawa Paper Co., Ltd. Adhesive tapes
JPH0292344A (ja) * 1988-09-29 1990-04-03 Toshiba Corp 超音波プローブ及び該プローブを備えた超音波診断装置
JPH02311520A (ja) * 1989-05-27 1990-12-27 Toshiba Chem Corp エポキシ樹脂組成物
JPH059270A (ja) * 1991-06-24 1993-01-19 Sumitomo Bakelite Co Ltd 樹脂組成物およびその製造方法
JPH05206325A (ja) * 1992-01-24 1993-08-13 Hitachi Ltd 半導体装置
JPH05283561A (ja) * 1992-03-30 1993-10-29 Nec Corp 樹脂封止型半導体装置
US5391924A (en) * 1992-09-14 1995-02-21 Kabushiki Kaisha Toshiba Plastic package type semiconductor device
US5641997A (en) * 1993-09-14 1997-06-24 Kabushiki Kaisha Toshiba Plastic-encapsulated semiconductor device
US5571851A (en) * 1994-01-28 1996-11-05 J.M. Huber Corporation Reinforcing fillers for plastics systems

Cited By (72)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6909179B2 (en) * 1996-03-18 2005-06-21 Renesas Technology Corp. Lead frame and semiconductor device using the lead frame and method of manufacturing the same
US6030854A (en) * 1996-03-29 2000-02-29 Intel Corporation Method for producing a multilayer interconnection structure
US6313514B1 (en) * 1997-06-06 2001-11-06 Infineon Technologies Ag Pressure sensor component
US20050218517A1 (en) * 1997-07-21 2005-10-06 M.A. Capote Semiconductor flip-chip package and method for the fabrication thereof
US6469086B1 (en) * 1997-12-19 2002-10-22 Infineon Technologies Ag Plastic molding compound, composite body, and filler for a plastic molding compound
US6762508B1 (en) * 1998-02-27 2004-07-13 Canon Kabushiki Kaisha Semiconductor encapsulant resin having an additive with a gradient concentration
US20040229404A1 (en) * 1998-02-27 2004-11-18 Canon Kabushiki Kaisha Semiconductor encapsulant resin having an additive with a gradient concentration
US6982177B2 (en) 1998-10-05 2006-01-03 Micron Technology, Inc. Method for in-line testing of flip-chip semiconductor assemblies
US6954081B2 (en) 1998-10-05 2005-10-11 Micron Technology, Inc. Method for in-line testing of flip-chip semiconductor assemblies
US7105366B2 (en) * 1998-10-05 2006-09-12 Micron Technology, Inc. Method for in-line testing of flip-chip semiconductor assemblies
US7074648B2 (en) 1998-10-05 2006-07-11 Micron Technology, Inc. Method for packaging flip-chip semiconductor assemblies
US20030141888A1 (en) * 1998-10-05 2003-07-31 Cobbley Chad A. Method for in-line testing of flip-chip semiconductor assemblies
US20040080332A1 (en) * 1998-10-05 2004-04-29 Cobbley Chad A Method for manufacturing flip-chip semiconductor assembly
US20040097009A1 (en) * 1998-10-05 2004-05-20 Cobbley Chad A. Method for packaging flip-chip semiconductor assemblies
US6750070B2 (en) 1998-10-05 2004-06-15 Micron Technology, Inc. Process for manufacturing flip-chip semiconductor assembly
US20030132776A1 (en) * 1998-10-05 2003-07-17 Cobbley Chad A. Method for in-line testing of flip-chip semiconductor assemblies
US7005878B2 (en) 1998-10-05 2006-02-28 Micron Technology, Inc. Method for in-line testing of flip-chip semiconductor assemblies
US6972200B2 (en) 1998-10-05 2005-12-06 Micron Technology, Inc. Method for manufacturing flip-chip semiconductor assembly
US20040263197A1 (en) * 1998-10-05 2004-12-30 Cobbley Chad A. Method for in-line testing of flip-chip semiconductor assemblies
US20040263196A1 (en) * 1998-10-05 2004-12-30 Cobbley Chad A. Method for in-line testing of flip-chip semiconductor assemblies
US20040263195A1 (en) * 1998-10-05 2004-12-30 Cobbley Chad A. Method for in-line testing of flip-chip semiconductor assemblies
US6967113B2 (en) 1998-10-05 2005-11-22 Micron Technology, Inc. Method for in-line testing of flip-chip semiconductor assemblies
US20050007141A1 (en) * 1998-10-05 2005-01-13 Cobbley Chad A. Method for in-line testing of flip-chip semiconductor assemblies
US20050007142A1 (en) * 1998-10-05 2005-01-13 Cobbley Chad A. Method for in-line testing of flip-chip semiconductor assemblies
US20050024080A1 (en) * 1998-10-05 2005-02-03 Cobbley Chad A. Method for in-line testing of flip-chip semiconductor assemblies
US6962826B2 (en) 1998-10-05 2005-11-08 Micron Technology, Inc. Method for in-line testing of flip-chip semiconductor assemblies
US6949943B2 (en) 1998-10-05 2005-09-27 Micron Technology, Inc. Method for in-line testing of flip-chip semiconductor assemblies
US6953700B2 (en) 1998-10-05 2005-10-11 Micron Technology, Inc. Method for in-line testing of flip-chip semiconductor assemblies
US6953699B2 (en) 1998-10-05 2005-10-11 Micron Technology, Inc. Method for in-line testing of flip-chip semiconductor assemblies
US8120189B2 (en) * 1999-08-25 2012-02-21 Hitachi Chemical Company, Ltd. Wiring terminal-connecting adhesive
US20090101279A1 (en) * 1999-08-25 2009-04-23 Motohiro Arifuki Adhesive, method of connecting wiring terminals and wiring structure
US8115322B2 (en) 1999-08-25 2012-02-14 Hitachi Chemical Company, Ltd. Adhesive, method of connecting wiring terminals and wiring structure
US6373142B1 (en) * 1999-11-15 2002-04-16 Lsi Logic Corporation Method of adding filler into a non-filled underfill system by using a highly filled fillet
US6500685B2 (en) * 1999-12-06 2002-12-31 Oki Electric Industry Co., Ltd. Method for evaluating molding material with dams formed on a semiconductor substrate to define slits for capturing fillers contained in the molding material
US6380557B2 (en) * 1999-12-06 2002-04-30 Oki Electric Industry Co., Ltd. Test chip for evaluating fillers of molding material with dams formed on a semiconductor substrate to define slits for capturing the fillers
US6815258B2 (en) 2001-05-08 2004-11-09 International Business Machines Corporation Flip-chip package with underfill having low density filler
US20040026792A1 (en) * 2001-05-08 2004-02-12 Vincent Michael B. Flip-chip package with underfill having low density filler
US6674172B2 (en) 2001-05-08 2004-01-06 International Business Machines Corporation Flip-chip package with underfill having low density filler
US20030106707A1 (en) * 2001-12-11 2003-06-12 Vo Nhat D. Packaged integrated circuit and method therefor
US6617524B2 (en) * 2001-12-11 2003-09-09 Motorola, Inc. Packaged integrated circuit and method therefor
CN1813022B (zh) * 2003-06-30 2010-05-05 罗迪亚公司 一种具有改善的防粘连性和剥离性的含微粒的硅酮隔离涂料
WO2005005555A3 (en) * 2003-06-30 2005-12-01 Rhodia Microparticle containing silicone release coating having improved anti-block and release properties
US20050003216A1 (en) * 2003-06-30 2005-01-06 Jean-Marc Frances Microparticle containing silicone release coatings having improved anti-block and release properties
US7501585B2 (en) * 2004-04-29 2009-03-10 Infineon Technologies Ag Semiconductor device support element with fluid-tight boundary
US20050242447A1 (en) * 2004-04-29 2005-11-03 Infineon Technologies Ag Semiconductor device support element with fluid-tight boundary
US20050287350A1 (en) * 2004-06-28 2005-12-29 Crouthamel David L Encapsulating compound having reduced dielectric constant
US7749797B2 (en) * 2004-09-07 2010-07-06 Infineon Technologies Ag Semiconductor device having a sensor chip, and method for producing the same
US20090026558A1 (en) * 2004-09-07 2009-01-29 Infineon Technologies Ag Semiconductor device having a sensor chip, and method for producing the same
DE102004049654B3 (de) * 2004-10-11 2006-04-13 Infineon Technologies Ag Halbleiterbauteil mit Kunststoffgehäuse und Verfahren zur Herstellung desselben
US20080050907A1 (en) * 2004-10-11 2008-02-28 Infineon Technologies Ag Semiconductor Component with Plastic Housing, and Process for Producing the Same
US7554196B2 (en) * 2004-10-11 2009-06-30 Infineon Technologies Ag Plastic package and semiconductor component comprising such a plastic package, and method for its production
US7327023B2 (en) 2004-10-11 2008-02-05 Infineon Technologies Ag Semiconductor component with plastic housing, and process for producing the same
US20060091522A1 (en) * 2004-10-11 2006-05-04 Ulrich Bachmaier Plastic package and semiconductor component comprising such a plastic package, and method for its production
US7772105B2 (en) 2004-10-11 2010-08-10 Infineon Technologies Ag Semiconductor component with plastic housing, and process for producing the same
DE102004049663B3 (de) * 2004-10-11 2006-04-13 Infineon Technologies Ag Kunststoffgehäuse und Halbleiterbauteil mit derartigem Kunststoffgehäuse sowie Verfahren zur Herstellung derselben
US20060076667A1 (en) * 2004-10-11 2006-04-13 Ulrich Bachmaier Semiconductor component with plastic housing, and process for producing the same
US20120081872A1 (en) * 2010-09-30 2012-04-05 Alcatel-Lucent Canada Inc. Thermal warp compensation ic package
US8912449B2 (en) 2010-09-30 2014-12-16 Alcatel Lucent Thermal warp compensation IC package
US9478473B2 (en) * 2013-05-21 2016-10-25 Globalfoundries Inc. Fabricating a microelectronics lid using sol-gel processing
CN106169462A (zh) * 2015-05-22 2016-11-30 南茂科技股份有限公司 薄膜覆晶封装堆叠结构及其制作方法
CN106169449A (zh) * 2015-05-22 2016-11-30 南茂科技股份有限公司 薄膜覆晶封装体及其散热方法
CN106169462B (zh) * 2015-05-22 2019-02-22 南茂科技股份有限公司 薄膜覆晶封装堆叠结构及其制作方法
US20160365328A1 (en) * 2015-06-11 2016-12-15 International Business Machines Corporation Chip-on-chip structure and methods of manufacture
EP3605599A1 (de) * 2018-08-01 2020-02-05 Samsung Electronics Co., Ltd. Halbleitergehäuse und verfahren zur herstellung davon
KR20200014637A (ko) * 2018-08-01 2020-02-11 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US11069588B2 (en) 2018-08-01 2021-07-20 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same
US11699626B2 (en) 2018-08-01 2023-07-11 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same
US20200157348A1 (en) * 2018-11-19 2020-05-21 Shin-Etsu Chemical Co., Ltd. Photosensitive resin composition, pattern forming process, and antireflection film
CN113491009A (zh) * 2019-03-11 2021-10-08 积水化学工业株式会社 涂层剂、以及使用该涂层剂制造模块的制造方法
US20220124911A1 (en) * 2019-03-11 2022-04-21 Sekisui Chemical Co., Ltd. Coating agent and method for manufacturing module using the coating agent
CN113491009B (zh) * 2019-03-11 2025-08-26 积水化学工业株式会社 涂层剂、以及使用该涂层剂制造模块的制造方法
US12500130B2 (en) 2022-01-07 2025-12-16 Samsung Electronics Co., Ltd. Method of manufacture of fan-out type semiconductor package

Also Published As

Publication number Publication date
EP0714125A2 (de) 1996-05-29
EP0714125B1 (de) 1999-12-29
DE69514201D1 (de) 2000-02-03
DE69514201T2 (de) 2000-08-03
EP0714125A3 (de) 1996-07-17
US5989942A (en) 1999-11-23

Similar Documents

Publication Publication Date Title
US5907190A (en) Semiconductor device having a cured silicone coating with non uniformly dispersed filler
US5173764A (en) Semiconductor device having a particular lid means and encapsulant to reduce die stress
US5891753A (en) Method and apparatus for packaging flip chip bare die on printed circuit boards
US6392309B1 (en) Semiconductor device including solid state imaging device
JP3692935B2 (ja) 半導体装置の製造方法
US5471027A (en) Method for forming chip carrier with a single protective encapsulant
US5461197A (en) Electronic device having a chip with an external bump terminal equal or smaller than a via hole on a board
KR100322154B1 (ko) 전자패키지상에보호피막을형성하는방법및전자패키지
US6238223B1 (en) Method of depositing a thermoplastic polymer in semiconductor fabrication
US6201301B1 (en) Low cost thermally enhanced flip chip BGA
EP0637839B1 (de) Chipträger mit einer Schutzschicht für die Schaltungsoberfläche
JPH0240942A (ja) 電子パツケージ
CN1305662A (zh) 表面声波器件封装以及方法
EP0124624B1 (de) Halbleitervorrichtung
JPH1135893A (ja) シート状ホットメルト接着剤、および半導体装置
US5360942A (en) Multi-chip electronic package module utilizing an adhesive sheet
US6087200A (en) Using microspheres as a stress buffer for integrated circuit prototypes
US5883439A (en) Semiconductor device molded in plastic package free from crack by virtue of organic stress relaxation layer
KR20010049733A (ko) 접착제 및 반도체 장치
JPH08316357A (ja) 樹脂封止型パワーモジュール装置
US20050167773A1 (en) Semiconductor element for solid state image sensing device and solid state image sensing device using the same
JP3443196B2 (ja) 半導体装置およびその製造方法
JP2633285B2 (ja) 車載用混成集積回路装置
EP0670595A1 (de) Mit Harz eingekapseltes Halbleiterbauelement
JP2000124262A (ja) 半導体装置

Legal Events

Date Code Title Description
AS Assignment

Owner name: DOW CORNING TORAY SILICONE COMPANY, LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ISHIKAWA, TAKAE;MINE, KATSUTOSHI;NAITO, HIROYOSI;AND OTHERS;REEL/FRAME:007780/0484

Effective date: 19951107

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20030525