US6103592A - Manufacturing self-aligned polysilicon fet devices isolated with maskless shallow trench isolation and gate conductor fill technology with active devices and dummy doped regions formed in mesas - Google Patents

Manufacturing self-aligned polysilicon fet devices isolated with maskless shallow trench isolation and gate conductor fill technology with active devices and dummy doped regions formed in mesas Download PDF

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US6103592A
US6103592A US08/850,093 US85009397A US6103592A US 6103592 A US6103592 A US 6103592A US 85009397 A US85009397 A US 85009397A US 6103592 A US6103592 A US 6103592A
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Prior art keywords
mesas
silicon
layer
oxide layer
dummy
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Expired - Fee Related
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US08/850,093
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Max Gerald Levy
Bernhard Fiegl
Walter Glashauser
Frank Prein
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Qimonda AG
International Business Machines Corp
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Siemens AG
International Business Machines Corp
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Priority to US08/850,093 priority Critical patent/US6103592A/en
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Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LEVY, MAX G.
Assigned to SIEMENS AKTIENGESELLSCHAFT reassignment SIEMENS AKTIENGESELLSCHAFT ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SIEMENS MICROELECTRONICS, INC.
Priority to DE69824481T priority patent/DE69824481T2/de
Priority to EP98303125A priority patent/EP0875927B1/en
Priority to JP10116498A priority patent/JPH1126595A/ja
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Assigned to INFINEON TECHNOLOGIES AG reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SIEMENS AKTIENGESELLSCHAFT
Assigned to QIMONDA AG reassignment QIMONDA AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INFINEON TECHNOLOGIES AG
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Definitions

  • This invention relates to semiconductor devices and more particularly to shallow trench isolation in self-aligned FET devices.
  • Maskless STI Planarization using Self-Aligned Polysilicon process allows STI to be planarized without a planarization mask, with minimal measurements and no need for wafer to wafer customization and can be designed to be completely ground rule compatible with a gate conductor stack Fill technology.
  • FIG. 3 shows an isolation region of a prior art MOSFET device 60 with a doped silicon semiconductor substrate 62 on which an STI region 72 has been formed. Above the STI region is formed a gate conductor stack 74 of fill layers comprising a polysilicon layer 64, a silicide layer 68, and a silicon nitride gate insulator layer 70.
  • Maskless STI (MSTI) Planarization for gate conductor Fill Technology is accomplished by designing the AA (active area) mask with dummy active silicon mesas within the holes of gate conductor punch-holes. These dummy active silicon mesas are designed with the same ground rules as the rest of the chip.
  • Dash et al. discusses STI planarization using polysilicon but differs from the present invention in several ways with respect to the level of the silicon oxide fill and the level of the polysilicon.
  • the silicon oxide RIE used after polysilicon CMP does not include the required break-thru step and stops on the silicon nitride instead of in the silicon oxide. Both the break-thru step and having the RIE stop in the silicon oxide were found to be essential in creating a manufacturable process.
  • a method for manufacture of a semiconductor FET device employing a Shallow Trench Isolation comprising the following steps.
  • the pad structures are composed of silicon nitride; or the pad structures are composed of a lower layer of silicon oxide capped with an upper layer of silicon nitride.
  • step one strips away the pad structures from the device and then forms gate oxide layers above the surfaces of the substrate exposed by stripping away the pad structures.
  • P-wells and N-wells are formed in the substrate beneath the gate oxide layer and the silicon oxide layer.
  • a step of blanket deposition of a gate conductor layer composed of a polysilicon sublayer and a silicide sublayer upon the device followed by blanket deposition of a dielectric layer, followed by patterning and etching of windows down to active device areas and dummy areas in the substrate followed by the step of formation of FET devices and dummy devices by ion implantation of a dose of source/drain dopant ions into the active device areas and the dummy areas in the P-wells and the N-wells.
  • a Shallow Trench Isolation (STI) semiconductor FET device comprises a doped silicon semiconductor substrate with raised active silicon device areas and dummy active silicon mesas capped with a gate oxide layer and the substrate being coated with a planarized silicon oxide layer elsewhere. There are P-wells and N-wells formed in the substrate beneath the gate oxide layers and the silicon oxide layer, and a gate conductor layer and a dielectric layer formed over the gate oxide layers and the silicon oxide layer patterned into active devices, and dummy devices.
  • STI Shallow Trench Isolation
  • a Shallow Trench Isolation (STI) semiconductor FET device comprises a doped silicon semiconductor substrate with raised active silicon device areas and dummy active silicon mesas capped with a gate oxide layer and the substrate being coated with a planarized silicon oxide layer elsewhere, a gate conductor layer and a dielectric layer formed over the gate oxide layers, and polysilicon and dielectric layers being formed above the silicon oxide layer which are then patterned into dummy devices surrounding the mesas providing a pattern of punch hole vias.
  • STI Shallow Trench Isolation
  • the pad structure is stripped from the device and a gate oxide layer is formed above the surface of the substrate exposed as the pad structure is stripped away.
  • FET devices with gate structure are formed on the surface of the device with gate conductor structures and dummy structures formed on the surface of the planar silicon oxide layer.
  • Gate Conductor (GC) stack Filli over trenches, and etch of the fill to produce vias for vertical contacts to diffusion areas on active sites.
  • FIGS. 1A-1O illustrate a process of manufacturing a Shallow Trench Isolation (STI) device in accordance with this invention.
  • STI Shallow Trench Isolation
  • FIGS. 2A-2G illustrate a process of manufacturing a Shallow Trench Isolation (STI) device in accordance with this invention with deep trench capacitor structures.
  • STI Shallow Trench Isolation
  • FIG. 3 shows an isolation region of a prior art MOSFET device.
  • FIG. 4 shows a perspective view of the device in accordance with this invention with a dummy area in which the vias reach down into dummy regions where no active devices have been formed.
  • the structure is otherwise the same as the device described in FIGS. 1A-10.
  • FIGS. 1A-10 illustrate a process of manufacturing a Shallow Trench Isolation (STI) device 10 in accordance with this invention.
  • STI Shallow Trench Isolation
  • FIG. 1A shows the device 10 in an early stage of manufacture.
  • the device 10 is formed on a P-doped silicon substrate 11 upon which pad silicon dioxide/silicon nitride pad layer segments 14/14' have been formed.
  • the silicon nitride in pad layer segments 14/14' is to serve as an etch stop.
  • the silicon dioxide layer has a thickness from about 50 ⁇ to about 150 ⁇ and the silicon nitride layer has a thickness from about 1,000 ⁇ to about 1,500 ⁇ .
  • the active area mask 15/15' has been formed on the surface of silicon nitride layer segments 14/14' to protect the pad silicon dioxide/silicon nitride pad layer segments 14/14' and the silicon mesas 12/12' formed from the substrate 11 beneath the mask 15/15' during etching of the pad layers 14/14' into the pattern of mask 15/15', and during subsequent etching through mask 15/15' to form a set of shallow trenches 9/9'/9" in substrate 11 to a depth H below the surface of the pad layer segments 14/14'.
  • the depth H is from about 0.35 ⁇ m to about 0.48 ⁇ m below the upper surface of the pad layer segments 14/14'.
  • FIG. 1B shows the device 10 of FIG. 1A after the mask 15/15' has been stripped away from the device 10, leaving the substrate 11 with the raised (mesa) active areas 12, 12' covered with structures comprising pad layer segments 14, 14'.
  • the space between the structures comprising pad layer segments 14, 14' is a width W from about 0.25 ⁇ m to about 250 ⁇ m.
  • FIG. 1C shows the device 10 of FIG. 1B after deposition of a silicon dioxide layer 22 (having a thickness from about 4,800 ⁇ to about 5,600 ⁇ ) on the device 10 covering the shallow trenches 9/9'/9" and the structures comprising pad layer segments 14/14' and the mesas 12/12'.
  • a silicon dioxide layer 22 having a thickness from about 4,800 ⁇ to about 5,600 ⁇
  • the silicon dioxide layer 22 on device 10 is covered by deposition of a blanket polysilicon layer 24 on silicon oxide layer 22.
  • Layer 24 has a thickness from about 4,000 ⁇ to about 4,800 ⁇ .
  • FIG. 1D shows the device 10 of FIG. 1C after CMP (Chemical Mechanical) Polishing of blanket polysilicon layer 24 down to those portions of silicon dioxide layer 22 which are exposed because they overlie the remaining portions of the pad layer segments 14/14' above the mesas 12/12'.
  • CMP Chemical Mechanical Polishing
  • FIG. 1E shows the device 10 of FIG. 1D after selective RIE partial etching of the exposed surface of the silicon dioxide layer 22 forming hollows 22' and 22" above the pad layer segments 14/14' above the mesas 12/12'.
  • the etching removes a thickness from about 3,200 ⁇ to about 4,700 ⁇ of the silicon dioxide layer 22 over the remaining areas of pad layer 14/14'.
  • FIG. 1F shows the device 10 of FIG. 1E after removal of the remainder of the polysilicon layer 24 with a selective etchant which removes the polysilicon layer 24 while leaving the silicon dioxide structure 22 with hollows 22'/22" intact. In this case a thickness from about 200 ⁇ to about 4,300 ⁇ of polysilicon layer 24 is removed.
  • FIG. 1G shows the device 10 of FIG. 1F after a CMP process was used for about 50 seconds to about 70 seconds planarizing silicon dioxide layer 22 and clearing away the silicon nitride portions of pad layer segments 14/14'.
  • the CMP process leaves the surface of device 10 as a planarized surface of silicon dioxide layer 22.
  • FIG. 1H shows the device 10 of FIG. 1G after the silicon nitride etch stop and the silicon dioxide layers of the pad layer 14/14' have been stripped from device 10 leaving openings 24/24' (where layer 14/14' had been) in planar silicon dioxide layer 22 down to the surfaces of the mesas 12/12' exposed between the remaining portions of the silicon dioxide layer 22.
  • FIG. 1I shows the device 10 of FIG. 1H after "gate" sacrificial silicon dioxide gate segments 30/30' about 125 ⁇ thick have been formed above the mesas 12/12' by the conventional process of oxidation of the exposed surface of the substrate 11. Then V T implants are made through the sacrificial silicon dioxide gate segments 30/30' into the substrate 11.
  • an N-well mask 31" has been formed over the device 11 with a N-well window 31'" over the sacrificial silicon dioxide gate segments 30/30' through which N type dopant ions 31' are ion implanted into the surface of substrate 11 below the gate segment 30 to form an N-well 34.
  • FIG. 1J shows the device 10 of FIG. 1I after N-well mask 31" has been stripped away and a P-well mask 32" has been formed over the device 11 with a P-well window 32'" over the sacrificial silicon oxide gate segment 30' through which P type dopant ions 32' are ion implanted into the surface of substrate 11 below the gate segment 30 forming a P-well region 36.
  • FIG. 1K shows the device 10 of FIG. 1J after the sacrificial silicon oxide gate segments 30/30' have been stripped away by etching which also thins the silicon dioxide layer 22 into thinned planar oxide larger 22' to be coplanar with the surface of device 11. Then conventional gate silicon oxide (gate oxide) layer segments 38/38' (about 100 ⁇ thick) are formed on the surface of the mesas 12/12' within the recently enlarged openings 24/24'.
  • gate silicon oxide (gate oxide) layer segments 38/38' about 100 ⁇ thick
  • FIG. 1L shows the device 10 of FIG. 1K after the thinned planar oxide layer 22' and the gate oxide layer segments 38/38' have been coated with a doped polysilicon layer 40 preferably about 1000 ⁇ thick, with a thickness range from about 500 ⁇ to about 2,000 ⁇ .
  • Polysilicon layer 40 is coated with a silicide layer 42 preferably a tungsten silicide layer about 800 ⁇ thick, with a thickness range from about 500 ⁇ to about 2,000 ⁇ .
  • Tungsten silicide layer 42 is coated with a silicon dioxide or silicon nitride gate insulator layer 44 preferably about 2800 ⁇ thick, with a thickness range from about 2,000 ⁇ to about 4,000 ⁇ .
  • the device is coated with a photoresist gate stack mask 46 with openings 48A, 48B therethrough over the ends of gate oxide layer segment 38 over N-well 34 and opening 48C therethrough over gate oxide layer segment 38' P-well 36.
  • FIG. 1M shows the device 10 of FIG. 1L after the introducing the RIE etchant through openings 48A, 48B, and 48C down through gate insulator layer 44 etching openings 50A, 50B, and 50C therein extending down through tungsten silicide layer 42 and doped polysilicon layer 40 to expose the surface of the gate oxide layer segments 38/38' leaving a gate conductor stack 51 over N-well 34 with source/drain windows on either side and a dummy window 50C exposing the P-well for ion implanting subsequently, as indicated by arrows 58 in FIG. 10 which is described below.
  • FIG. 1N shows the device 10 FIG. 1M after ion implanting the P+ dopant source/drain regions 56S/56D below the silicon oxide segment 38 self-aligned with the gate conductor stack 51.
  • FIG. 10 shows the device 10 of FIG. 1N after ion implanting N+ dopant into N+ region 58 through the dummy opening 50C, as indicated by arrow 58, to form N+ region 58(N+) in P-well 36, below silicon oxide segment 38'.
  • MSTI maskless STI
  • FIGS. 2A-2G illustrate a process of manufacturing a Shallow Trench Isolation (STI) device 10 in accordance with this invention with deep trench capacitor structures 16.
  • STI Shallow Trench Isolation
  • FIG. 4 shows a perspective, sectional view of a portion of the device 10 in accordance with this invention with a dummy area in which the vias 54 reach down into dummy regions where no active devices have been formed.
  • the structure is otherwise the same as the device described in FIGS. 1A-10.
  • the device 10 is formed on the P-doped silicon substrate 11 upon which silicon mesas 12 have been formed from the substrate 11 between the recesses therein containing the shallow trenches filled with the silicon oxide regions 22 upon which dummy gate conductor stacks of polysilicon layer 40, silicide layer 42 and the silicon dioxide or silicon nitride dielectric layer 44 have been formed. Between the dummy conductor stacks are the vias 54 (punch holes) which extend down to the top of the mesas 12.
  • LOCOS is inexpensive but suffers from insulator thinning at narrow dimensions, bird's beak formation, field-implant encroachment, and creates significant wafer topography.
  • Poly-Buffered LOCOS and Poly-encapsulated LOCOS improved the bird's beak formation but still result in a narrow channel effect that increases device Vts.
  • Shallow Trench Isolation provides an abrupt active-to-isolation transition without bird's beak formation with a minimum impact on device characteristics or topography.
  • the process often requires extensive measurements and wafer to wafer process customization to control, i.e., a resist planarization mask used for fabrication of a 16 Mb DRAM, and has a higher cost than LOCOS based methods.
  • a manufacturable STI planarization process using Self-Aligned polysilicon and a planarization mask provides a stable and reliable process with a robust process window. It does not require extensive inline measurements or wafer to wafer process customization to control.
  • the Self-Aligned Poly-silicon planarization process can be greatly simplified by use of mesas of active silicon within the STI regions in accordance with this invention.
  • Substrates start with an STI of depth "H” with maximum width W.
  • “H” depends on device design requirements.
  • “W” depends on planarization distance of CMP pad used for polishing sacrificial polysilicon ( ⁇ 30-50 ⁇ m for an IC1000 CMP Pad);
  • STI shapes are designed to have active silicon mesas placed within the gate conductor stack-Fill "punch-hole" areas;
  • the cost has been calculated to decrease from about $145 to about $117 for the STI planarization module using MSTI.
  • MSTI By designing active silicon mesas within large STI regions (within the gate conductor stack-Fill punch-hole areas in a gate conductor stack-Fill technology) and limiting the largest STI width to the planarization distance of CMP pad used for polishing the sacrificial polysilicon (-30-50 ⁇ m for an IC1000 CMP pad), MSTI can be easily implemented.
  • GC gate conductor

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  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Semiconductor Memories (AREA)
  • Weting (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
US08/850,093 1997-05-01 1997-05-01 Manufacturing self-aligned polysilicon fet devices isolated with maskless shallow trench isolation and gate conductor fill technology with active devices and dummy doped regions formed in mesas Expired - Fee Related US6103592A (en)

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US08/850,093 US6103592A (en) 1997-05-01 1997-05-01 Manufacturing self-aligned polysilicon fet devices isolated with maskless shallow trench isolation and gate conductor fill technology with active devices and dummy doped regions formed in mesas
DE69824481T DE69824481T2 (de) 1997-05-01 1998-04-23 Verfahren zur Herstellung von FET-Bauelementen mit flacher,maskenloser Grabenisolation
EP98303125A EP0875927B1 (en) 1997-05-01 1998-04-23 Method of manufacturing FET devices with maskless shallow trench isolation (STI)
JP10116498A JPH1126595A (ja) 1997-05-01 1998-04-27 浅いトレンチ分離およびゲート導体充填技術によって分離された自己整合ポリシリコンｆｅｔデバイス、およびその製造方法

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JPH1126595A (ja) 1999-01-29
DE69824481D1 (de) 2004-07-22
EP0875927B1 (en) 2004-06-16

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