US6861684B2 - Method of fabricating a vertical insulated gate transistor with low overlap of the gate on the source and the drain, and an integrated circuit including this kind of transistor - Google Patents

Method of fabricating a vertical insulated gate transistor with low overlap of the gate on the source and the drain, and an integrated circuit including this kind of transistor Download PDF

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Publication number
US6861684B2
US6861684B2 US10/114,329 US11432902A US6861684B2 US 6861684 B2 US6861684 B2 US 6861684B2 US 11432902 A US11432902 A US 11432902A US 6861684 B2 US6861684 B2 US 6861684B2
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gate
source
pillar
integrated circuit
transistor
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US20020177265A1 (en
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Thomas Skotnicki
Emmanuel Josse
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STMicroelectronics SA
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STMicroelectronics SA
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01314—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of Ge, C or of compounds of Si, Ge or C contacting the insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
    • H10D64/0133—Aspects related to lithography, isolation or planarisation of the conductor at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes

Definitions

  • the invention relates to integrated circuits and more particularly to vertical insulated gate transistors.
  • the invention applies in particular, although not exclusively, to high-speed logic circuits and radio-frequency circuits. More generally, the invention finds an application in technologies below 0.07 micron.
  • the vertical transistor is a device that overcomes the limitations of the planar MOS transistor, in lengths less than 0.1 micron.
  • Its conduction body consists of a silicon pillar insulated and covered by a gate. It therefore has at least two conduction interfaces. Accordingly, the current I on and the transconductance per unit width are at least doubled.
  • conduction over a plurality of interfaces, in conjunction with the coupling of the gates makes it possible to eliminate the need to form ultrafine gate oxides or high-permittivity dielectrics.
  • the vertical transistor is a technological platform particularly suitable for implementing a coating gate architecture with ultrashort dimensions. This is because the channel length in the vertical transistor is not fixed by the photolithographic resolution. It is therefore possible to form channels with very small dimensions using standard photolithographic equipment. Also, coating a projecting silicon pillar with a gate is much simpler than coating a thin silicon film buried in a substrate.
  • the person skilled in the art knows of many methods of fabricating a vertical insulated gate transistor, using different techniques to form the silicon pillar.
  • the silicon pillar is grown epitaxially in an open window in a dielectric stack.
  • the silicon pillar is etched anisotropically from the insulated substrate.
  • forming the pillar by etching resembles etching the gate of a planar transistor.
  • the pillar is doped after it is formed, although it could be doped during epitaxial growth or before etching.
  • the source and drain regions are implanted in a self-aligned manner relative to the pillar.
  • the source can also be implanted before epitaxial growth, in which case it is referred to as “continuous” (the source areas on either side of the pillar are joined together).
  • the gate oxide is then formed on the flanks of the silicon pillar.
  • the polysilicon gate is then deposited, doped and then etched.
  • the gate greatly overlaps the source and drain areas, with an oxide between them whose thickness is comparable to that of the gate oxide.
  • This overlap represents a serious penalty, as the associated capacitors (that associated with the overlapping of the gate on the drain and that associated with the overlapping of the gate on the source) contribute to the total load capacitance of an individual cell.
  • this state necessarily renders the vertical transistor inappropriate for radio-frequency applications necessitating high transition frequencies, since the transition frequency of an MOS transistor is directly proportional to the reciprocal of the overlap capacitances.
  • One way to reduce the overlap capacitances is to decouple the growth of the oxide on the flanks of the pillar from the growth of the oxide on the substrate.
  • existing techniques for reducing the overlap of the gate on the source or the drain still yield poor performance, especially in the case of a pillar formed by anisotropic etching.
  • One object of the invention is to propose a method of fabricating a vertical insulated gate transistor which is based on anisotropic etching of the silicon pillar and reduces the electrical capacitances due to the overlapping of the gate of the vertical transistor, whilst being simple to implement and compatible with a CMOS fabrication process.
  • the invention therefore proposes a method of fabricating a vertical insulated gate transistor, the method including forming a vertical semiconductor pillar on a semiconductor substrate by anisotropic etching and forming a dielectrically isolated semiconductor gate resting on the flanks of the pillar and on the top surface of the substrate.
  • forming the insulated gate includes:
  • cavities can in theory be filled with a gaseous dielectric, for example air, it is preferable to fill them with a solid dielectric material.
  • the cavities can be filled by oxidation or deposition of a dielectric material.
  • the formation of the vertical pillar includes epitaxial growth of a semiconductor layer on the substrate and anisotropic etching of said epitaxially grown semiconductor layer.
  • the invention also proposes an integrated circuit including a vertical insulated gate transistor including, on a semiconductor substrate, a vertical pillar having one of the source and drain regions at the top, the other of the source and drain regions being situated in the substrate at the periphery of the pillar.
  • the transistor also includes a gate dielectric layer situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer.
  • the gate includes a semiconductor block having a first region resting on the gate dielectric layer and a second region facing at least portions of the source and drain regions and separated from those source and drain region portions by dielectric cavities.
  • the first region of the gate semiconductor block is formed of a first semiconductor material, for example silicon-germanium alloy, and the second region of the gate semiconductor block is formed of a second semiconductor material, for example silicon.
  • the percentage of germanium can be from approximately 30% to approximately 50%.
  • the length of the cavities can be from approximately 25 nm to approximately 40 nm, and the width of the cavities can be from approximately 30 nm to approximately 60 nm.
  • FIGS. 1 to 14 show the principal steps of one embodiment of a method according to the invention, yielding one embodiment of a transistor according to the invention.
  • FIG. 1 shows a semiconductor, for example silicon, substrate 1 including lateral isolation areas 2 using the shallow trench isolation technique.
  • the lateral isolation areas 2 delimit an active substrate area in and on which the future vertical transistor will be formed.
  • insulating wells are also implanted in the substrate 1 . They are not shown in FIG. 1 , for simplicity.
  • a layer of silicon 3 ( FIG. 2 ) is then grown epitaxially on the top surface of the structure shown in FIG. 1 .
  • the thickness of the layer 3 fixes the height of the future silicon pillar.
  • epitaxial growth is not selective, leading to growth of the silicon layer both on the substrate 1 and on the lateral isolation area 2 .
  • the epitaxial growth can instead be selective with respect to the lateral isolation area 2 .
  • the silicon layer 3 is grown only on the silicon of the substrate.
  • the silicon layer and the substrate are doped by implantation 4 .
  • This implantation the type and dosage of which depend on the required characteristics of the transistor, will provide the doping of the channel of the future transistor.
  • the pillar 5 of the future transistor is etched anisotropically.
  • the etching can be carried out with detection of end of attack on reaching the isolation or for a fixed time.
  • FIG. 5 a sacrificial oxide 6 is formed on the surface of the structure shown in FIG. 4 .
  • the source region S and drain region D are then formed by implantation 40 self-aligned with respect to the pillar 5 , which provides a connection between the body of the pillar and the substrate.
  • the source can instead be implanted before the silicon layer 3 is grown epitaxially, at the same time as the isolating wells are implanted. In this case, the source S is continuous.
  • the sacrificial oxide 6 is removed by conventional deoxidation.
  • a gate oxide layer 7 is then formed, for example grown in a furnace (FIG. 8 ).
  • a layer 8 of a polycrystalline silicon-germanium alloy is then deposited (FIG. 9 ).
  • the conventional conform deposit is known in itself.
  • a polysilicon layer 9 is deposited, also by a conventional conform deposition (FIG. 10 ).
  • the stack of gates formed of the polysilicon layer 9 and the polycrystalline-silicon-germanium layer 8 is then doped by implantation.
  • the gate semiconductor block is then formed ( FIG. 11 ) by anisotropically etching the stack of layers 9 and 8 , stopping at the oxide layer 7 .
  • FIG. 11 shows that at this stage of the process the gate semiconductor block has a silicon-germanium part 80 resting on the gate oxide and a silicon part 90 resting on the part 80 .
  • the silicon-germanium 80 is then selectively etched with respect to the polysilicon 90 and the gate oxide 7 , in a manner that is known in itself, to form cavities 10 and 11 (FIG. 12 ).
  • the gate semiconductor block has a silicon-germanium first region 800 resting on the gate dielectric layer 7 and a second region 90 facing a portion of the drain region D and a portion of the source region S. Also, the second region 90 is separated from these portions of the source and drain regions by the cavities 11 and 10 .
  • the overlapping of the gate onto the source and the drain is significantly reduced.
  • the interface between the gate and the oxide in the channel area still consists of polycrystalline silicon-germanium.
  • the next step consists of re-oxidizing the gate or depositing an oxide to fill the open cavities 10 and 11 with dielectric, for example with silicon dioxide 12 .
  • the transistor according to the invention therefore includes, on a semiconductor substrate 1 , a vertical pillar 5 incorporating the drain region D at the top.
  • the source region S is situated in the substrate at the periphery of the pillar 5 .
  • a gate dielectric layer 7 is situated on the flank of the pillar on the top surface of the substrate.
  • the semiconductor gate which rests on the gate dielectric layer, includes a semiconductor block having a silicon-germanium first region 800 resting on the gate dielectric layer 7 and a second region 90 facing a portion of the drain D and a portion of the source S, the second region being separated from these portions of the source and drain regions by dielectric cavities 14 S and 14 D.
  • the length LS of the cavity 14 S and the length LD of the cavity 14 D can be from approximately 25 nm to approximately 40 nm. Also, the width of these cavities, i.e. the thickness of the silicon-germanium layer, can be from approximately 30 nm to approximately 60 nm.
  • FIG. 14 is a top view of the structure from FIG. 13 , additionally showing the source, drain and gate contacts.
  • the interface between the gate and the gate oxide in the area of the channel is still of polycrystalline-silicon-germanium at the end of the process.
  • using a silicon-germanium layer with a small proportion of germanium improves activation of the boron and the phosphorus, which are the usual dopants of P + and N + gates. This significantly reduces the phenomenon of gate impoverishment (depletion), which in turn contributes to improving the current I on and further reducing the effects of the short channels.
  • the invention reduces the capacitances due to the overlapping of the gate onto the drain and the source. This automatically increases the transition frequency of the transistor.
  • the cavity has almost forty times the thickness of the gate oxide layer (15 ⁇ in a 0.1 micron technology).
  • the associated capacitance is therefore divided by forty by virtue of the formation of the cavities.
  • the invention therefore fully exploits the advantages of the vertical transistor.
  • the silicon pillar to be formed by anisotropic etching, which is particularly simple to implement, and renders the implementation compatible for high-speed logic and radio-frequency applications.

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  • Insulated Gate Type Field-Effect Transistor (AREA)
US10/114,329 2001-04-02 2002-04-02 Method of fabricating a vertical insulated gate transistor with low overlap of the gate on the source and the drain, and an integrated circuit including this kind of transistor Expired - Lifetime US6861684B2 (en)

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FR0104436 2001-04-02
FR0104436A FR2823009B1 (fr) 2001-04-02 2001-04-02 Procede de fabrication d'un transistor vertical a grille isolee a faible recouvrement de la grille sur la source et sur le drain, et circuit integre comportant un tel transistor

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US20070045741A1 (en) * 2005-09-01 2007-03-01 Leonard Forbes DRAM tunneling access transistor
US20090029513A1 (en) * 2007-07-27 2009-01-29 Stmicroelectronics, Inc. Vertical quadruple conduction channel insulated gate transistor
US20100270611A1 (en) * 2009-04-28 2010-10-28 Fujio Masuoka Semiconductor device including a mos transistor and production method therefor
US20110079841A1 (en) * 2009-10-01 2011-04-07 Fujio Masuoka Semiconductor device
US20110215381A1 (en) * 2010-03-08 2011-09-08 Fujio Masuoka Solid state imaging device
US20120196415A1 (en) * 2008-01-29 2012-08-02 Unisantis Electronics Singapore Pte Ltd. Semiconductor device and production method therefor
US8372713B2 (en) 2008-01-29 2013-02-12 Unisantis Electronics Singapore Pte Ltd. Semiconductor device and production method therefor
US8482041B2 (en) 2007-10-29 2013-07-09 Unisantis Electronics Singapore Pte Ltd. Semiconductor structure and method of fabricating the semiconductor structure
US8486785B2 (en) 2010-06-09 2013-07-16 Unisantis Electronics Singapore Pte Ltd. Surround gate CMOS semiconductor device
US8487357B2 (en) 2010-03-12 2013-07-16 Unisantis Electronics Singapore Pte Ltd. Solid state imaging device having high sensitivity and high pixel density
US8564034B2 (en) 2011-09-08 2013-10-22 Unisantis Electronics Singapore Pte. Ltd. Solid-state imaging device
US8669601B2 (en) 2011-09-15 2014-03-11 Unisantis Electronics Singapore Pte. Ltd. Method for producing semiconductor device and semiconductor device having pillar-shaped semiconductor
US8748938B2 (en) 2012-02-20 2014-06-10 Unisantis Electronics Singapore Pte. Ltd. Solid-state imaging device
US8772175B2 (en) 2011-12-19 2014-07-08 Unisantis Electronics Singapore Pte. Ltd. Method for manufacturing semiconductor device and semiconductor device
US8916478B2 (en) 2011-12-19 2014-12-23 Unisantis Electronics Singapore Pte. Ltd. Method for manufacturing semiconductor device and semiconductor device
US9153697B2 (en) 2010-06-15 2015-10-06 Unisantis Electronics Singapore Pte Ltd. Surrounding gate transistor (SGT) structure
US20150295040A1 (en) * 2014-04-14 2015-10-15 Taiwan Semiconductor Manufacturing Company Limited Systems and methods for fabricating vertical-gate-all-around transistor structures
US20180068903A1 (en) * 2016-09-08 2018-03-08 International Business Machines Corporation Low resistance source-drain contacts using high temperature silicides
US10600778B2 (en) 2017-11-16 2020-03-24 International Business Machines Corporation Method and apparatus of forming high voltage varactor and vertical transistor on a substrate
US20240332418A1 (en) * 2023-03-30 2024-10-03 Winbond Electronics Corp. Semiconductor device and method forming the same

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US20070052012A1 (en) * 2005-08-24 2007-03-08 Micron Technology, Inc. Vertical tunneling nano-wire transistor
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US7425491B2 (en) 2006-04-04 2008-09-16 Micron Technology, Inc. Nanowire transistor with surrounding gate
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US7491995B2 (en) 2006-04-04 2009-02-17 Micron Technology, Inc. DRAM with nanofin transistors
KR100929635B1 (ko) * 2007-11-05 2009-12-03 주식회사 하이닉스반도체 수직형 트랜지스터 및 그의 형성방법
KR102050561B1 (ko) 2012-12-18 2020-01-09 삼성디스플레이 주식회사 수직형 박막트랜지스터 및 이의 제조 방법
US9755033B2 (en) 2014-06-13 2017-09-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of forming vertical structure
US10361300B2 (en) * 2017-02-28 2019-07-23 International Business Machines Corporation Asymmetric vertical device
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US20100289559A1 (en) * 2005-09-01 2010-11-18 Micron Technology, Inc. Dram tunneling access transistor
US7446372B2 (en) * 2005-09-01 2008-11-04 Micron Technology, Inc. DRAM tunneling access transistor
US20090046504A1 (en) * 2005-09-01 2009-02-19 Micron Technology, Inc. Dram tunneling access transistor
US7772066B2 (en) 2005-09-01 2010-08-10 Micron Technology, Inc. DRAM tunneling access transistor
US20070045741A1 (en) * 2005-09-01 2007-03-01 Leonard Forbes DRAM tunneling access transistor
US7983070B2 (en) 2005-09-01 2011-07-19 Micron Technology, Inc. DRAM tunneling access transistor
US20090029513A1 (en) * 2007-07-27 2009-01-29 Stmicroelectronics, Inc. Vertical quadruple conduction channel insulated gate transistor
US8679903B2 (en) 2007-07-27 2014-03-25 Stmicroelectronics, Inc. Vertical quadruple conduction channel insulated gate transistor
US8482041B2 (en) 2007-10-29 2013-07-09 Unisantis Electronics Singapore Pte Ltd. Semiconductor structure and method of fabricating the semiconductor structure
US8598650B2 (en) 2008-01-29 2013-12-03 Unisantis Electronics Singapore Pte Ltd. Semiconductor device and production method therefor
US20120196415A1 (en) * 2008-01-29 2012-08-02 Unisantis Electronics Singapore Pte Ltd. Semiconductor device and production method therefor
US8343835B2 (en) * 2008-01-29 2013-01-01 Unisantis Electronics Singapore Pte Ltd. Semiconductor device and production method therefor
US8372713B2 (en) 2008-01-29 2013-02-12 Unisantis Electronics Singapore Pte Ltd. Semiconductor device and production method therefor
US8647947B2 (en) 2009-04-28 2014-02-11 Unisantis Electronics Singapore Pte Ltd. Semiconductor device including a MOS transistor and production method therefor
US8497548B2 (en) 2009-04-28 2013-07-30 Unisantis Electronics Singapore Pte Ltd. Semiconductor device including a MOS transistor and production method therefor
US20100270611A1 (en) * 2009-04-28 2010-10-28 Fujio Masuoka Semiconductor device including a mos transistor and production method therefor
US8610202B2 (en) 2009-10-01 2013-12-17 Unisantis Electronics Singapore Pte Ltd. Semiconductor device having a surrounding gate
US20110079841A1 (en) * 2009-10-01 2011-04-07 Fujio Masuoka Semiconductor device
US8575662B2 (en) 2010-03-08 2013-11-05 Unisantis Electronics Singapore Pte Ltd. Solid state imaging device having high pixel density
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