US6913971B2 - Layer transfer methods - Google Patents

Layer transfer methods Download PDF

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US6913971B2
US6913971B2 US10/616,586 US61658603A US6913971B2 US 6913971 B2 US6913971 B2 US 6913971B2 US 61658603 A US61658603 A US 61658603A US 6913971 B2 US6913971 B2 US 6913971B2
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recess
substrate
zone
weakness
source substrate
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US20040082147A1 (en
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Bernard Aspar
Séverine Bressot
Olivier Rayssac
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Soitec SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Commissariat a lEnergie Atomique CEA
Soitec SA
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1924Preparing SOI wafers with separation/delamination along a porous layer
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • H10P90/1916Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Definitions

  • the present invention relates to improved methods for transferring a layer of material from a source substrate onto a support substrate during the fabrication of composite substrates, in particular for optics, optoelectronics, or electronics.
  • Novel techniques have recently been developed for transferring a layer of a material, such as a processed layer of semiconductor material, from a first or “source” substrate onto a second or “support” substrate.
  • the term “processed layer” means a layer of material that has undergone some or all of the steps of a technique for forming electronic components. Transfer techniques may use a source substrate that has a weakened zone that was formed by implanting atomic species, or a substrate having a buried porous zone, or a substrate with two layers that have been bonded to each other at a bonding interface by using a controlled bonding energy. Such techniques are described briefly below with reference to FIGS. 1 to 3 .
  • the source substrate 1 includes a weakened zone formed by using one of the techniques mentioned above.
  • the source substrate is brought into contact with a support substrate 2 to form a stack.
  • the layer to be transferred 11 is then detached from the remainder 12 of the source substrate along a zone of weakness 13 of the substrate.
  • the layer 11 may be detached by introducing mechanical stresses, such as tension and/or bending and/or shear stresses.
  • the mechanical stresses can be applied, for example, by a pulling rig, by a cutting blade applied to the side of the stack at the zone of weakness 13 , or by a jet of fluid or liquid, or gas applied laterally to the zone of weakness.
  • the mechanical stresses encourage the propagation of a crack along the zone of weakness 13 .
  • the two substrates 1 and 2 could be connected to each other by molecular bonding, without using an adhesive or an adhesive film. Transfer of the layer 11 is possible if the mechanical retention of layer 11 of the source substrate 1 is well below the mechanical retention of the layer 11 of the support substrate 2 . However, that condition may no longer be satisfied if adhesive is used since the exact volume of deposited adhesive is difficult to control. As can be seen in FIG. 2 , the adhesive 3 very often projects outwardly 30 beyond the respective side faces 10 , 20 (or sides) of substrates 1 , 2 to cover or mask the periphery of the zone of weakness 13 . It is very difficult to properly detach the layer 11 from the substrate 1 by applying mechanical stresses when the periphery of the zone of weakness 13 is covered.
  • the mechanical force required to detach the layer 11 is very high, and as shown in FIG. 3 , could result in a fracture of the substrates and in particular of the support substrate 2 along fracture lines 21 .
  • the fracture lines may not extend in the plane of the zone of weakness 13 , but can occur in a random and unpredictable manner throughout the thickness of the substrate 2 .
  • the methods according to the present invention overcome the disadvantages described above.
  • described herein are improved layer transfer methods that prevent excess material deposited at a bonding interface between a source substrate and a support substrate from covering the peripheral edge of the zone of weakness.
  • the invention generally relates to a method for fabricating a composite substrate which comprises forming a recess in a front face of at least one of a support substrate or a source substrate that includes a zone of weakness, the recess having a configuration that, in conjunction with the zone of weakness, assists in defining a transfer layer in the source substrate; depositing a bonding material onto at least one of the front face of the source substrate or the front face of the support substrate; bonding the front faces of the source and support substrates together in a manner to provide at least some of the bonding material in the recess; and detaching the transfer layer from the source substrate along the zone of weakness to form a composite substrate comprising the transfer layer, bonding material and the support substrate.
  • the transfer layer has a periphery and the configuration of the recess corresponds to the periphery of the transfer layer.
  • the transfer layer periphery and recess are circular.
  • the recess preferably comprises a groove or channel.
  • a preferred bonding material is at least one of an adhesive or an adhesive material.
  • the recess is formed in the front face of the support substrate, the bonding material is deposited onto the front face of the source substrate as a uniform layer, and the bonding material enters the recess when the source and support substrates are bonded together.
  • the recess is formed in the front face of the source substrate, the recess has a depth which extends to near the zone of weakness, and the bonding material is applied onto the front face of the source substrate.
  • the bonding material in the recess protects the peripheral edge of the transfer layer.
  • the recess is preferably configured to receive bonding material so that the bonding material does not extend past the zone of weakness on outer portions of the source substrate.
  • the recess may be formed through the entire thickness of the source substrate, the support substrate, or both.
  • the bonding material may be releasable, if desired, so that further modification can be made to the composite structure.
  • the recess can be formed by at least one of wet etching or dry etching or by mechanical machining.
  • the zone of weakness can be formed by any one of a variety of techniques, including implanting atomic species into the source substrate, providing a porous layer in the source substrate or by providing a releasable bonding interface in the source substrate.
  • implanting atomic species into the source substrate providing a porous layer in the source substrate or by providing a releasable bonding interface in the source substrate.
  • the recess can be formed prior to implanting the atomic species.
  • the invention also relates to a composite substrate comprising a transfer layer, bonding material and the support substrate, wherein the bonding material is present in a recess having a configuration that assists in defining the transfer layer and as a layer that bonds the transfer layer to the support substrate.
  • FIGS. 1 to 3 are cross-sectional diagrams illustrating the various steps of a prior art method of transferring a layer
  • FIGS. 4 to 7 are side, cross-sectional views of substrates illustrating the various steps of a first implementation of a layer transfer method according to the invention
  • FIGS. 8 to 11 are side, cross-sectional views of substrates illustrating the various steps of a variant of the first implementation of the method according to the invention shown in FIGS. 4 to 7 ;
  • FIG. 12 is a side, cross-sectional view of substrates illustrating a second implementation of the layer transfer method according to the invention.
  • the present methods pertain to transferring a layer of material from a source substrate onto a support substrate, to fabricate a composite substrate for applications in the fields of electronics, optics, or optoelectronics.
  • the source substrate includes a zone of weakness interposed between the layer of material to be transferred and the remainder of the source substrate. At least one recess for receiving excess additional material is formed in at least one of the two substrates, wherein the recess opens onto the “front face” of the substrate in which it is formed. Additional material is then deposited onto a front face of the source substrate, or onto the front face of the support substrate, or onto both front faces. Next, the front faces of the source substrate and the support substrate are bonded to each other. Lastly, the layer to be transferred is detached from the remainder of the source substrate along the zone of weakness.
  • the various described substrates are in the shape of a disk or a cylinder because that is the most common shape. However, it should be understood that the substrates could have other shapes.
  • FIG. 4 depicts a layer of material 41 that has been derived from a source substrate 4 .
  • the layer of material 41 is to be transferred onto a support substrate 5 during the fabrication of a composite substrate.
  • the resulting composite substrate may be used for applications in the fields of electronics, optics, and optoelectronics.
  • composite means that the substrate has a plurality of layers.
  • source substrate and support substrate can encompass both a singular substrate of a given material and a stack of layers of materials which may be of different types.
  • the source substrate 4 has a cylindrical side face 40 , a front face 44 , and an opposite, rear face 45 .
  • the source substrate 4 also has an internal zone of weakness 43 .
  • the term “zone of weakness” generally designates a weak zone of the source substrate 4 , and the two layers located on either side thereof will subsequently be detached along this zone of weakness 43 .
  • the zone of weakness 43 can be a zone obtained by implanting atomic species in the source substrate 4 .
  • the zone of weakness 43 is interposed between a layer of material 41 which will subsequently be transferred, and the remainder 42 of the source substrate.
  • the layer 41 and the remainder 42 are formed of the same material.
  • the layer to be transferred 41 extends between the front face 44 and the zone of weakness 43 .
  • implanting atomic species means any bombardment of atomic, molecular, or ionic species that is capable of introducing the species into a material at a certain depth below the bombarded surface 44 .
  • the maximum concentration of the species is at that depth, and the depth is determined by the implantation energy of the species.
  • Atomic species can be implanted in the source substrate 4 , for example, by using an ion beam implanter or a plasma immersion implanter.
  • Implantation is preferably accomplished by ionic bombardment, and the implanted ionic species is preferably hydrogen.
  • Other ionic species can advantageously be used alone or in combination with hydrogen, for example rare gases such as helium.
  • a zone of weakness 43 can also be formed by a porous layer obtained, for example, by using the method known under the trade name ELTRAN® registered by Canon, described in U.S. Pat. No. 6,100,166.
  • the source substrate 4 includes a stack of layers with at least one layer of material 41 obtained by epitaxial growth on a porous layer 43 .
  • the porous layer 43 rests on the remainder 42 of the source substrate, wherein the term “remainder” designates a single layer of material.
  • the zone of weakness 43 can also be a “releasable” bonding interface interposed between the layer 41 and the remainder 42 .
  • the remainder 42 may be formed of one or more layers.
  • the term “releasable” means that bonding is not permanent, so that the layer 41 can subsequently be disconnected from the remainder 42 .
  • a support substrate 5 has a cylindrical side face 50 , a front face 54 , and a rear face 55 .
  • the support substrate 5 is used to mechanically hold the assembly together.
  • the front faces 44 and 54 of, respectively, the source substrate 4 and the support substrate 5 are pressed against each other in the subsequent steps of the present method.
  • the present method includes, prior to depositing any material, forming at least one recess opening on the front face of at least one of the two substrates 4 and 5 (or both). As shown in the figures, this recess collects any excess material 6 that is deposited between the respective front faces 44 and 54 of the two substrates 4 and 5 .
  • the recess 56 is formed in the support substrate 5 and opens outwardly into the front face 54 .
  • the recess 56 can be of any shape, but may advantageously be in the shape of an annular groove located close to the periphery of the substrate 5 .
  • the dimensions of the recess 56 i.e., its width, length and depth, can be selected by the skilled person depending on the amount of excess volume of material 6 that it will be able to receive.
  • the recess 56 creates a buffer space that collects any excess material 6 . Different variable factors may contribute to the fact that the volume of additional material 6 cannot be accurately reproduced from one substrate to another.
  • the size of the recess 56 will thus generally correspond to about 10% to 20% of the total volume of additional material 6 .
  • the present technique makes it possible to introduce successive substrates having slightly varying diameters into the fabrication facility without having to modify the volume of material 6 that is deposited.
  • the recess 56 can be formed in a variety of ways and in particular by methods known as “cold methods”, which are those methods carried out at a temperature of less than about 400° C.
  • the recess can also be formed by “hot methods”, which are methods that heat the substrate to temperatures of more than 400° C., but with the heating being localized to the region in which etching occurs.
  • Cold methods include wet etching and dry etching.
  • Wet etching consists of applying a mask to the front face 54 of the support substrate 5 .
  • the mask may be obtained by photolithography and includes the pattern of the recess 56 which is to be reproduced.
  • the mask can be produced using a photosensitive resin, a layer of silicon dioxide (SiO 2 ), or a layer of silicon nitride (Si 3 N 4 ).
  • the prepared substrate is then immersed in an etching solution having a suitable chemical solution kept at a temperature of close to 70° C., while the rear face 55 is protected from the solution. This etching solution selectively attacks the unprotected portion of the front face 54 and etches the recess 56 .
  • the etching solution contacts the substrate 5 for a predetermined duration which determines the etching depth.
  • a mask can be formed from SiO 2 or Si 3 N 4 to place on a layer of silicon, and then either potassium hydroxide (KOH) or tetramethyl hydroxylamine (TMAH) can be used to etch the silicon. These two chemical solutions exhibit very great selectivity between silicon and SiO 2 or Si 3 N 4 . Following etching, the mask must be removed. It is possible to use a solvent when the mask is based on a resin, for example, or to use a solution of hydrofluoric acid (HF) for a SiO 2 mask, or to use phosphoric acid (H 3 PO 4 ) at 180° C. for a Si 3 N 4 mask.
  • HF hydrofluoric acid
  • H 3 PO 4 phosphoric acid
  • Dry etching may also be carried out through a mask applied to the front face 54 of the substrate 5 .
  • the mask can be produced as described above for wet etching. Dry etching could then be accomplished by ionic bombardment, which combines the ballistic action of ions with their chemical action.
  • RIE reactive ion etching
  • the chemical compounds used for the bombardment depend strongly on the chemical nature of the layer to be etched.
  • silicon may be etched with sulfur hexafluoride SF 6
  • silicon carbide may be etched with a mixture of sulfur hexafluoride and oxygen (SF 6 /O 2 )
  • silicon oxide may be etched with a mixture of sulfur hexafluoride and oxygen (SF 6 /O 2 ) or with a mixture of trifluoromethane and sulfur hexafluoride (CHF 3 /SF 6 )
  • silicon nitride can be etched using a trifluoromethane/oxygen/sulfur hexafluoride mixture (CHF 3 /O 2 /SF 6 ).
  • Etching can vary as a function of different parameters, such as an applied voltage, or the pressure inside the vessel in which the particular etching method is used. In contrast to wet etching, it is not necessary to protect the rear face of the substrate prior to etching. Such a technique is known as monoface etching. The mask is then removed as described above.
  • Hot methods may include mechanical machining, for example, by using a saw or a laser.
  • the advantage of this type of technique is that there is no need to protect either the front face or the rear face of the substrate.
  • Mechanical machining can be carried out using a saw, made of, for example, silicon carbide, which can produce grooves of about 100 micrometers ( ⁇ m).
  • a laser beam could also be used to heat the material until it melts.
  • Such a technique allows machining to be automated and allows a series of cut segments to be formed.
  • the molten material often tends to re-deposit itself on the sides of the structure, forming beads which then have to be removed by chemical attack. Thus, any active zones on the substrate should be protected.
  • a material 6 is deposited either on the front face 44 of the source substrate 4 (as shown in FIG. 5 ), or on the front face 54 of the support substrate 5 , or on both front faces. In the last two cases, material 6 is deposited only after the recess 56 has been formed.
  • the bonding material 6 is preferably an adhesive (for example an epoxy adhesive or a cyanoacrylate adhesive) or an adhesive compound, such as a liquid or solid compound.
  • the material 6 can be applied to or deposited onto substrates 4 or 5 to allow them to adhere to each other.
  • suitable adhesive compounds include polyimides, wax or a product known as “SOG” (spin on glass), which is a liquid oxide deposited by a centrifuge.
  • the two substrates are then pressed against each other so that the layer of material 6 is between the front faces 44 and 54 such that the two substrates 4 and 5 are bonded to each other. Any excess material 6 penetrates into the recess 56 , which prevents excess material 6 from projecting outwardly in the direction of the side faces 40 and 50 . Thus, excess material does not cover the peripheral edge of the zone of weakness 43 .
  • a mechanical stress is applied so that the layer to be transferred 41 detaches from the remainder 42 of the source substrate 4 along the zone of weakness 43 .
  • the stress may be a tension and/or a bending and/or a shear stress, for example.
  • the stress may be applied, for example, by a pulling rig, by a blade such as a guillotine contacting the side face 40 of the source substrate 4 at the zone of weakness 43 , or by a jet of fluid (liquid or gas) applied laterally to the zone of weakness 43 .
  • Detachment takes place horizontally along the zone of weakness 43 and vertically, that is perpendicular to, or substantially perpendicular to, the outer limit of the layer of material 6 .
  • FIGS. 8 to 11 A second variant of the present method is illustrated in FIGS. 8 to 11 .
  • a recess 46 for receiving any excess of material 6 is formed on the front face 44 of the source substrate 4 . Apart from the position of the recess, the successive steps of the method shown in these figures are similar to those of FIGS. 4 to 7 , and thus their description will not be repeated here in detail.
  • a laser should not be used to form the recess 46 since metallic layers, for example, or a weakened layer obtained by implanting atomic species, may be incapable of tolerating the localized heating caused by the laser.
  • the recess 46 should be formed prior to the atomic species implantation step. This precaution will prevent the localized elevated temperature caused by the machining from causing the layer 41 to detach prematurely from the remainder 42 of substrate 4 .
  • etching should be carried out in the cut paths (the inactive zones on the front face 44 ) to limit the loss of surface area.
  • the depth of the recess 46 is at least equal to the depth at which the zone of weakness 43 is located (which corresponds to the thickness of the layer to be transferred 41 ).
  • FIG. 12 shows a second embodiment that includes recesses for receiving an excess amount of material 6 .
  • the source substrate 4 and the support substrate 5 are shown bonded together.
  • the recess formed in one substrate communicates with the rear face thereof via a channel.
  • a first variant of the channel has been arbitrarily selected to be shown on the support substrate 5
  • a second variant is shown on the source substrate 4 . It should be understood that the channels could be reversed, and that other configurations are contemplated.
  • a recess 56 communicates with the rear face 55 of substrate 5 via a channel 57 .
  • the channel 57 can have any shape and connects the recess of the front face 54 to the rear face 55 .
  • the recess is the channel 47 that passes through the source substrate 4 from one side to the other.
  • the channels 47 and 57 are formed using the same techniques used for forming the recesses 46 and 56 , and preferably use wet or dry etching techniques, which result in deep etched channels.
  • the channels 47 or 57 allows the excess of material 6 to be evacuated from the rear faces 45 and 55 of the substrates. Since the channels are open to the outside, such a configuration allows greater variation in the volume of applied material 6 .
  • substrates 4 and 5 are suitable for substrates 4 and 5 of a variety of materials, in particular semiconductors that can be used in the fields of optics, electronics, and optoelectronics.
  • suitable substrate materials include, but are not limited to, silicon, germanium, silicon carbide (SiC), or III-V materials, which are compounds having at least one element found in column IIIa of the periodic table and the other element found in column Va, for example gallium arsenide (GaAs), or indium phosphide (InP).

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FR0209018 2002-07-17
FR0209018A FR2842647B1 (fr) 2002-07-17 2002-07-17 Procede de transfert de couche

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JP (1) JP4740590B2 (de)
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AU (1) AU2003250992A1 (de)
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US20080248629A1 (en) * 2007-04-06 2008-10-09 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
US20110230034A1 (en) * 2008-12-15 2011-09-22 S.O.I. Tec Silicon On Insulator Technologies Method of thinning a structure
US20110315664A1 (en) * 2010-06-23 2011-12-29 Michel Bruel Method for treating a part made from a decomposable semiconductor material
US9481566B2 (en) 2012-07-31 2016-11-01 Soitec Methods of forming semiconductor structures including MEMS devices and integrated circuits on opposing sides of substrates, and related structures and devices
US9847243B2 (en) 2009-08-27 2017-12-19 Corning Incorporated Debonding a glass substrate from carrier using ultrasonic wave

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JP5939881B2 (ja) * 2012-05-02 2016-06-22 株式会社ディスコ 研削方法
DE102014102917B4 (de) * 2013-03-05 2024-01-18 Flextronics Ap, Llc Bauteil mit Abzugsstrecken, Halbleiterbaugruppe mit Druckentlastungsstruktur und Verfahren zur Verhinderung von Druckaufbau in einer Halbleiterverpackung

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US7439160B2 (en) * 2004-03-01 2008-10-21 S.O.I.Tec Silicon On Insulator Technologies Methods for producing a semiconductor entity
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US20110230034A1 (en) * 2008-12-15 2011-09-22 S.O.I. Tec Silicon On Insulator Technologies Method of thinning a structure
US8357589B2 (en) 2008-12-15 2013-01-22 Soitec Method of thinning a structure
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US9847243B2 (en) 2009-08-27 2017-12-19 Corning Incorporated Debonding a glass substrate from carrier using ultrasonic wave
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WO2004008526A1 (en) 2004-01-22
AU2003250992A8 (en) 2004-02-02
TWI286816B (en) 2007-09-11
EP1543553A1 (de) 2005-06-22
FR2842647A1 (fr) 2004-01-23
JP4740590B2 (ja) 2011-08-03
AU2003250992A1 (en) 2004-02-02
ATE498201T1 (de) 2011-02-15
DE60335995D1 (de) 2011-03-24
US20040082147A1 (en) 2004-04-29
EP1543553B1 (de) 2011-02-09
JP2005533374A (ja) 2005-11-04
FR2842647B1 (fr) 2004-09-17
MY135493A (en) 2008-04-30
TW200416943A (en) 2004-09-01

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