ATE498201T1 - Schichtentransferverfahren - Google Patents

Schichtentransferverfahren

Info

Publication number
ATE498201T1
ATE498201T1 AT03763890T AT03763890T ATE498201T1 AT E498201 T1 ATE498201 T1 AT E498201T1 AT 03763890 T AT03763890 T AT 03763890T AT 03763890 T AT03763890 T AT 03763890T AT E498201 T1 ATE498201 T1 AT E498201T1
Authority
AT
Austria
Prior art keywords
substrate
source
support
recess
front face
Prior art date
Application number
AT03763890T
Other languages
English (en)
Inventor
Bernard Aspar
Severine Bressot
Olivier Rayssac
Original Assignee
Soitec Silicon On Insulator
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator, Commissariat Energie Atomique filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE498201T1 publication Critical patent/ATE498201T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1924—Preparing SOI wafers with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Recrystallisation Techniques (AREA)
  • Laminated Bodies (AREA)
  • Medicinal Preparation (AREA)
  • Detergent Compositions (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
  • Medicines That Contain Protein Lipid Enzymes And Other Medicines (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Ropes Or Cables (AREA)
  • Separation By Low-Temperature Treatments (AREA)
  • Prostheses (AREA)
  • Weting (AREA)
  • Lining Or Joining Of Plastics Or The Like (AREA)
  • Electroluminescent Light Sources (AREA)
  • Element Separation (AREA)
AT03763890T 2002-07-17 2003-07-16 Schichtentransferverfahren ATE498201T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0209018A FR2842647B1 (fr) 2002-07-17 2002-07-17 Procede de transfert de couche
PCT/EP2003/007853 WO2004008526A1 (en) 2002-07-17 2003-07-16 A layer transfer method

Publications (1)

Publication Number Publication Date
ATE498201T1 true ATE498201T1 (de) 2011-02-15

Family

ID=29797483

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03763890T ATE498201T1 (de) 2002-07-17 2003-07-16 Schichtentransferverfahren

Country Status (10)

Country Link
US (1) US6913971B2 (de)
EP (1) EP1543553B1 (de)
JP (1) JP4740590B2 (de)
AT (1) ATE498201T1 (de)
AU (1) AU2003250992A1 (de)
DE (1) DE60335995D1 (de)
FR (1) FR2842647B1 (de)
MY (1) MY135493A (de)
TW (1) TWI286816B (de)
WO (1) WO2004008526A1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1571705A3 (de) * 2004-03-01 2006-01-04 S.O.I.Tec Silicon on Insulator Technologies Verfahren zur Herstellung einer Hableiterstruktur auf einem Substrat
US20080248629A1 (en) * 2007-04-06 2008-10-09 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate
FR2939962B1 (fr) * 2008-12-15 2011-03-18 Soitec Silicon On Insulator Procede d'amincissement d'une structure.
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
US9847243B2 (en) 2009-08-27 2017-12-19 Corning Incorporated Debonding a glass substrate from carrier using ultrasonic wave
US8932910B2 (en) * 2010-05-20 2015-01-13 Ev Group E. Thallner Gmbh Method for producing chip stacks, and a carrier for carrying out the method
FR2961948B1 (fr) * 2010-06-23 2012-08-03 Soitec Silicon On Insulator Procede de traitement d'une piece en materiau compose
JP5939881B2 (ja) * 2012-05-02 2016-06-22 株式会社ディスコ 研削方法
CN104507853B (zh) 2012-07-31 2016-11-23 索泰克公司 形成半导体设备的方法
DE102014102917B4 (de) * 2013-03-05 2024-01-18 Flextronics Ap, Llc Bauteil mit Abzugsstrecken, Halbleiterbaugruppe mit Druckentlastungsstruktur und Verfahren zur Verhinderung von Druckaufbau in einer Halbleiterverpackung

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61208842A (ja) * 1985-03-14 1986-09-17 Nippon Telegr & Teleph Corp <Ntt> 半導体ウエハ支持基板
JPH0521480A (ja) * 1991-07-12 1993-01-29 Dainippon Printing Co Ltd リードフレーム
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JPH0737768A (ja) * 1992-11-26 1995-02-07 Sumitomo Electric Ind Ltd 半導体ウェハの補強方法及び補強された半導体ウェハ
JPH07335817A (ja) * 1994-06-10 1995-12-22 Dainippon Printing Co Ltd リードフレーム部材
JPH0963912A (ja) * 1995-08-18 1997-03-07 Hoya Corp 貼り合わせ基板製造方法
JPH09232199A (ja) * 1996-02-27 1997-09-05 Victor Co Of Japan Ltd 薄膜プロセス用複合ウェハ基板
SG67458A1 (en) * 1996-12-18 1999-09-21 Canon Kk Process for producing semiconductor article
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
US6406336B1 (en) 1998-01-20 2002-06-18 Fci Americas Technology, Inc. Contact with anti-skiving feature
US6054370A (en) * 1998-06-30 2000-04-25 Intel Corporation Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer
FR2781925B1 (fr) * 1998-07-30 2001-11-23 Commissariat Energie Atomique Transfert selectif d'elements d'un support vers un autre support
JP2000223683A (ja) * 1999-02-02 2000-08-11 Canon Inc 複合部材及びその分離方法、貼り合わせ基板及びその分離方法、移設層の移設方法、並びにｓｏｉ基板の製造方法
US6236103B1 (en) * 1999-03-31 2001-05-22 International Business Machines Corp. Integrated high-performance decoupling capacitor and heat sink
US6406636B1 (en) * 1999-06-02 2002-06-18 Megasense, Inc. Methods for wafer to wafer bonding using microstructures
JP2001007362A (ja) 1999-06-17 2001-01-12 Canon Inc 半導体基材および太陽電池の製造方法
JP2001196566A (ja) * 2000-01-07 2001-07-19 Sony Corp 半導体基板およびその製造方法
JP4361658B2 (ja) * 2000-02-14 2009-11-11 富士通マイクロエレクトロニクス株式会社 実装基板及び実装方法
JP2001296650A (ja) * 2000-04-17 2001-10-26 Nec Corp レチクル
FR2811807B1 (fr) 2000-07-12 2003-07-04 Commissariat Energie Atomique Procede de decoupage d'un bloc de materiau et de formation d'un film mince
EP1364398A4 (de) * 2001-01-02 2011-11-30 Draper Lab Charles S Verfahren zur mikroherstellung von strukturen unter verwendung von silizium-auf-isolator-material
FR2837620B1 (fr) * 2002-03-25 2005-04-29 Commissariat Energie Atomique Procede de transfert d'elements de substrat a substrat

Also Published As

Publication number Publication date
TW200416943A (en) 2004-09-01
US20040082147A1 (en) 2004-04-29
EP1543553A1 (de) 2005-06-22
FR2842647B1 (fr) 2004-09-17
AU2003250992A1 (en) 2004-02-02
DE60335995D1 (de) 2011-03-24
WO2004008526A1 (en) 2004-01-22
JP4740590B2 (ja) 2011-08-03
JP2005533374A (ja) 2005-11-04
EP1543553B1 (de) 2011-02-09
MY135493A (en) 2008-04-30
TWI286816B (en) 2007-09-11
FR2842647A1 (fr) 2004-01-23
AU2003250992A8 (en) 2004-02-02
US6913971B2 (en) 2005-07-05

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties