US7492209B2 - High-frequency switching device with reduced harmonics - Google Patents

High-frequency switching device with reduced harmonics Download PDF

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US7492209B2
US7492209B2 US11/492,504 US49250406A US7492209B2 US 7492209 B2 US7492209 B2 US 7492209B2 US 49250406 A US49250406 A US 49250406A US 7492209 B2 US7492209 B2 US 7492209B2
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gate
coupled
fet
switching device
drain
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US20070243849A1 (en
Inventor
Dima Prikhodko
Sergey Nabokin
Steven C. Sprinkle
Mikhail Shirokov
Gene A. Tkachenko
Jason Chiesa
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Skyworks Solutions Inc
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Skyworks Solutions Inc
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Assigned to SKYWORKS SOLUTIONS, INC. reassignment SKYWORKS SOLUTIONS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHIESA, JASON, NABOKIN, SERGEY, PRIKHODKO, DIMA, SHIROKOV, MIKHAIL, SPRINKLE, STEVEN C., TKACHENKO, GENE A.
Priority to PCT/US2007/008635 priority patent/WO2007123822A2/en
Priority to EP07755045.7A priority patent/EP2008362B1/de
Priority to KR1020087028031A priority patent/KR101409122B1/ko
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H45/00—Details of relays
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P1/00—Auxiliary devices
    • H01P1/10—Auxiliary devices for switching or interrupting
    • H01P1/15—Auxiliary devices for switching or interrupting by semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/002—Switching arrangements with several input- or output terminals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/10—Modifications for increasing the maximum permissible switched voltage
    • H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors

Definitions

  • the present invention is generally in the field of electrical circuits. More specifically, the invention is in the field of high-frequency switching circuits.
  • High-frequency switching devices such as high-frequency switching devices having multiple inputs and a shared output
  • a high-frequency switching device can be used in a cellular handset operating in a system using a global system for mobile communications (GSM) communications standard to enable the cellular handset to operate either at a low band frequency of 900.0 MHz or a high band frequency of 1800.0 MHz by selectively coupling a corresponding input to the shared output.
  • GSM global system for mobile communications
  • a conventional high-frequency switching device can include two or more switching blocks, where each switching block includes a number of field effect transistors (FETs) coupled together, and where each switching block is coupled to a separate input and a shared output.
  • the gates of the FETs in each switching block can be coupled to a control voltage input, which can provide a high control voltage to turn on the switching block and a low control voltage to turn off the switching block.
  • the number of FETs in each switching block can be increased.
  • increasing the number of FETs in each switching block undesirably increases the semiconductor die area consumed by the switching device.
  • a first capacitor can be coupled between the gate and drain of the FET in each switching block that is coupled to the shared output of the switching device and a second capacitor can be coupled between the gate and source of the FET in each switching block that is coupled to an input of the switching device.
  • the present invention is directed to a high-frequency switching device with reduced harmonics.
  • the present invention overcomes the need in the art for a high-frequency switching device that provides increased power handling capability and reduced harmonic output.
  • a low harmonic switching device includes a first switching block including a first multi-gate FET, where the first switching block is coupled to a first input and a shared output of the low harmonic switching device.
  • a first capacitor is coupled between a first gate and a source of the first multi-gate FET and a second capacitor is coupled between a second gate and a drain of the first multi-gate FET so as to cause a reduction in a harmonic amplitude in the shared output.
  • the first multi-gate FET may include a third gate situated between the first gate and the second gate.
  • a first resistor can couple the source of the first multi-gate FET to the drain of the first multi-gate FET.
  • a first control voltage input can be coupled to the first gate and the second gate of the first multi-gate FET.
  • a second resistor can couple the first gate of the first multi-gate FET to the control voltage and a third resistor can couple the second gate of the first multi-gate FET to the first control voltage.
  • the first switching block can further include a second multi-gate FET, where a source of the second multi-gate FET is coupled to the drain of the first multi-gate FET and a drain of the second multi-gate FET is coupled to the shared output.
  • a third capacitor can be coupled between a first gate and said drain of the second multi-gate FET and a fourth capacitor can be coupled between a second gate and the source of the second multi-gate FET.
  • the low harmonic switching device further includes a second switching block, where the second switching block is coupled to a second input and the shared output of the low harmonic switching device.
  • the first input can be coupled to the shared output when the first control voltage turns the first switching block on and a second control voltage turns the second switching block off and the second input can be coupled to the shared output when the second control voltage turns the second switching block on and the first control voltage turns the first switching block off.
  • FIG. 1 illustrates a diagram of an exemplary switching device.
  • FIG. 2 illustrates a diagram of an exemplary switching device in accordance with one embodiment of the present invention.
  • FIG. 3 is a graph showing a fundamental/third harmonic difference curve for an exemplary switching device in accordance with one embodiment of the present invention.
  • FIG. 4 illustrates a diagram of an exemplary switching device in accordance with another embodiment of the present invention.
  • FIG. 5 is a graph showing a fundamental/third harmonic difference curve for an exemplary switching device in accordance with another embodiment of the present invention.
  • the present invention is directed to a high-frequency switching device with reduced harmonics.
  • the following description contains specific information pertaining to the implementation of the present invention.
  • One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order not to obscure the invention. The specific details not described in the present application are within the knowledge of a person of ordinary skill in the art.
  • FIG. 1 shows a schematic diagram of an exemplary conventional switching device.
  • Conventional switching device 100 includes switching block 102 and 104 , which are output-coupled at node 106 .
  • Conventional switching device 100 can be a high frequency switching device, such as an RF switching device, and can be utilized in wireless communications devices that use GSM or wideband code-division multiple access (W-CDMA) communications standards, for example.
  • GSM Global System for Mobile communications
  • W-CDMA wideband code-division multiple access
  • switching circuit section 102 includes FETs 108 a , 108 b , 108 c , 108 d , 108 e , and 108 f (hereinafter “FETs 108 a through 108 f ”), which are coupled together in a series configuration.
  • FETs 108 a through 108 f can be an N-channel FET (NFET), for example.
  • Switching circuit section 102 also includes capacitor 110 , which is coupled between gate and drain terminals of FET 108 f , and capacitor 112 , which is coupled between gate and source terminals of FET 108 a . Also shown in FIG.
  • signal input 114 which is a high-frequency signal input, is coupled to node 116 and signal output 118 , which is a high-frequency signal output, is coupled to node 106 .
  • Signal output 118 can be coupled to a load, such as an antenna, for example.
  • control voltage input 120 is coupled to the gates of FETs 108 a through 108 f at node 122 .
  • switching circuit section 104 includes FETs 122 a , 122 b , 122 c , 122 d , 122 e , and 122 f (hereinafter “FETs 122 a through 122 f ”), which are also coupled together in a series configuration.
  • FETs 122 a through 122 f can be an NFET, for example.
  • Switching circuit section 104 also includes capacitor 124 , which is coupled between gate and drain terminals of FET 122 f , and capacitor 126 , which is coupled between gate and source terminals of FET 122 a .
  • signal input 128 which is a high-frequency signal input, is coupled to node 130 and control voltage input 132 is coupled to the gates of FETs 108 a through 108 f at node 134 .
  • switching circuit section 102 can be turned on by applying a high voltage, which can be between 2.4 and 5.0 volts, for example, at control voltage input 120 and switching circuit section 104 can be turned off by applying a low voltage, which can be approximately 0.0 volts, for example, at control voltage input 132 and vice versa.
  • a high voltage which can be between 2.4 and 5.0 volts, for example, at control voltage input 120
  • switching circuit section 104 can be turned off by applying a low voltage, which can be approximately 0.0 volts, for example, at control voltage input 132 and vice versa.
  • switching circuit section 102 When switching circuit section 102 is turned on and switching circuit section 104 is turned off, for example, an RF signal, such as a 900.0 MHz low band GSM signal, at signal input 114 is allowed to pass through FETs 108 a through 108 f to signal output 118 and another RF signal, such as an 1800.0 MHz high band GSM signal, at signal input 128 is prevented from passing through FETs 122 a through 122 f to signal output 118 .
  • an RF signal such as a 900.0 MHz low band GSM signal
  • an RF signal at signal output 118 provides a high output voltage at node 106 , which is divided between gate/drain and gate/source junctions of each of FETs 122 a through 122 f .
  • FETs 122 a through 122 f in switching circuit section 104 are turned off when switching circuit section 102 is turned on, if the output voltage at node 106 is too high, one or more of FETs 122 a through 122 f may turn on, which can cause an undesirable increase in amplitude of the third harmonic of the RF signal at signal output 118 .
  • Capacitors 124 and 126 are utilized to reduce third harmonic amplitude by reducing the voltage swing at the gate/drain junction of FET 122 f and the gate/source junction of FET 122 a , respectively.
  • capacitors 110 and 112 are utilized to reduce third harmonic amplitude by reducing the voltage swing at the gate/drain junction of FET 108 f and the gate/source junction of FET 108 a , respectively.
  • third harmonic amplitude provided by conventional switching device 100 is undesirably high at low control voltages.
  • third harmonic amplitude provided by conventional switching device 100 increases significantly for a control voltage below approximately 3.0 volts.
  • FIG. 2 shows a schematic diagram of an exemplary switching device in accordance with one embodiment of the present invention.
  • Low harmonic low harmonic switching device 200 includes switching block 202 and 204 .
  • Low harmonic switching device 200 can be a high frequency switching device, such as an RF switching device. In other embodiments, low harmonic switching device 200 can include more than two switching blocks.
  • Low harmonic switching device 200 also includes signal inputs 262 and 266 , signal output 270 , which is also referred to as a “shared output” in the present application, and control voltage inputs 274 and 278 .
  • Low harmonic switching device 200 can be utilized in wireless communications devices that use GSM or W-CDMA communications standards, for example.
  • Switching circuit section 202 includes FETs 206 and 208 , capacitors 210 , 212 , 214 , and 216 , and resistors 218 , 220 , 222 , 224 , 226 , 228 , 230 , and 232 .
  • Switching circuit section 204 includes FETs 234 and 236 , capacitors 238 , 240 , 242 , and 244 , and resistors 246 , 248 , 250 , 252 , 254 , 256 , 258 , and 260 .
  • signal input 262 which can be a high-frequency signal input, such as an RF signal input, is coupled to switching circuit section 202 at node 264
  • signal input 266 which can also be a high-frequency signal input, such as an RF signal input
  • signal output 270 which can be a high-frequency signal output, such as an RF signal output, is coupled to the signal outputs of switching block 202 and 204 at node 272
  • Signal output 270 can be coupled to a load (not shown in FIG. 2 ), such as an antenna, for example. Also shown in FIG.
  • control voltage inputs 274 and 278 are coupled to nodes 276 and 280 of switching block 202 and 204 , respectively.
  • Control voltage inputs 274 and 278 can receive a high control voltage (VH), which can be between 2.4 volts and 5.0 volts, for example, to turn on respective switching block 202 and 204 .
  • Control voltage inputs 274 and 278 can also receive a low control voltage (VL), which can be approximately 0.0 volts, for example, to turn off respective switch circuit sections 202 and 204 .
  • VH high control voltage
  • VL low control voltage
  • the source terminal of FET 206 is coupled to first terminals of resistor 220 and capacitor 216 at node 264 and the drain terminal of FET 206 is coupled to a second terminal of resistor 220 and a first terminal of capacitor 214 at node 282 .
  • resistor 220 might have a resistance of at least 10.0 kilo-ohms (kOhms). Also shown in FIG.
  • FET 206 can be a multi-gate FET, such as a multi-gate NFET. In the present embodiment, FET 206 can have three gates. In other embodiments, FET 206 can have two gates or more than three gates.
  • Capacitors 214 and 216 might each have a capacitance of at least 2.0 picofarads (pF), for example. Also shown in FIG.
  • resistors 228 , 230 , and 232 are coupled to control voltage input 274 at node 276 .
  • resistors 228 , 230 , and 232 might each have a resistance of between 5.0 kOhms and 10.0 kOhms.
  • the source terminal of FET 208 is coupled to first terminals of resistor 218 and capacitor 212 at node 282 and the drain terminal of FET 206 is coupled to a second terminal of resistor 218 and a first terminal of capacitor 210 at node 272 .
  • Resistor 218 can have a resistance that is substantially equal to the resistance of resistor 220 . Also shown in FIG.
  • FET 208 can be a multi-gate FET, such as a multi-gate NFET. In the present embodiment, FET 208 can have three gates. In other embodiments, FET 208 can have two gates or more than three gates.
  • Capacitors 210 and 212 can have a capacitance that is substantially equal to the capacitance of capacitors 214 and 216 , respectively. Also shown in FIG.
  • resistors 222 , 224 , and 226 are coupled to control voltage input 274 at node 276 .
  • Resistors 222 , 224 , and 226 can have a resistance that is substantially equal to the resistance of resistors 228 , 230 , and 232 , respectively.
  • the source terminal of FET 234 is coupled to first terminals of resistor 248 and capacitor 244 at node 268 and the drain terminal of FET 234 is coupled to a second terminal of resistor 248 and a first terminal of capacitor 242 at node 284 .
  • Resistor 248 can have a resistance that is substantially equal to the resistance of resistor 220 . Also shown in FIG.
  • FET 234 can be a multi-gate FET, such as a multi-gate NFET. In the present embodiment, FET 234 can have three gates. In other embodiments, FET 234 can have two gates or more than three gates.
  • Capacitors 242 and 244 can have a capacitance that is substantially equal to the capacitance of capacitors 214 and 216 , respectively. Also shown in FIG.
  • resistors 256 , 258 , and 260 are coupled to control voltage input 278 at node 280 .
  • Resistors 256 , 258 , and 260 can have a resistance that is substantially equal to the resistance of resistors 228 , 230 , and 232 , respectively.
  • the source terminal of FET 236 is coupled to first terminals of resistor 246 and capacitor 240 at node 284 and the drain terminal of FET 236 is coupled to a second terminal of resistor 246 and a first terminal of capacitor 238 at node 272 .
  • Resistor 246 can have a resistance that is substantially equal to the resistance of resistor 248 .
  • gate terminal G 1 of FET 236 is coupled to a second terminal of capacitor 238 and a first terminal of resistor 250
  • gate terminal G 2 of FET 236 is coupled to a first terminal of resistor 252
  • gate terminal G 3 of FET 236 is coupled to a first terminal of resistor 254 and a second terminal of capacitor 240 .
  • FET 236 can be a multi-gate FET, such as a multi-gate NFET. In the present embodiment, FET 236 can have three gates. In other embodiments, FET 236 can have two gates or more than three gates.
  • Capacitors 238 and 240 can have a capacitance that is substantially equal to the capacitance of capacitors 242 and 244 , respectively. Also shown in FIG. 2 , the second terminals of resistors 222 , 224 , and 226 are coupled to control voltage input 274 at node 276 .
  • Resistors 250 , 252 , and 254 can have a resistance that is substantially equal to the resistance of resistors 256 , 258 , and 260 , respectively.
  • Switching circuit section 202 can be turned on by applying VH (i.e. a high control voltage) to control voltage input 274 , which turns on FETs 206 and 208 , and switching circuit section 204 can be turned off by applying VL (i.e. a low control voltage) to control voltage input 278 , which turns off FETs 234 and 236 , and vice versa.
  • VH i.e. a high control voltage
  • VL i.e. a low control voltage
  • signal input 262 is coupled to signal output 270 such that an RF signal (e.g. a 900.0 MHz low band GSM signal) at signal input 262 is allowed to pass through FETs 206 and 208 to signal output 270 .
  • signal input 266 is de-coupled from signal output 270 such that another RF signal (e.g. an 1800.0 MHz high band GSM signal) at signal input 266 is prevented from passing through FETs 234 and 236 to signal output 270 .
  • an RF signal at signal output 270 provides a peak RF voltage (Vrf) at node 272 , which is equally divided between gate/drain and gate/source junctions of each of FETs 234 and 236 .
  • Vrf peak RF voltage
  • the RF signal at signal output 270 provides Vrf at node 272 , which is equally divided between gate/drain and gate/source junctions of each of FETs 206 and 208 .
  • a high Vrf can cause the voltage at the gate/drain and gate/source junctions of FETs 234 and 236 to increase such that FET 234 and/or FET 236 turns on, which can cause an undesirable increase in harmonic levels (i.e. amplitudes), such as the amplitude of the third harmonic.
  • capacitors 210 , 214 , 238 , and 242 which are coupled between gate (G 1 ) and drain of respective FETs 208 , 206 , 236 , and 234
  • capacitors 212 , 216 , 240 , and 244 which are coupled between gate (G 3 ) and source of respective FETs 208 , 206 , 236 and 234
  • G 3 gate
  • FETs 208 , 206 , 236 and 234 are provided to attenuate the voltage at gate/drain and gate/source junctions of FETs 208 , 206 , 236 and 234 .
  • switching circuit section 202 when switching circuit section 202 is turned off, the voltage at gate/drain and gate/source junctions of FETs 206 and 208 is attenuated, which reduces the amplitude of third harmonics generated by switching circuit 202 .
  • switching circuit section 204 when switching circuit section 204 is turned off, the voltage at gate/drain and gate/source junctions of FETs 234 and 236 is attenuated, which reduces the amplitude of third harmonics generated by switching circuit 204 .
  • the embodiment of the invention in FIG. 2 advantageously achieves a high-frequency switching device having reduced third harmonic amplitude compared to conventional switching device 100 in FIG. 1 .
  • the third harmonic amplitude begins to increase at a control voltage of approximately 2.8 volts in high-frequency low harmonic switching device 200 in FIG. 2 .
  • the third harmonic amplitude begins to significantly increase at a higher control voltage of approximately 3.0 volts in conventional switching device 100 in FIG. 1 .
  • the embodiment of the invention in FIG. 2 can advantageously operate effectively at a lower control voltage compared to conventional switching device 100 .
  • the embodiment of the invention in FIG. 2 also provides a high-frequency switching device that has increased power handling capability compared to the conventional high-frequency switching device in FIG. 1 . Furthermore, by utilizing multi-gate FETs in place of single gate FETs, the embodiment of the invention in FIG. 2 provides a high-frequency switching device that advantageously occupies a smaller area on a semiconductor die compared to the conventional high-frequency switching device in FIG. 1 .
  • FIG. 3 shows exemplary graph 300 including an exemplary fundamental/third harmonic difference curve in accordance with one embodiment of the present invention.
  • Graph 300 includes VH axis 302 , dBc axis 304 , and fundamental/third harmonic difference curves 306 and 308 .
  • VH axis 302 corresponds to an exemplary range of control voltages are can be utilized to turn on switching block of conventional switching device 100 in FIG. 1 and low harmonic switching device 200 in FIG. 2
  • dBc axis 304 corresponds to an exemplary range of differences between a fundamental frequency of an RF input signal (e.g. a GSM input signal at an input power of approximately 35.0 dBm) and a third harmonic of the fundamental frequency in dBm).
  • a fundamental frequency of an RF input signal e.g. a GSM input signal at an input power of approximately 35.0 dBm
  • a third harmonic of the fundamental frequency in dBm e.g. a GSM input signal at an input power of
  • Fundamental/third harmonic difference curve 306 corresponds to an exemplary difference between a fundamental frequency and a third harmonic as measured in dBm vs. VH for an embodiment of the invention's switching device in FIG. 2 and fundamental/third harmonic difference curve 308 corresponds to an exemplary difference between the fundamental frequency and the third harmonic as measured in dBm vs. VH for conventional switching circuit 100 in FIG. 1 .
  • fundamental/third harmonic difference curve 308 begins to roll off (i.e. begins to significantly decrease) at approximately 3.0 volts, while fundamental/third harmonic difference curve 306 begins to roll off at approximately 2.8 volts.
  • third harmonic amplitude begins to increase at a lower control voltage for low harmonic switching device 200 in FIG. 2 compared to conventional switching device 100 in FIG. 1 .
  • the embodiment of the present invention in FIG. 2 achieves a switching device that can effectively operate at a lower control voltage with lower third harmonic amplitude compared to conventional switching device 100 in FIG. 1 .
  • FIG. 4 shows a schematic diagram of an exemplary switching device in accordance with one embodiment of the present invention.
  • Low harmonic switching device 400 includes switching block 403 and 405 .
  • Low harmonic switching device 400 can be a high frequency switching device, such as an RF switching device. In other embodiments, low harmonic switching device 400 can include more than two switching block.
  • Low harmonic switching device 400 also includes signal inputs 462 and 466 , signal output 470 , which is also referred to as a “shared output” in the present application, and control voltage inputs 474 and 478 .
  • Low harmonic switching device 400 can be utilized in wireless communications devices that use GSM or W-CDMA communications standards, for example. However, low harmonic switching device 400 can also be utilized in other high frequency switching applications where reduced third harmonic level and increased power handling capability is desired.
  • Switching circuit section 403 includes FETs 406 and 408 , capacitors 410 , 412 , 414 , and 416 , and resistors 418 , 420 , 422 , 424 , 426 , 428 , 430 , 432 , 485 , 486 , and 488 .
  • Switching circuit 405 includes FETs 434 and 436 , capacitors 438 , 440 , 442 , and 444 , and resistors 446 , 448 , 450 , 452 , 454 , 456 , 458 , 460 , 488 , 489 , and 490 .
  • signal input 462 which can be a high-frequency signal input, such as an RF signal input
  • signal input 466 which can also be a high-frequency signal input, such as an RF signal input
  • signal output 470 which can be a high-frequency signal output, such as an RF signal output
  • Signal output 470 can be coupled to a load (not shown in FIG. 4 ), such as an antenna, for example. Also shown in FIG.
  • control voltage inputs 474 and 478 are coupled to nodes 476 and 480 of switching block 402 and 404 , respectively.
  • Control voltage inputs 474 and 478 can receive a high control voltage (VH), which can be between 2.4 volts and 5.0 volts, for example, to turn on respective switching block 403 and 405 .
  • Control voltage inputs 474 and 478 can also receive a low control voltage (VL), which can be approximately 0.0 volts, for example, to turn off respective switch circuit sections 403 and 405 .
  • VH high control voltage
  • VL low control voltage
  • reference voltage 492 is coupled to first terminals of resistors 485 , 486 , 487 , 488 , 489 , and 490 at node 494 .
  • Reference voltage 492 is a DC voltage and is substantially equal to VH (i.e. the high control voltage utilized to turn on switching block 403 and 405 ). In the embodiment of the invention in FIG. 4 , reference voltage 492 is utilized to tie the source and drains of FETs 406 , 408 , 434 , and 436 to a common DC voltage (i.e. VH).
  • the source terminal of FET 406 is coupled to the second terminal of resistor 487 and the first terminal of capacitor 416 at node 464 and the drain terminal of FET 406 is coupled to a second terminal of resistor 486 and a first terminal of capacitor 414 at node 482 .
  • gate terminal G 1 of FET 406 is coupled to a second terminal of capacitor 414 and a first terminal of resistor 428
  • gate terminal G 2 of FET 406 is coupled to a first terminal of resistor 430
  • gate terminal G 3 of FET 406 is coupled to a first terminal of resistor 432 and a second terminal of capacitor 416 .
  • the second terminals of resistors 428 , 430 , and 432 are coupled to control voltage input 474 at node 476 .
  • the source terminal of FET 408 is coupled to second terminal of resistor 486 and a first terminal of capacitor 412 at node 482 and the drain terminal of FET 406 is coupled to a second terminal of resistor 485 and a first terminal of capacitor 410 at node 472 .
  • gate terminal G 1 of FET 408 is coupled to a second terminal of capacitor 410 and a first terminal of resistor 422
  • gate terminal G 2 of FET 408 is coupled to a first terminal of resistor 424
  • gate terminal G 3 of FET 408 is coupled to a first terminal of resistor 426 and a second terminal of capacitor 412 .
  • the second terminals of resistors 422 , 424 , and 426 are coupled to control voltage input 474 at node 476 .
  • the source terminal of FET 434 is coupled to the second terminal of resistor 490 and the first terminal of capacitor 444 at node 468 and the drain terminal of FET 434 is coupled to a second terminal of resistor 489 and a first terminal of capacitor 442 at node 484 .
  • gate terminal G 1 of FET 434 is coupled to a second terminal of capacitor 442 and a first terminal of resistor 456
  • gate terminal G 2 of FET 434 is coupled to a first terminal of resistor 458
  • gate terminal G 3 of FET 434 is coupled to a first terminal of resistor 460 and a second terminal of capacitor 444 .
  • the second terminals of resistors 456 , 458 , and 460 are coupled to control voltage input 478 at node 480 .
  • the source terminal of FET 436 is coupled to second terminal of resistor 489 and a first terminal of capacitor 440 at node 484 and the drain terminal of FET 436 is coupled to a second terminal of resistor 488 and a first terminal of capacitor 438 at node 472 .
  • gate terminal G 1 of FET 436 is coupled to a second terminal of capacitor 438 and a first terminal of resistor 450
  • gate terminal G 2 of FET 436 is coupled to a first terminal of resistor 452
  • gate terminal G 3 of FET 436 is coupled to a first terminal of resistor 454 and a second terminal of capacitor 440 .
  • the second terminals of resistors 450 , 452 , and 454 are coupled to control voltage input 478 at node 480 .
  • Switching circuit section 403 can be turned on by applying VH (i.e. a high control voltage) to control voltage input 474 , which turns on FETs 406 and 408 , and switching circuit section 405 can be turned off by applying VL (i.e. a low control voltage) to control voltage input 478 , which turns off FETs 434 and 436 , and vice versa.
  • VH i.e. a high control voltage
  • VL i.e. a low control voltage
  • a 900.0 MHz low band GSM signal at signal input 462 is allowed to pass through FETs 406 and 408 to signal output 470 .
  • signal input 466 is de-coupled from signal output 470 such that another RF signal (e.g. an 1800.0 MHz high band GSM signal) at signal input 466 is prevented from passing through FETs 434 and 436 to signal output 470 .
  • another RF signal e.g. an 1800.0 MHz high band GSM signal
  • an RF signal at signal output 470 provides a peak RF voltage (Vrf) at node 474 , which is equally divided between gate/drain and gate/source junctions of each of FETs 434 and 436 .
  • the RF signal at signal output 470 provides Vrf at node 472 , which is equally divided between gate/drain and gate/source junctions of each of FETs 406 and 408 .
  • a high Vrf can cause the voltage at the gate/drain and gate/source junctions of FETs 434 and 436 to increase such that FET 434 and/or FET 436 turns on, which can cause an undesirable increase in harmonic levels (i.e. amplitudes), such as the amplitude of the third harmonic.
  • the sources and drains of FETs 406 , 408 , 434 , and 436 are coupled to reference voltage 492 , which is substantially equal to VH.
  • the sources and drains of FETs 406 , 408 , 434 , and 436 are set to a predetermined DC voltage (i.e. VH).
  • the sources and drains of FETs 206 , 208 , 234 , and 236 are floating.
  • VH 3.0 volts
  • VL 0.0 volt
  • pinch-off voltage (Vpinch) is equal to ⁇ 1.0 volts
  • Vthreshold the threshold voltage of the FETs in the embodiments in FIGS. 2 and 4 is equal to 0.3 volt.
  • switching circuit section 202 in FIG. 2 is on and switching circuit section 204 is off and switching circuit section 403 in FIG. 4 is on and switching circuit section 405 is off.
  • the source and drain voltages of FETs 206 and 208 will be VH minus Vthreshold (i.e. 3.0 volts ⁇ 0.3 volts), which is equal to 2.7 volts.
  • VL 0.0 volts
  • the gate/source and gate/drain voltages of FETs 234 and 236 will be ⁇ 2.7 volts.
  • the source and drain voltages of the FETs are set to VH, which is equal to 3.0 volts in the present example.
  • VH 3.0 volts in the present example.
  • the gate/source and gate/drain voltages of FETs 434 and 436 will be at ⁇ 3.0 volts instead of ⁇ 2.7 volts.
  • the embodiment of the invention in FIG. 4 achieves greater control over the FETs in a switching circuit section that is turned off compared to the control achieved over the FETs in a turned-off switching circuit section in embodiment of the invention in FIG. 2 .
  • the embodiment of the invention in FIG. 4 achieves a further reduction in third harmonic amplitude at low control voltages compared to the third harmonic amplitude reduction achieved in embodiment of the invention in FIG. 2 .
  • capacitors 410 , 414 , 438 , and 442 which are coupled between gate (G 1 ) and drain of respective FETs 408 , 406 , 436 , and 434
  • capacitors 412 , 416 , 440 , and 444 which are coupled between gate (G 3 ) and source of respective FETs 408 , 406 , 436 and 434 , are provided to attenuate the voltage at gate/drain and gate/source junctions of FETs 408 , 406 , 436 and 434 .
  • the embodiment of the invention in FIG. 4 advantageously achieves a high-frequency switching device having a significantly reduced third harmonic amplitude compared to conventional switching device 100 in FIG. 1 .
  • the embodiment of the invention in FIG. 4 can advantageously operate effectively at a significantly lower control voltage compared to conventional switching device 100 .
  • the embodiment of the invention in FIG. 4 also provides a high-frequency switching device that has significantly increased power handling capability compared to the conventional high-frequency switching device in FIG. 1 . Furthermore, by utilizing multi-gate FETs in place of single gate FETs, the embodiment of the invention in FIG. 4 provides a high-frequency switching device that advantageously occupies a smaller area on a semiconductor die compared to the conventional high-frequency switching device in FIG. 1 .
  • FIG. 5 shows exemplary graph 500 including an exemplary fundamental/third harmonic difference curve in accordance with one embodiment of the present invention.
  • VH axis 502 , dBc axis 504 , and fundamental/third harmonic difference curve 508 correspond, respectively, to VH axis 302 , dBc axis 304 , and fundamental/third harmonic difference curve 308 in graph 300 in FIG. 3 .
  • Fundamental/third harmonic difference curve 510 corresponds to an exemplary difference between a fundamental frequency and a third harmonic as measured in dBm vs. VH for an embodiment of the invention's switching device in FIG. 4
  • fundamental/third harmonic difference curve 508 corresponds to an exemplary difference between the fundamental frequency and the third harmonic as measured in dBm vs. VH for conventional switching circuit 100 in FIG. 1 .
  • fundamental/third harmonic difference curve 508 begins to roll off (i.e. begins to significantly decrease) at approximately 3.0 volts, while fundamental/third harmonic difference curve 510 begins to increase at approximately 2.8 volts.
  • the embodiment of the invention in FIG. 4 provides a significant reduction in third harmonic amplitude for VH less than approximately 3.0 volts compared to conventional switching circuit 100 .
  • the embodiment of the present invention in FIG. 4 achieves a switching device that can effectively operate at a significantly lower control voltage with substantially lower third harmonic amplitude compared to conventional switching device 100 in FIG. 1 .
  • the embodiment of the invention in FIG. 2 advantageously achieves a high-frequency switching device having reduced third harmonic amplitude compared to conventional switching device 100 in FIG. 1 .
  • the embodiment of the invention in FIG. 2 can advantageously operate effectively at a lower control voltage compared to conventional switching device 100 .
  • the embodiment of the invention in FIG. 4 advantageously achieves a high-frequency switching device having a significantly reduced third harmonic amplitude compared to conventional switching device 100 in FIG. 1 .
  • the embodiment of the invention in FIG. 4 can advantageously operate effectively at a significantly lower control voltage compared to conventional switching device 100 .
  • the embodiment of the invention in FIG. 4 provides a high-frequency switching device that has significantly increased power handling capability compared to the conventional high-frequency switching device in FIG. 1 .
  • FIGS. 2 and 4 provide a high-frequency switching device that advantageously occupies a smaller area on a semiconductor die compared to the conventional high-frequency switching device in FIG. 1 .

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PCT/US2007/008635 WO2007123822A2 (en) 2006-04-17 2007-04-04 High-frequency switching device with reduced harmonics
EP07755045.7A EP2008362B1 (de) 2006-04-17 2007-04-04 Hf-schaltgerät mit verminderten oberschwingungen
KR1020087028031A KR101409122B1 (ko) 2006-04-17 2007-04-04 고조파가 감소된 고주파 스위칭 장치

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US10116298B2 (en) * 2016-03-31 2018-10-30 Qorvo Us, Inc. Apparatus with main transistor-based switch and on-state linearization network
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US11418183B2 (en) 2018-03-28 2022-08-16 Psemi Corporation AC coupling modules for bias ladders
US10523195B1 (en) 2018-08-02 2019-12-31 Psemi Corporation Mixed style bias network for RF switch FET stacks
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US10998900B2 (en) 2019-05-30 2021-05-04 Qorvo Us, Inc. Radio frequency switch
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WO2007123822A3 (en) 2008-08-07
WO2007123822A2 (en) 2007-11-01
EP2008362A2 (de) 2008-12-31
KR101409122B1 (ko) 2014-06-17
US20070243849A1 (en) 2007-10-18
KR20090009246A (ko) 2009-01-22
EP2008362B1 (de) 2014-07-02
EP2008362A4 (de) 2010-04-28

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