US8658908B2 - Multiple patterning wiring board, wiring board and electronic apparatus - Google Patents

Multiple patterning wiring board, wiring board and electronic apparatus Download PDF

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Publication number
US8658908B2
US8658908B2 US13/254,138 US201013254138A US8658908B2 US 8658908 B2 US8658908 B2 US 8658908B2 US 201013254138 A US201013254138 A US 201013254138A US 8658908 B2 US8658908 B2 US 8658908B2
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wiring board
groove
electronic component
dividing groove
dividing
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US20110315439A1 (en
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Shuzou Nakashima
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Kyocera Corp
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Kyocera Corp
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/15—Containers comprising an insulating or insulated base
    • H10W76/153—Containers comprising an insulating or insulated base having interconnections in passages through the insulating or insulated base
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/0909—Preformed cutting or breaking line
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10371—Shields or metal cases
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0195—Tool for a process not provided for in H05K3/00, e.g. tool for handling objects using suction, for deforming objects, for applying local pressure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0228—Cutting, sawing, milling or shearing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/60—Seals
    • H10W76/63—Seals characterised by their shape or disposition, e.g. between cap and walls of a container
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present invention relates to a multiple patterning wiring board comprising a base substrate comprising a plurality of wiring board regions arranged in rows and columns in a center portion thereof, the wiring board regions each serving as a wiring board for mounting an electronic component, and a dividing groove being formed at borders between wiring board regions, as well as a wiring board obtained as a result of the multiple patterning wiring board being divided, and an electronic apparatus in which an electronic component is mounted on and a lid member is bonded to the wiring board.
  • Conventional wiring boards for mounting electronic components such as semiconductor devices and crystal oscillators are formed by, for example, disposing a wiring conductor comprising a metallized conductor containing a metal powder such as tungsten or molybdenum on a surface of an insulating base body made of an electrically insulating material such as an aluminum oxide sintered body.
  • Such a wiring board usually includes an electronic component mounting region provided with wiring conductors drawn to the surface so as to be connected to an electronic component.
  • An electronic component is mounted on the electronic component mounting region of such a wiring board, each electrode of the electronic component is electrically connected to the corresponding one of the wiring conductors via electrically connecting means such as solder or a bonding wire, and a lid member made of a metal, ceramics, glass, a resin or the like is bonded such that the lid member covers the electronic component so as to seal the electronic component.
  • An electronic apparatus is produced in this manner.
  • the lid member is bonded to the wiring board by, for example, using a sealant such as a resin.
  • a sealant such as a resin
  • a wiring board having a recess portion on the upper face thereof in which in a frame-like portion (side wall portion) surrounding the recess portion, a groove having a V-shaped cross section (with its opening width being as large as the width of the side wall portion) is formed so as to extend over the entire width of the side wall portion from the outer end to the inner end (see, for example, Patent Literature 1).
  • the multiple patterning wiring board is a board in which a plurality of wiring board regions are arranged and formed in rows and columns in a center portion of a broad base substrate, the wiring board regions each serving as a wiring board after the base substrate is divided, and dividing grooves for dividing the wiring board regions are formed in rows and columns.
  • Some wiring boards are flat plate-shaped without a recess portion, and a lid member that has a recess portion and covers an electronic component mounted on the center portion of the wiring board is bonded to such a wiring board.
  • a method can be conceived in which, as in the case of the wiring board having a recess portion as described above, a groove having a V-shaped cross section (with its opening width being as large as a width between the electronic component mounting region and an outer edge of the wiring board) is formed so as to extend over the entire width between the electronic component mounting region and the outer edge of the wiring board.
  • the method in which a multiple patterning wiring board having a groove for increasing the bonding strength to a lid member in each wiring board region is produced and divided along a dividing groove is problematic in that the multiple patterning wiring board is not properly divided along the dividing groove and as a result a burr or crack is likely to form in an outer edge portion of the resulting wiring boards.
  • the groove for increasing the bonding strength to a lid member is formed in the same main face as the dividing groove at a depth deeper than the dividing groove, for example, the stress applied when dividing the base substrate tends to concentrate in the bottom of the groove, so that the base substrate is likely to be divided from the bottom of the groove, rather than the bottom of the dividing groove.
  • the invention has been conceived in view of the problems encountered with the related art as described above, and it is an object of the invention to provide a multiple patterning wiring board that can reduce burrs and cracks that form in wiring boards when the multiple patterning wiring board having a groove for bonding a lid member in one main face is divided. It is another object of the invention to provide a wiring board obtained from such a multiple patterning wiring board and an electronic apparatus including such a wiring board.
  • the invention provides a multiple patterning wiring board, comprising a base substrate comprising in one main surface thereof, a plurality of wiring board regions arranged in rows and columns, the wiring board regions each comprising an electronic component mounting region in a center portion thereof, a dividing groove at borders between the wiring board regions and, a region configured to bond a lid member which is formed between the electronic component mounting region and the dividing groove, wherein the lid member bonding region comprises a groove, the groove having a width less than or equal to a width of the electronic component mounting region and a depth less than a depth of the dividing groove.
  • the groove extends continuously along the dividing groove between adjacent two regions of the plurality of wiring board regions.
  • the invention provides a wiring board obtained by dividing the multiple patterning wiring board mentioned above along the dividing groove.
  • the invention provides a wiring board obtained by dividing the multiple patterning wiring board mentioned above along the dividing groove, wherein the wiring board comprises, in the one main face, an electronic component mounting region, and a groove is located between the electronic component mounting region and an outer edge of the wiring board, and has both ends thereof extending to opposing sides.
  • the invention provides an electronic apparatus, comprising an electronic component mounted on the electronic component mounting region of the wiring board mentioned above and a lid member bonded so as to cover the electronic component.
  • a region configured to bond a lid member which is formed between an electronic component mounting region and a dividing groove in one main face of a base substrate, and the lid member bonding region comprises a groove, the groove having a width less than or equal to the width of the electronic component mounting region and a depth less than the depth of the dividing groove. Therefore, the stress applied when dividing the base substrate by bending easily concentrates in the bottom of the dividing groove rather than the bottom of the groove, and as a result, a situation in which the base substrate is divided from the bottom of the groove can be suppressed.
  • the bottom of the dividing groove is located at a position deeper than the bottom of the groove and the bottom of the groove is not located between the bottom of the dividing groove and the other main face. Therefore, a situation is suppressed in which fractures forming from the bottom of the dividing groove deviate toward the groove while running toward the other main face. Accordingly, the base substrate can be properly divided along the dividing groove, and it is therefore possible to reduce the possibility of the formation of a burr or crack in the outer edge portion of the divided wiring boards.
  • the groove when the groove extends continuously along the dividing groove between adjacent two regions of the plurality of wiring board regions, the groove is linear extending over a plurality of wiring board regions. Therefore, the groove can be easily formed using a cutter blade or the like when the multiple patterning wiring board is produced, and the surface area of the groove at the corner of the upper face of a divided wiring board can be increased.
  • the wiring board is a wiring board obtained by dividing the multiple patterning wiring board of the above configuration along the dividing groove, and therefore the formation of a burr or crack at the outer edge portion of the wiring board is reduced and the opening width of the groove is smaller than the width between the electronic component mounting region and the outer edge of the wiring board, and as a result, a predetermined width can be secured between the outer edge of the divided wiring board and the groove, and this portion will not be easily cracked due to the wiring board bumping into another wiring board or the like. Accordingly, the outer edge of the wiring board can be easily recognized by an image recognition apparatus or the like and an electronic component can be mounted onto the wiring board using the outer edge of the wiring board as a reference with high positional accuracy.
  • the wiring board is a wiring board obtained by dividing the multiple patterning wiring board of the above configuration along the dividing groove, wherein the wiring board comprises, comprising, in one main face, an electronic component mounting region, and a groove is located between the electronic component mounting region and an outer edge of the wiring board, and ends thereof extend to opposing sides. Therefore, the surface area of the groove at the corner of the wiring board as viewed from above can be increased, and the amount of sealant at the corner can be increased, and as a result, the bonding strength of the corner of the wiring board to a lid member can be increased.
  • an electronic component is mounted on the electronic component mounting region of the wiring board having the above configuration and a lid member is bonded so as to cover the electronic component. Therefore, the formation of a burr or crack at the outer edge portion of the electronic apparatus is reduced, and the groove can be properly filled with a sealant, securely bonding the wiring board and the lid member, and as a result, the outer edge of the electronic apparatus can be easily recognized by an image recognition apparatus or the like, and the electronic apparatus can be mounted onto an external electrical circuit board using the outer edge of the electronic apparatus as a reference with high positional accuracy.
  • FIG. 1( a ) is a plan view of a multiple patterning wiring board according to an embodiment of the invention
  • FIG. 1( b ) is a cross-sectional view taken along the line A-A of FIG. 1( a );
  • FIG. 2( a ) is an enlarged plan view of a section A shown in FIG. 1( a ), and FIG. 2( b ) is an enlarged cross-sectional view of the section A shown in FIG. 1( b );
  • FIG. 3( a ) is a plan view of a multiple patterning wiring board according to an embodiment of the invention
  • FIG. 3( b ) is a cross-sectional view taken along the line A-A of FIG. 3( a );
  • FIG. 4( a ) is an enlarged cross sectional view of a section A shown in FIG. 3( a ), and FIG. 4( b ) is an enlarged cross-sectional view of the section A shown in FIG. 3( b );
  • FIG. 5( a ) is a plan view of a multiple patterning wiring board according to an embodiment of the invention
  • FIG. 5( b ) is a cross-sectional view taken along the line A-A of FIG. 5( a );
  • FIG. 6( a ) is an enlarged cross sectional view of a section A shown in FIG. 5( a ), and FIG. 6( b ) is an enlarged cross-sectional view of the section A shown in FIG. 5( b );
  • FIG. 7 is an enlarged cross-sectional of a relevant part of a multiple patterning wiring board according to another embodiment of the invention.
  • FIGS. 8( a ) to 8 ( c ) are cross-sectional views showing an example of a process for manufacturing a multiple patterning wiring board according to the invention.
  • FIGS. 9( a ) and 9 ( b ) are cross-sectional views showing another example of a process for manufacturing a multiple patterning wiring board according to the invention.
  • FIGS. 10( a ) and 10 ( b ) are cross-sectional views showing another example of a process for manufacturing a multiple patterning wiring board according to the invention.
  • FIG. 11 is a cross-sectional view showing another example of a process for manufacturing a multiple patterning wiring board according to the invention.
  • FIG. 12( a ) is a perspective view of a wiring board according to an embodiment of the invention
  • FIG. 12( b ) is a cross-sectional view of an electronic apparatus according to an embodiment of the invention
  • FIG. 13( a ) is a perspective view of a wiring board according to an embodiment of the invention
  • FIG. 13( b ) is a cross-sectional view of an electronic apparatus according to an embodiment of the invention.
  • FIGS. 14( a ) and 14 ( b ) are plan views of a relevant part of a multiple patterning wiring board according to an embodiment of the invention.
  • FIGS. 1 to 7 illustrate multiple patterning wiring boards according to embodiments of the invention.
  • reference numeral 1 denotes a base substrate
  • reference numeral 1 a denotes a wiring board region
  • reference numeral 1 b denotes an electronic component mounting region
  • reference numeral 1 c denotes a lid member bonding region
  • reference numeral 1 d denotes a second electronic component mounting region
  • reference numeral 2 ( 2 x , 2 y ) denotes a dividing groove
  • reference numeral 2 a ( 2 ya ) denotes a second dividing groove
  • reference numeral 3 3 x , 3 y ) denotes a groove
  • reference numeral 4 denotes a wiring conductor
  • reference numeral 5 denotes a recess portion.
  • FIGS. 2( a ), 4 ( a ) and 6 ( a ) are shown in the plan views, the dividing grooves 2 ( 2 x , 2 y ) and the grooves 3 ( 3 x , 3 y ) are hatched for easy recognition.
  • a total of sixteen wiring board regions 1 a are arranged in the base substrate 1 , with four wiring board regions 1 a in each row and column.
  • Dividing grooves 2 including a vertical dividing groove 2 y and a horizontal dividing groove 2 x are formed at borders between wiring board regions 1 a .
  • the multiple patterning wiring board comprises a base substrate 1 comprising in one main surface thereof, a plurality of wiring board regions 1 a arranged in rows and columns, the wiring board regions 1 a each comprising an electronic component mounting region 1 b in a center portion thereof, a dividing groove 2 at borders between the wiring board regions 1 a , and a region is configured to bond a lid member (not shown) which is formed between the electronic component mounting region 1 b and the dividing groove 2 , wherein the lid member bonding region is comprises grooves 3 , the groove having a width less than a width of the region 1 c and a depth d 2 less than a depth d 1 of the dividing groove 2 .
  • the base substrate 1 can be divided from the bottom of the dividing groove 2 .
  • the bottom of the dividing groove 2 is located at a position deeper than the bottom of the groove 3 , the bottom of the groove 3 is not located at a position between the bottom of the dividing groove 2 and the other main face, and therefore a situation is suppressed in which fractures forming from the bottom of the dividing groove 2 deviate toward the groove 3 while running toward the other main face. Accordingly, the base substrate 1 can be properly divided into individual wiring board regions 1 a along the dividing groove 2 , and it is therefore possible to reduce the possibility of the formation of a burr or crack in the outer edge portion of the divided wiring boards.
  • the groove 3 extends continuously along either the vertical dividing groove 2 or the horizontal dividing groove 2 of the base substrate 1 between adjacent two regions of the plurality of wiring board regions 1 a .
  • the groove 3 is linear extending over a plurality of wiring board regions 1 a , and therefore the groove 3 can be easily formed using a cutter blade or by dicing or the like when the multiple patterning wiring board is produced, and the surface area of the groove 3 at the corner of the upper face of a divided wiring board can be increased.
  • the base substrate 1 comprises, for example, a plurality of wiring board regions 1 a arranged in rows and columns in a center portion of an electrically insulating base body made of an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, a silicon nitride sintered body or a ceramic material such as glass ceramics, the wiring board regions 1 a each comprising a wiring conductor 4 comprising a metallized conductor containing a metal powder such as tungsten, molybdenum, copper or silver formed therein.
  • the base substrate 1 is produced as follows. A ceramic slurry obtained by mixing a ceramic raw material powder such as aluminum oxide, silicon oxide, magnesium oxide or calcium oxide with an appropriate organic binder, solvent, plasticizer, dispersing agent and the like is formed into a sheet by using a conventionally known sheet forming method such as a doctor blade method to give a ceramic green sheet. After that, the ceramic green sheet is appropriately punched. Where necessary, a plurality of punched ceramic green sheets are stacked to produce a green formed product that will serve as the base substrate 1 . The green formed product is fired at a temperature of approximately 1500 to 1800° C. In this manner, a base substrate composed of a single or a plurality of insulating layers is produced.
  • a ceramic raw material powder such as aluminum oxide, silicon oxide, magnesium oxide or calcium oxide
  • solvent, plasticizer, dispersing agent and the like is formed into a sheet by using a conventionally known sheet forming method such as a doctor blade method to give a ceramic green sheet. After that, the ceramic green sheet is appropriately punched
  • the wiring conductor 4 comprises a wiring conductor layer disposed on the surface of the insulating base body or between insulating layers and a through conductor that passes through the insulating layers to electrically connect the wiring conductor layers located above and below the through conductor.
  • the wiring conductor layer is formed by printing/applying a metallized paste for forming the wiring conductor layer onto the ceramic green sheet for forming the base substrate 1 by printing means such as a screen printing method and firing the paste together with the green formed product that will serve as the base substrate 1 .
  • the through conductor is formed by, prior to printing/applying the metallized paste for forming the wiring conductor, forming a through hole for forming the through conductor in the ceramic green sheet for forming the base substrate 1 by a processing method such as punching using a cast or punch or laser processing, filling the through hole with a metallized paste for forming the through conductor by printing means such as a screen printing method, and firing the paste together with the green formed product that will serve as the base substrate 1 .
  • the metallized paste is produced by adding an organic binder, an organic solvent, optionally a dispersing agent and the like to a metal powder as a main component and mixing and kneading these components by kneading means such as a ball mill, three-roll mill or planetary mixer.
  • a glass or ceramic powder may be added according to the sintering behavior of the ceramic green sheet or in order to increase the bonding strength to the base substrate after firing.
  • the metallized paste for forming the through conductor is adjusted by the type or amount of organic binder or organic solvent that is added so as to have a viscosity suitable for filling, generally, a viscosity higher than that of the metallized paste for forming the wiring conductor layer.
  • An exposed surface of the wiring conductor 4 is coated with a metal having excellent corrosion resistance such as nickel or gold as necessary. It is thereby possible to effectively suppress corrosion of the wiring conductor 4 , as well as securing the bonding between the wiring conductor 4 and an electronic component, the bonding between the wiring conductor 4 and a bonding wire and the bonding between the wiring conductor 4 and a wiring conductor of an external electrical circuit board.
  • the exposed surface of the wiring conductor 4 may be coated with, for example, a nickel plating layer having a thickness of about 1 to 10 ⁇ m and a gold plating layer having a thickness of about 0.1 to 3 ⁇ m that are formed in sequence by an electrolytic plating method or electroless plating method.
  • the dividing groove 2 is formed at borders between wiring board regions 1 a in one main face of the base substrate 1 .
  • the vertical cross-section of the dividing groove 2 may be V-shaped, U-shaped or rectangular.
  • the bottom of the dividing groove 2 has a shape in which stress is easily concentrated when the base substrate 1 is broken along the dividing groove 2 by bending, and therefore the base substrate 1 can be broken with ease and accuracy.
  • a second dividing groove 2 a ( 2 ya in the vertical direction of FIG. 7 ) at borders between wiring board regions 1 a in the other main face of the base substrate 1 .
  • the bottom of the dividing groove 2 on one main face side is located at a position that is deeper than the bottom of the groove 3 and near the bottom of the second dividing groove 2 a on the other main face side, and therefore fractures will easily run from the bottom of the second dividing groove 2 a on the other main face side toward the bottom of the dividing groove 2 on one main face side that is opposite to the other main face.
  • a positional offset of about several tens to several hundreds of micrometers can occur between the dividing groove 2 on one main face side and the second dividing groove 2 a on the other main face side.
  • the groove 3 is provided at a position that is spaced apart from the dividing groove 2 on one main face side and is closer to the electronic component mounting region 1 b , the second dividing groove 2 a and the groove 3 are far apart from each other, and therefore progression of fracturing from the second dividing groove 2 a toward the groove 3 is suppressed, and the possibility of the formation of a burr or crack in the outer edge portion of the wiring board can be reduced.
  • the groove 3 is preferably provided at a position closer to the recess portion 5 , rather than a position closer to the dividing groove 2 for the same reason described above.
  • the depth of the dividing groove 2 is set as appropriate according to the material or the like of the insulating base body, and the dividing groove 2 is formed to have a depth that is about 50 to 70% of the thickness of the base substrate 1 . By doing so, it is possible to obtain a multiple patterning wiring board in which the base substrate 1 can be properly divided and which can be prevented from inadvertent fracturing.
  • the second dividing groove 2 a is formed in the other main face of the base substrate 1 , the second dividing groove 2 a is formed such that the total depth of the dividing groove 2 and the second dividing groove 2 a will be the above-described percentage of the thickness of the base substrate 1 .
  • the dividing groove 2 in one main face of the base substrate 1 has an opening width of about 0.05 to 1.0 mm.
  • the opening width of the dividing groove 2 falls within this range, the base substrate 1 can be properly divided. Further, the size of the wiring board regions 1 a is not reduced by the influence of the surface area occupied by the dividing groove 2 , and the wiring board regions 1 a are not deformed significantly when the dividing groove 2 is formed.
  • the groove 3 is formed in the lid member bonding region 1 c between the dividing groove 2 and the electronic component mounting region 1 b in one main face of the base substrate 1 .
  • the groove 3 has a rectangular frame-like shape surrounding the electronic component mounting region 1 b .
  • the groove 3 has a shape extending along either the vertical dividing groove 2 or the horizontal dividing groove 2 of the base substrate 1 (a vertical groove 3 has a shape extending along the vertical dividing groove 2 and a horizontal groove 3 has a shape extending along the horizontal dividing groove 2 ), and is continuous between adjacent wiring board regions 1 a .
  • FIGS. 1 to 6 as shown in FIGS.
  • the depth d 2 of the groove 3 is set to be smaller than the depth d 1 of the dividing groove 2 , and the groove 3 is formed to have a depth that is about 10 to 40% of the thickness of the base substrate 1 .
  • the groove 3 has a cross section having a shape as in the examples shown in FIGS. 1 to 6 . In the case where the groove 3 is formed using a cutter blade, the bottom of the groove 3 has a V-shaped vertical cross section, but it may be U-shaped or rectangular.
  • the groove 3 In order to reduce the occurrence of fracturing in the bottom of the groove 3 when the base substrate 1 is divided, it is preferable to form the groove 3 to have a shape in which the stress does not easily concentrate in the bottom, such as a U shape or round rectangular shape having round corners. Such a shape can be obtained by forming the groove 3 using a laser.
  • the bottom angle of the groove 3 is set to, for example, about 20 degrees to 90 degrees.
  • the base substrate 1 has dummy regions if in the periphery of a center portion in which a plurality of wiring board regions 1 a are arranged in rows and columns.
  • the dummy region if is a region for facilitating manufacturing and transportation of the multiple patterning wiring board. Positioning, fixation and the like can be performed using the dummy region if during processing or transportation of the green formed product which will serve as the base substrate 1 or the multiple patterning wiring board.
  • end portions of the dividing groove 2 are located in the dummy region if between the outermost wiring board region 1 a and the periphery of the green formed product which will serve as the base substrate 1 .
  • the dummy region may be provided between a plurality of wiring board regions 1 a .
  • the dividing groove 2 is formed between the wiring board region 1 a and the dummy region.
  • grooves 3 are symmetrically provided with respect to a dividing groove 2 , or in other words, it is preferable that as in the example shown in FIG. 7 , distances w 1 between a pair of grooves 3 provided on opposing sides of a dividing groove 2 and the dividing groove 2 are the same.
  • the distance w 1 from the dividing groove 2 to the groove 3 is substantially equal on both sides of the dividing groove 2 , and therefore when the base substrate 1 is divided along the dividing groove 2 , the stress is applied substantially equally to both sides of the dividing groove 2 , and as a result, it is possible to further reduce the possibility of the formation of a burr or crack in the outer edge portion of the wiring boards.
  • a groove 3 is also formed in the dummy region 1 f , and the groove 3 formed in the wiring board region 1 a and the groove 3 formed in the dummy region 1 f are symmetrically provided with respect to the dividing groove 2 . Further, it is preferable that the distance w 1 between the dividing groove 2 and the groove 3 is larger than the distance between the electronic component mounting region 1 b and the groove 3 (w 2 shown in FIG. 7 ) (w 1 >w 2 ).
  • the groove 3 is provided at a position that is spaced apart from the dividing groove 2 and is closer to the electronic component mounting region 1 b . Therefore, division from the bottom of the groove 3 can be suppressed, and the possibility of the formation of a burr or crack in the outer edge portion of the divided wiring boards can be reduced.
  • FIGS. 14( a ) and 14 ( b ) are plan views of a relevant part of a multiple patterning wiring board according to an embodiment of the invention.
  • the lid member bonding region 1 c and the groove 3 are out of alignment by an amount corresponding to the amount by which the electronic component mounting region 1 b is out of alignment with the center of the wiring board region 1 a , and thus the distances between the dividing groove 2 and the respective grooves 3 become different (wL>wR), and as a result, when the base substrate 1 is divided along the dividing groove 2 , the stress is not equally applied to both sides of the dividing groove 2 .
  • the dividing groove 2 and the groove 3 can be formed by pressing a cutter blade or cast against the green formed product which will serve as the base substrate 1 or by subjecting the green formed product which will serve as the base substrate 1 or the fired base substrate 1 to laser processing or dicing processing.
  • FIGS. 8 to 11 are enlarged cross-sectional views showing examples of a process for manufacturing the multiple patterning wiring board shown in FIGS. 3 and 4 .
  • reference numeral 1 ′ denotes a green formed product that will serve as a base substrate 1
  • reference numeral 2 y ′ denotes a notch that is formed in the green formed product 1 ′ and will serve as a dividing groove 2 y
  • reference numeral 3 y ′ denotes a notch that is formed in the green formed product 1 ′ and will serve as a groove 3 y
  • reference numeral 4 ′ denotes a metallized paste that will serve as a wiring conductor 4
  • reference numeral 6 denotes a cutter blade for forming the notch 2 y ′
  • reference numeral 7 denotes a cutter blade for forming the notch 3 y ′.
  • FIGS. 8 to 11 show a step of forming the notch 2 y ′ which will serve as the dividing groove 2 y and the notch 3 y ′ which will serve as the groove 3 y in the green formed product 1 ′ with the cutter blades 6 and 7 in the process for manufacturing a multiple patterning wiring board of the invention as in the example shown in FIGS. 3 and 4 .
  • the dividing groove 2 and the groove 3 are formed as follows, for example.
  • the green formed product 1 ′ is prepared, and thereafter, the cutter blade 6 is pressed against the green formed product 1 ′ which will serve as the base substrate 1 to form a notch 2 y ′ which will serve as a dividing groove 2 y .
  • the cutter blade 7 is pressed against the green formed product 1 ′ which will serve as the base substrate 1 to form a notch 3 y ′ which will serve as a groove 3 y .
  • the green formed product 1 ′ is fired, whereby a base substrate 1 having a dividing groove 2 y and a groove 3 y is obtained.
  • horizontal dividing grooves 2 x and horizontal grooves 3 x are formed in the same manner as the vertical dividing grooves 2 y and the vertical grooves 3 y are formed.
  • notches 3 y ′ provided on both sides of a notch 2 y ′ are formed in two steps, but as in the example shown in FIG. 9 , the notches 3 y ′ on both sides of a notch 2 y ′ may be formed simultaneously.
  • the notch 3 y ′ forming step can be simplified, and it is possible to reduce deformation of the green formed product 1 ′, deformation of the notch 2 y ′ and the notch 3 y ′ and the like, and thus the dividing groove 2 y and the groove 3 y can be formed with high accuracy.
  • an integrated cutter blade having two cutter blades 7 may be used.
  • Such a cutter blade is thick as a whole, it is possible to reduce a situation in which the cutter blade 7 is deformed due to the stress applied when the notch 3 y ′ is formed and as a result the depth, inclination or the like of the notch 3 y ′ are changed as compared to the case where the notches 3 y ′ are formed in two steps using a single thin cutter blade 7 .
  • Such a cutter blade can be easily produced by, for example, bonding two cutter blades 7 together.
  • the notches 3 ′ are formed after the notches 2 ′ have been formed in the green formed product 1 ′, but as in the example shown in FIG. 10 , the notches 2 ′ may be formed after the notches 3 ′ have been formed in the green formed product 1 ′.
  • the notches 2 ′ and the notches 3 ′ may be formed simultaneously. In this case, the notches 2 ′ and the notches 3 ′ may be formed simultaneously using an integrated cutter blade having a cutter blade 6 for forming the notch 2 ′ and cutter blades 7 for forming the notches 3 ′.
  • the step of forming the notches 2 ′ and the notches 3 ′ can be simplified, and it is possible to control the distance w 1 between the dividing groove 2 and the groove 3 with high accuracy.
  • the notches 3 y ′ are formed after the notches 2 y ′ have been formed in the green formed product 1 ′ as in the example shown in FIGS. 8 and 9 , it is possible to suppress a situation in which the width and depth of the notches 3 ′ are reduced due to deformation of the green formed product 1 ′ by the stress applied when the notches 2 ′ having a greater depth are formed, and the width and depth of the grooves 3 y can be controlled with high accuracy, as compared to the case where the notches 3 y ′ are formed first.
  • the notches 3 y ′ are formed to have a depth less than that of the notches 2 y ′, deformation of the green formed product 1 ′ that occurs when the notches 3 y ′ are formed is smaller than that when the notches 2 y ′ are formed, and thus a situation is suppressed in which the depth of the notches 2 ′ is reduced due to deformation of the green formed product 1 ′.
  • a vertical notch 3 ′ and a horizontal notch 3 ′ ( 3 x ′ and 3 y ′) which will serve as grooves 3 ( 3 x and 3 y ) may be formed after a notch 2 y ′ which will serve as a vertical dividing groove 2 y and a notch 2 x ′ which will serve as a horizontal dividing groove 2 x have been formed.
  • FIGS. 12( a ) and 13 ( a ) are perspective views of wiring boards according to embodiments of the invention
  • FIGS. 12( b ) and 13 ( b ) are cross-sectional views of electronic apparatuses according to embodiments of the invention.
  • reference numeral 8 denotes an electronic component
  • reference numeral 9 denotes a lid member
  • reference numeral 10 denotes a sealant
  • reference numeral 11 denotes a bonding material
  • reference numeral 12 denotes a second electronic component.
  • the example shown in FIG. 12( a ) illustrates an example of a wiring board 1 e obtained by dividing the multiple patterning wiring board shown in FIGS. 1 and 2
  • the example shown in FIG. 13( a ) illustrates an example of a wiring board 1 e obtained by dividing the multiple patterning wiring board shown in FIGS. 5 and 6 .
  • a wiring board 1 e of the invention is a wiring board obtained by dividing any of the multiple patterning wiring boards having the above configurations along the dividing groove 2 .
  • the formation of a burr or crack is reduced at the outer edge portion of the wiring board 1 e , and the opening width of the groove 3 is less than the width of the side wall portion, and therefore there is an appropriate thickness between the outer edge of the divided wiring board 1 e and the groove 3 , and this portion will not be easily cracked due to the wiring board 1 e bumping into another wiring board 1 e or the like during transportation, so that the outer edge of the wiring board 1 e can be easily recognized by an image recognition apparatus or the like, and an electronic component 8 can be mounted onto the wiring board 1 e using the outer edge of the wiring board 1 e as a reference with high positional accuracy.
  • a wiring board 1 e of the invention is a wiring board obtained by dividing any of the multiple patterning wiring boards configured as in the examples shown in FIGS. 1 to 6 along the dividing groove 2 .
  • the wiring board 1 e has, in one main face, an electronic component mounting region 1 b and a groove 3 is located between the electronic component mounting region 1 b and the outer edge of the wiring board 1 e and ends thereof extend to opposing sides.
  • the surface area of the groove 3 at the corner of the wiring board 1 e can be increased as viewed from above and the amount of sealant 10 at the corner can be increased, and as a result, the bonding strength of the corner of the wiring board 1 e to a lid member 9 can be increased.
  • a situation can be suppressed in which a gap is created between the corner of the wiring board 1 e and the sealant 10 due to application of heat to cure the sealant 10 , and the thickness of the sealant 10 at the corner of the wiring board 1 e is reduced, and as a result, the bonding strength between the wiring board 1 e and the lid member 9 is reduced.
  • the groove 3 is cross-shaped at the corner where thermal stress due to the difference in thermal expansion between the wiring board 1 e and the lid member 9 becomes large, so that the bonding surface area of the sealant 10 is increased and the sealant 10 filling the groove 3 will serve as a resistance against the horizontal force, and as a result, the bonding reliability between the lid member 9 and the wiring board 1 e is improved.
  • An electronic apparatus of the invention is an electronic apparatus, as in the examples shown in FIGS. 12( b ) and 13 ( b ), in which an electronic component 8 is mounted on the electronic component mounting region 1 b of the wiring board 1 e having the above configuration and a lid member 9 is bonded so as to cover the electronic component 8 , and it is therefore possible to fill the groove 3 with a sealant 10 and securely bond the wiring board 1 e and the lid member.
  • FIG. 12( b ) illustrates an electronic apparatus in which an electronic component 8 is mounted on the electronic component mounting region 1 b and a cap-shaped lid member 9 is bonded so as to cover the electronic component.
  • FIG. 12( b ) illustrates an electronic apparatus in which an electronic component 8 is mounted on the electronic component mounting region 1 b and a cap-shaped lid member 9 is bonded so as to cover the electronic component.
  • FIG. 13( b ) illustrates an electronic apparatus in which the electronic component mounting region 1 b has a recess portion 5 , second electronic components 12 are mounted on the bottom of the recess portion 5 , an electronic component 8 is mounted on the opening of the recess portion 5 so as to cover the recess portion 5 , and a cap-shaped lid member 9 is bonded so as to cover the electronic component 8 .
  • the electronic component 8 is a semiconductor device such as an IC chip or LSI chip, a piezoelectric element such as a crystal oscillator or piezoelectric vibrator, or any of various sensors.
  • the electronic component 8 is mounted as follows. In the case where the electronic component 8 is a flip-chip type semiconductor device, for example, the electronic component 8 is mounted by electrically or mechanically connecting an electrode of the semiconductor device and a wiring conductor 4 via a bonding material 11 such as a solder bump, a gold bump or a conductive resin (anisotropic conductive resin or the like). In the case of the example shown in FIG. 12 , after the electronic component 8 has been bonded to the electronic component mounting region 1 b using the bonding material 11 , an underfill may be injected between the electronic component 8 and the wiring board 1 e .
  • a bonding material 11 such as a solder bump, a gold bump or a conductive resin (anisotropic conductive resin or the like.
  • the electronic component 8 is a wire-bonding type semiconductor device
  • an electrode of the semiconductor device and a wiring conductor 4 are electrically connected via a bonding wire.
  • the electronic component 8 is a piezoelectric element such as a crystal oscillator
  • the piezoelectric element is fixed using a bonding material 11 such as a conductive resin and an electrode of the piezoelectric element and a wiring conductor are electrically connected.
  • a second electronic component 12 such as a resistive element or capacitive element may be mounted in the periphery of the electronic component 8 .
  • the size of the electronic apparatus can be reduced as compared to the case where the electronic component 8 and the second electronic component 12 are mounted in the same plane.
  • the lid member 9 is a cap-shaped lid member made of a metal, ceramics, glass, a resin or the like.
  • the lid member 9 is preferably made of a material having a thermal expansion coefficient that is close to that of the insulating base body of the wiring board 1 e .
  • the lid member may be made of an Fe—Ni (iron-nickel) alloy, an Fe—Ni—Co (iron-nickel-cobalt) alloy or the like.
  • the lid member 9 not only a lid member made of a light transmitting plate material made of glass, a resin or the like, but also a lid member having a light transmitting lens made of glass, a resin or the like, or a lens attached thereto.
  • the electronic component 8 may be coated with a resin such as epoxy resin or silicone resin as necessary.
  • a resin such as epoxy resin or silicone resin
  • the electronic component 8 may be covered with a resin containing a phosphor, so that the wavelength of the light emitted from the light emitting element can be converted by the phosphor contained in the covering resin.
  • the sealant 10 can be made of a thermosetting or photocurable resin material such as acrylic resin, epoxy resin, phenol resin, cresol resin, silicone resin or polyether amide resin, or low melting glass.
  • the sealant 10 may optionally contain a dark color pigment or dye such as black, brown, dark brown, dark green or deep blue.
  • the electronic component 8 is a light emitting element and a light-shielding lid member 9 whose upper portion is partially light transmitting is bonded, it is possible to prevent the light from the light emitting element from leaking to the sides through the sealant 10 .
  • a recess portion 5 and a groove 3 are formed only in one main face of the base substrate 1 , but a dividing groove 2 , a groove 3 and a recess portion 5 may be formed on the other main face.
  • the depth of the groove 3 formed in the other main face is also set to be less than the depth of the dividing groove 2 and the recess portion 5 formed in the other main face.
  • the electronic apparatus may be produced by mounting an electronic component 8 onto each wiring board region 1 a of the multiple patterning wiring board and bonding a lid member 9 thereto, and thereafter dividing the multiple patterning wiring board along the dividing groove 2 .

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structure Of Printed Boards (AREA)
US13/254,138 2009-06-25 2010-06-23 Multiple patterning wiring board, wiring board and electronic apparatus Expired - Fee Related US8658908B2 (en)

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JP2009-150614 2009-06-25
JP2009150614A JP5355246B2 (ja) 2009-06-25 2009-06-25 多数個取り配線基板および配線基板ならびに電子装置
PCT/JP2010/060658 WO2010150820A1 (ja) 2009-06-25 2010-06-23 多数個取り配線基板および配線基板ならびに電子装置

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11490511B2 (en) * 2018-06-28 2022-11-01 Kyocera Corporation Circuit board and electronic device that includes it

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012108229A1 (ja) * 2011-02-07 2012-08-16 株式会社村田製作所 セラミック基板およびその製造方法
JP5763962B2 (ja) 2011-04-19 2015-08-12 日本特殊陶業株式会社 セラミック配線基板、多数個取りセラミック配線基板、およびその製造方法
JP5945099B2 (ja) 2011-04-20 2016-07-05 日本特殊陶業株式会社 配線基板、多数個取り配線基板、およびその製造方法
JP6006474B2 (ja) 2011-04-25 2016-10-12 日本特殊陶業株式会社 配線基板、多数個取り配線基板、およびその製造方法
KR20140109849A (ko) * 2011-12-27 2014-09-16 니혼도꾸슈도교 가부시키가이샤 배선기판 및 다수개 취득 배선기판
KR20130081515A (ko) * 2012-01-09 2013-07-17 삼성전자주식회사 Ｌｅｄ 패키지용 기판 및 ｌｅｄ 패키지 제조방법
JP6129491B2 (ja) * 2012-08-06 2017-05-17 Ｎｇｋエレクトロデバイス株式会社 多数個取り配線基板
JP6029173B2 (ja) * 2013-02-04 2016-11-24 Ｎｇｋエレクトロデバイス株式会社 セラミックパッケージ及びその製造方法
CN105359632B (zh) * 2013-10-23 2018-02-06 京瓷株式会社 布线基板以及电子装置
US9820384B2 (en) * 2013-12-11 2017-11-14 Intel Corporation Flexible electronic assembly method
JP6403092B2 (ja) * 2014-10-20 2018-10-10 日立金属株式会社 セラミック基板およびそれを用いた電子部品の製造方法
EP3448133B1 (en) 2016-04-22 2020-12-02 Kyocera Corporation Multipiece wiring board, wiring board, and method for manufacturing multipiece wiring board
CN111433285B (zh) * 2017-12-08 2022-07-26 东洋纺株式会社 聚酯弹性体树脂组合物
JP6550516B1 (ja) * 2018-09-18 2019-07-24 レノボ・シンガポール・プライベート・リミテッド パネル、ｐｃｂおよびｐｃｂの製造方法
DE102018128570A1 (de) * 2018-11-14 2020-05-14 Osram Opto Semiconductors Gmbh Verfahren zur herstellung einer vielzahl strahlungsemittierender bauelemente, strahlungsemittierendes bauelement, verfahren zur herstellung eines verbindungsträgers und verbindungsträger
JP7200705B2 (ja) * 2019-01-31 2023-01-10 セイコーエプソン株式会社 振動デバイス、振動デバイスの製造方法、振動モジュール、電子機器および移動体
JP7135947B2 (ja) * 2019-03-12 2022-09-13 三菱マテリアル株式会社 絶縁回路基板の製造方法及びセラミックス板
JP2023139724A (ja) * 2022-03-22 2023-10-04 キヤノン株式会社 多面取り基板、機能モジュール及びその製造方法

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3608186A (en) * 1969-10-30 1971-09-28 Jearld L Hutson Semiconductor device manufacture with junction passivation
US5024970A (en) * 1989-06-27 1991-06-18 Mitsubishi Denki Kabushiki Kaisha Method of obtaining semiconductor chips
US20030042596A1 (en) * 2001-09-06 2003-03-06 Crane Stanford W. Semiconductor package
JP2004200631A (ja) 2002-12-13 2004-07-15 Kingpak Technology Inc 光センサパッケージ構造
JP2006041456A (ja) 2004-06-25 2006-02-09 Kyocera Corp 光半導体素子収納用パッケージおよび光半導体装置
JP2006128363A (ja) 2004-10-28 2006-05-18 Kyocera Corp 多数個取り配線基板および電子装置
US7087857B2 (en) * 2003-08-12 2006-08-08 Disco Corporation Method of dividing a workpiece in the form of a plate having a layer and a substrate made of different materials
JP2008147234A (ja) 2006-12-06 2008-06-26 Denso Corp 半導体基板のキャップ固着方法
US20090101395A1 (en) 2007-10-23 2009-04-23 Kabushiki Kaisha Toshiba Printed wiring board and electronic apparatus
US20090294928A1 (en) * 2008-05-28 2009-12-03 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Holes In Substrate to Interconnect Top Shield and Ground Shield
JP2010080567A (ja) 2008-09-25 2010-04-08 Kyocera Corp 多数個取り配線基板および配線基板ならびに電子装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5124677A (en) * 1990-08-22 1992-06-23 Harris Corporation Waffleline-configured surface-mount package for high frequency signal coupling applications
JPH10270813A (ja) * 1997-03-27 1998-10-09 Murata Mfg Co Ltd ブレーク溝付きセラミック基板およびこのセラミック基板から製造される電子部品
JP2005033450A (ja) * 2003-07-11 2005-02-03 Murata Mfg Co Ltd 電子部品およびその製造方法
US7492044B2 (en) * 2005-10-06 2009-02-17 Lenovo (Singapore) Pte. Ltd. System and method for decreasing stress on solder holding BGA module to computer motherboard
US20080192446A1 (en) * 2007-02-09 2008-08-14 Johannes Hankofer Protection For Circuit Boards

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3608186A (en) * 1969-10-30 1971-09-28 Jearld L Hutson Semiconductor device manufacture with junction passivation
US5024970A (en) * 1989-06-27 1991-06-18 Mitsubishi Denki Kabushiki Kaisha Method of obtaining semiconductor chips
US20030042596A1 (en) * 2001-09-06 2003-03-06 Crane Stanford W. Semiconductor package
JP2004200631A (ja) 2002-12-13 2004-07-15 Kingpak Technology Inc 光センサパッケージ構造
US7087857B2 (en) * 2003-08-12 2006-08-08 Disco Corporation Method of dividing a workpiece in the form of a plate having a layer and a substrate made of different materials
JP2006041456A (ja) 2004-06-25 2006-02-09 Kyocera Corp 光半導体素子収納用パッケージおよび光半導体装置
JP2006128363A (ja) 2004-10-28 2006-05-18 Kyocera Corp 多数個取り配線基板および電子装置
JP2008147234A (ja) 2006-12-06 2008-06-26 Denso Corp 半導体基板のキャップ固着方法
US20090101395A1 (en) 2007-10-23 2009-04-23 Kabushiki Kaisha Toshiba Printed wiring board and electronic apparatus
CN101420819A (zh) 2007-10-23 2009-04-29 株式会社东芝 印刷线路板以及电子设备
US20090294928A1 (en) * 2008-05-28 2009-12-03 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Holes In Substrate to Interconnect Top Shield and Ground Shield
JP2010080567A (ja) 2008-09-25 2010-04-08 Kyocera Corp 多数個取り配線基板および配線基板ならびに電子装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Chinese language office action dated Jun. 5, 2013 and its English language Statement of Relevance of Non-English References Pursuant to 37 CFR 1.98(a)(3)(i) issued in corresponding Chinese application 201080009867.3.

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11490511B2 (en) * 2018-06-28 2022-11-01 Kyocera Corporation Circuit board and electronic device that includes it

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EP2448377A4 (en) 2014-03-12
EP2448377A1 (en) 2012-05-02
US20110315439A1 (en) 2011-12-29
CN102342185B (zh) 2015-04-22
CN102342185A (zh) 2012-02-01
EP2448377B1 (en) 2015-11-25
WO2010150820A1 (ja) 2010-12-29
JP2011009400A (ja) 2011-01-13
JP5355246B2 (ja) 2013-11-27

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