Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors

Definitions

• This invention relates to alterable threshold memory devices of the kind including a semiconductor substrate, a- memory silicon oxide layer provided on said substrate, a silicon nitride layer overlying said memory silicon oxide layer, an interfacial silicon oxide layer overlying said silicon nitride layer and a gate elec ⁇ trode overlying said interfacial silicon oxide layer.
• MNOS multiple insulator layer structures gen ⁇ erally termed MNOS, which inpludes silicon gate SNOS and SONOS structures.
• PI_ s ⁇ ,_ WTPO primarily to explain the observed MNOS memory character ⁇ istics such as the shift in flat-band voltage with applied gate bias pulse amplitude (write/erase) for various oxide thicknesses in the range 15-27 Angstroms.
• the model teaches that the shape of the energy barrier in an MNOS structure is a function of the applied elec ⁇ tric field, and is as illustrated in Fig. 2.
• Fig. 2 The three regimes shown in Fig. 2 are for an SNOS structure under high, intermediate and low applied positive bias.
• the top portion of this Figure repre ⁇ sents the conduction band shape at very high electric fields where the charge tunnels through only a portion of the oxide.
• the middle portion of Fig. 2 represents the band shape for intermediate electric fields, and the bottom portion represents that for low electric fields.
• the electric field ranges for these three conditions are
• the analytical oxide current obtained by the conventional charge storage models of the Beguwala type is due to modified Fowler-Nordheim tunneling of charge carriers.
• This oxide current may be expressed in the general form:
• Equation (1) For high electric fields, defined by Equation (1), G and F take the values given by:
• Equation (2) For intermediate fields, defined by Equation (2), G and F are given by:
• h Planck's constant
• h h/2 ⁇
• k Boltzmann's constant
• e the electronic charge
• T the absolute ambient temperature of the device
• m the effective electron mass
• Eni. the instantaneous electric field in the nitride.
• Fig. 3 shows the expected variation in saturation threshold voltage with the memory oxide thickness if the write and
• OMPI erase states of an SNOS device were ⁇ dominated by the oxide tunneling current, (as taught by the existing charge storage models).
• oxide tunneling current Starting from a 0 threshold voltage, if one were to apply a gate bias, charges tunnel across the oxide generating a large oxide current. Due to tunneling, charges would accumulate near the oxide-nitride interface and in time the threshold voltage would increase either to a more positive or more negative value depending upon the gate polarity.
• the internal electric fields in the oxide and nitride are altered, thereby decreasing the oxide current and in ⁇ creasing the nitride current. This chain of events continues until the oxide and nitride currents equalize at the saturation threshold voltage.
• the threshold voltage would reach a saturated value at +V , or -V_ p - , respectively, for a positive or negative gate bias polarity.
• the threshold voltage would reach a saturated value at +V , or -V_ p - , respectively, for a positive or negative gate bias polarity.
• An alterable threshold semiconductor memory device of the kind specified is known from published International Patent Application No. WO 81/00790.
• This known device includes a semiconductor substrate having provided thereon a first silicon dioxide layer with a thickness of about 10-15 Angstroms, a silicon nitride layer on the first silicon dioxide layer, a second silicon dioxide layer having a thickness of about 70-100 Angstroms on the silicon nitride layer and a polysili- con gate electrode on the second silicon dioxide layer.
• an alterable threshold semiconductor memory device of the kind specified, characterized in that said memory silicon oxide layer has a thickness lying in the range of 25-40 Angstroms and said interfacial silicon oxide layer has a thickness lying in the range of 30-60 Angstroms.
• an alterable threshold semiconductor memory device according to the invention has the advantage of a high write speed and large memory window.
• a further advantage is a high degree of retention.
• the inventive structure is SONOS (silicon-interfacial oxide-nitride- memory oxide-substrate) , where the interfacial "oxide” encompasses known compositions such as oxynitride, and oxide-oxynitride structures, in addition to oxide itself.
• the invention relates to the multiple dielectric gate structure and is applicable to various memory devices including transistors, capacitors, and charge transfer gates. It has been discovered that the improved memory characteristics of the present invention, which are totally unexpected on the basis of the conventional charge storage models, may be fully explained by using a new concept in charge distribution in multiple die ⁇ lectric devices.
• the concept is that for positive voltages charge is stored not only proximate the memory oxide-nitride interface but also proximate the gate electrode, the charge accumulation near the gate elec- trode being significantly larger than that at the oxide- nitride interface.
• the charge accumulation at the memory oxide-nitride interface is due to conventional oxide current Jo arising from the modified Fowler-
• J-.-.,.. arises due to transportation of holes from the nitride conduction band to the silicon valence band.
• the positions of the charge centroids corresponding to the .two charge accumulations is a function of the number of charge traps and the quantity of charge stored, but in general, as illustrated in Fig. 4, is near the respec ⁇ tive interfaces mentioned above.
• Fig. 1 is an energy band diagram of an SNOS structure showing the current components.
• Fig. 2 is an illustration of SNOS conduction- band shape under an applied field.
• Fig. 3 is a graphical illustration of the predicted relationship, derived from conventional theory, between the current components in the oxide and nitride layers and the SNOS device threshold voltage.
• Fig. 4 illustrates the positions of the charge centroids in accordance with the new charge storage concept used to explain the improved characteristics of the present invention.
• Figs. 5A nd 5B are, respectively, schematic cross-sectional views of an n polysilicon-nitride- oxide-semiconductor (SNOS) memory device and an n polysilicon-oxide-nitride-oxide-semiconductor (SONOS) memory device.
• SNOS n polysilicon-nitride- oxide-semiconductor
• SONOS n polysilicon-oxide-nitride-oxide-semiconductor
• Fig. 6 is a graphical illustration of the observed saturation threshold voltage as a function of oxide thickness for a SNOS device.
• Fig. 7 is a graphical view of the observed maximum saturation threshold voltage as a function of nitride thickness for a SNOS device.
• Fig. 8 is a graphical illustration of the dependence of the initial (memory window) decay rate on the memory oxide thickness for written and erased SNOS devices.
• Fig. 9 is a graphical view of the observed threshold window at three months as a function of oxide thickness for a SNOS device.
• Figs. 10 and 11 are graphical illustrations - of the variation of threshold voltage with pulse width for various memory oxide thicknesses in a SNOS device constructed in accordance with the present invention.
• Fig. 12 is a graphical illustration of the variation of threshold voltage with pulse width in a polysilicon-oxide-nitride-oxide-silicon (SONOS) structure formed in accordance with the principles of the present invention.
• SONOS polysilicon-oxide-nitride-oxide-silicon
• Figs. 13A and 13B are energy band diagrams of the device of Fig. 5A showing the charge traps and cur- rent components for negative and positive gate bias, respectively, in accordance with the present invention.
• Fig. 14 is a schematic cross-sectional repre ⁇ sentation of a three-gate SNOS ner.ory cell which incor ⁇ porates a memory transistor.
• Fig. 15 illustrates an exe-plary memory cell array which incorporates the cell of Fig. 14.
• Fig. 16 is a graphical illustration of the effect of write/erase cycling on char ⁇ e retention.
• a nonvolatile (NV) memory .device comprises an SNOS structure 10 having a preferred memory oxide 12 thickness of 25 to 40 Angstroms.
• Typical prior art memory structures use a thin memory oxide of about 10-20 Angstroms to increase the writing speed, at the expense of decreased retention.
• the structure 10 pro ⁇ vides writing speeds which are comparable to those provided by 10-20 Angstroms memory oxide structures, and also provides excellent retention.
• the NV memory device may comprise an SNOS structure 10 having a relatively thin nitride 13, of thickness as small as 150 to 250 Angstroms.
• Standard prior art practice is to use a nitride thickness of about 400 to 500 Angstroms, despite the fact that in ⁇ creasing the nitride thickness increases the programming voltage.
• the disadvantage of increased programming voltage is accepted because of the conventional belief that going to a thinner nitride greatly reduces the memory window.
• a 150 to 250 Angstrom thin-nitride device 10 permits the use of program voltages of about -_ 10-15 volts, rather than the +_ 25 volts normally used. There is some loss in initial memory window, but the loss is less than half that expected, leaving a practical, useful memory window about 5-7 volts.
• the NV memory device comprises a SONOS structure 100, Fig. 5B, having a thin interfacial oxide layer 14 of about 30-60 Angstroms 'thickness and memory oxide and nitride layers. This structure exhibits both increased writing speeds and increased maximum threshold voltages.
• the SNOS structure 10 shown in Fig. 5A was formed starting from p-type monocrystalline silicon substrates 11 having a conductivity of 10-20 oh ⁇ -cm and a crystallographic orientation (100). Substrate 11 was conventionally etch-cleaned. Then, a layer of silicon dioxide 12 was thermally grown on the cleaned surface of substrate. This was accomplished by subjecting the substrate 11 to oxidation at a temperature of about 750°C using pure oxygen at a flow rate of about 4 liters per minute for a period of about 8-12 minutes. As shown in the various figures, data was obtained for oxide layer 12 thicknesses of up to about 40 Angstroms.
• Silicon nitride layer 13 was then deposited on the oxide 12 by low pressure chemical vapor deposition (hereafter LPCVD) by decomposition of ammonia (NH_) and the silicon-bearing gas dichlorosilane, SiH deliberatelyCl 9 (here ⁇ after DCS), at a pressure in the range of 400-500 milli- torr and a temperature of about 750°C.
• the ratio of am- monia to DCS was about 3.5:1 (ratios of up to 100:1 or more should work) and the nitride deposition rate was about 24 Angstroms per minute.
• the nitride thickness for the exemplary devices ranged between less than 200 Angstroms to about 400 Angstroms, as shown, e.g. , in Fig. 7.
• poly- silicon (polycrystalline silicon) layer 15 was formed by LPCVD using silane at a temperature of about 625°C.
• the thickness of layer 15 typically can be about 3500-4500 Angstroms.
• the samples used here were 4000 Angstroms thick.
• layers 12-15 were etched using con ⁇ ventional photolithographic and etching techniques to form the gate structure 16.
• the surface regions of the substrate 11 were n doped forming the source 17 and the drain 18 while simultane ⁇ ously n doping the polysilicon layer 15.
• the phosphorus deposition was accomplished at a temperature of about 900°C for a period of about 15 minutes.
• the final source and drain junction depths formed in this manner were about 1 micron.
• the structure was subjected to a hydrogen anneal step at atmospheric pressure for about thirty minutes using a hydrogen flow of about ten liters per minute.
• the annealing temperature is determined by the nature of the processing steps following the above- described deposition step. If no high temperature processing is carried out after the nitride deposition, the hydrogen anneal may be accomplished at a relatively - low temperature of about 750°C. On the other hand, if high temperature processing is carried out after the nitride deposition, as in the present case, the hydrogen anneal should take place at a higher temperature. The present examples were annealed for 30 minutes at 900°C. This higher temperature hydrogen anneal repairs degrada ⁇ tion in charge retention caused by high temperature heat treatment.
• a thick layer of silicon dioxide 19 was formed over the entire structure for electrical isolation of the device. Subsequently contact holes were etched through oxide 19 to allow making electrical contacts with the source 17 and drain 18. Then, aluminum metallization was evaporation de ⁇ posited and formed into base contacts 21 and 22 for the source 17 and drain 18, respectively, and metal contact 20 for the polysilicon gate 15. Gate contact 20 was made outside the device active area and is shown schematical- ly in Fig. 5A.
• the process of forming the silicon-oxide- nitride-oxide-silicon (SONOS) structure 100 shown in Fig. 5B follows the steps described above in connection with the forming of SNOS structure 10 with the additional step of forming an interfacial oxide layer 14 after the deposition of the nitride layer 13.
• the interfacial oxide layer 14 was formed at the same temperature and pressure as the nitride by decomposition of nitrous oxide (N O) and DCS.
• the N 2 0:DCS ratio used was 4:1.
• the flow rate of N O was 90 cc. per minute; that of DCS was 22.5 cc. per minute.
• the write and erase curves were generated, for example, by subjecting the devices to various pulse stressing conditions (pulse amplitude and duration) .
• pulse stressing conditions pulse amplitude and duration
• the amplitude of the pulse used was in the range + (10-30) volts, the positive and negative ranges being applicable to the write and erase data respectively, for the exemplary n-channel devices and the pulse duration was in the range of 10 microseconds to 1 second.
• the write and erase curves were generated for a given pulse amplitude by varying the pulse duration in multiples of ten.
• the data to determine the charge retention in the devices was obtained by: (1) initializing the devices by determining the initial write and erase threshold voltages; (2) obtaining retention graphs for the un- cycled devices by storing the devices at an elevated temperature of 100°C for a time of up to 10 seconds and determining the threshold voltages at intervals during
• steps 1 and 4 i.e. obtaining the initial written and erased state threshold voltages, involved applying a +25 volt pulse of ten millisecond duration and a -25 volt pulse of 100 millisecond duration, respectively, to the gates of the memory devices.
• Source 17, drain 18 and substrate 11 (Fig. 5) were all tied to the ground during this initial ⁇ ization.
• the data obtained in the above fashion has been reproduced herein in the form of various graphical illustrations which will now be described in detail.
• Fig. 3 depicts, for a given positive or negative applied gate voltage, the oxide and nitride currents, and the resulting maximum threshold voltages.
• This equilibrium point is the maximum positive (or negative) threshold associated with Toxl., ' i.e., VT_l, (or -VT m l, ) .
• This eq ⁇ uilibrium cor- responds to the attainment of charge Q, , distributed ad ⁇ jacent the oxide-nitride interface. See Fig. 4. Under this as is oxide tunneling current dominance, there is no charge Q_ ' at the gate-nitride interface.
• the oxide thickness is increased to T _, the oxide current decreases to Jox2sky and the maximum predicted positive and negative thresholds decrease to V render and - T 2 respectively.
• T K NI ⁇ o T.N._I is the nitride thickness
• X is the charge centroid of Q and is independent ⁇ f T NI Q is the quantity of stored charge ⁇ -N ⁇ _I is the dielectric constant of the silicon nitride and € is the permittivity of free space.
• Figs. 6 and 7 show maximum threshold data obtained for devices 10 fabricated as described above.
• the maximum threshold voltage is shown as a function of memory oxide thickness (Fig. 6) and silicon nitride thickness (Fig. 7).
• Fig. 6 for erasing, the maximum negative threshold voltage decreases with increasing memory oxide thickness. This behavior is consistent with the predictions of the conventional two-current component model, discussed above.
• the Fig. 6 data show the maximum positive threshold actually increases slightly as the thickness of the memory oxide is increased. This result is inconsistent with the predictions of the conventional two-current component model.
• the maximum negative threshold voltage increases with increasing nitride thickness. This behavior is predicted by equation (4). However, during writing the maximum positive threshold voltage is essentially constant, in contrast to the increasing threshold predicted by equa ⁇ tion (4) .
• Figs. 8 and 9 For memory oxide thickness values larger than 40 Angstroms, operating (erase) speeds decrease, the memory window is narrowed, and the written state deteriorates. At values smaller than 25 Angstroms, the device approaches the characteristics of the prior art, thin oxide devices. For example, the decay rate in ⁇ creases to the undesirable prior art levels.
• the thick memory oxide responsible for this enhanced retention is also responsible for decreased operational speeds. For this reason, a major effort of the current technology is to decrease the memory oxide thickness to enhance operating speeds, although this is done at the expense of retention.
• the erase speeds for the thicker, 25-40 Angstrom memory oxide are slower than for thinner oxides. See Fig. 10. However, the write speeds are essentially independent of the memory oxide. See Fig. 11.
• the exemplary devices 10 which incorporate a relatively thick, 25-40 Angstrom memory oxide provide the enhanced nonvolatility shown in Figs. 8 and 9 without loss of write speeds, as shown in Fig. 11. Such devices are particularly suitable for application in EAROMs (elec ⁇ trically alterable read-only memories) or other devices where writing speed is crucial.
• Fig. 16 The retention of thick memory oxide SNOS devices is further demonstrated in Fig. 16.
• the retention of this thick memory oxide device is about two decades longer than that of otherwise equivalent prior art devices.
• device performance is also improved by using a thin silicon nitride layer 13.
• writing or erasing typically requires +_20-25 volts at the gate electrode of the memory device, compared to the 5 volt signals utilized for control and logic functions.
• Typical prior art memory devices utilize a silicon nitride thickness of about 400 Angstroms and require programming voltages of about 25 volts. Decreasing the silicon nitride thickness to, e.g., 200 Angstroms would decrease the required programming voltage to about 12-13 volts, as calculated by (200/400) x 25v. The conven ⁇ tional model predicts that such a thin nitride would cause a much-reduced initial memory window, However, Fig.
• nitride thicknesses of less than 400 Angstroms and, specifically, thicknesses to about 150 Angstroms can be used to decrease the programming voltage while retaining a usable memory window.
• nitride thickness of 150 to 250 Angstroms nonvolatile memory devices can be programmed with voltages of +_1° ⁇ 15 volts, rather than the +_25 volts now in industry use.
• SONOS devices with a thin interfacial oxide layer 14 exhibit both increased writing speed and a higher thres ⁇ hold voltage in*the written state.
• the preferred thick ⁇ ness of the interfacial oxide is in the range of 30-60 Angstroms. Below 30 Angstroms, the device characteris ⁇ tics begin to approach those of a SNOS device. Beyond 60 Angstroms, the erase speed is reduced, making the interfacial oxide less desirable. For erasing, the SONOS device is slower than the conventional SNOS device and the magnitude of the maximum threshold voltage is smaller. As mentioned previously, this is no hindrance for memory devices, such as EAROMs, for which the erase speeds are not critical.
• Fig. 13A illustrates the application of a negative gate bias, -V (hereafter also called “erasing”);
• Fig. 13B illustrates the application of a positive gate bias, ' +Vv__ ⁇ (hereafter also called
• one current component is due to holes tunneling from the accumulated p-type substrate through the thin memory oxide and into the gate silicon nitride.
• a second current component is J . , the nitride hole current. J . results from the holes in the nitride being driven by -V to the gate.
• the third component, J , is the hole current to the gate, that is, the interface current due to holes leaving the nitride and entering the valence
• the oxide tunneling current J . is larger than the nitride hole current J , positive charge accumulates near the oxide-nitride interface under the negative gate bias. However, there is no appreciable charge accumulation near the gate, since there is no energy barrier to holes entering the poly- silicon gate. As a result, there is a single centroid of charge near the oxide-nitride interface. As charge accumulates near the oxide-nitride interface, the inter ⁇ nal electric fields in the oxide and nitride are altered, decreasing the dominant oxide tunneling current and increasing the nitride hole current. This continues until the oxide and nitride currents equalize, at the saturated negative threshold. Increasing the oxide thickness decreases the oxide tunneling current and decreases the saturated negative threshold.
• the three-current model predicts the same erase behavior predicted in Fig. 3 for the conven- tional two-current model. These predictions are substan ⁇ tiated by the erase behavior data of Figs. 6-8, 10 and 12.
• the situation is much different for the positive gate bias, write situation.
• a positive gate bias the surface of the silicon substrate is inverted. Tunneling current is now domi ⁇ nated by electrons tunneling from the inverted silicon surface through the oxide and into the nitride.
• This component is designated J .
• the second component is again J , , the hole current in the silicon nitride.
• the third component, the gate interface current presents two possibilities. The first is the transport of elec ⁇ trons from the nitride into the conduction band of the polysilicon gate.
• the buildup of charge near the nitride-poly- silicon gate interface lowers the electric field near the oxide-nitride interface and thereby reduces the accumulation of negative charge at that interface.
• the electric field decreases in the nitride bulk, the field at the nitride-polysilicon gate interface increases, This in turn increases the hole injection from the gate.
• the charge buildup in the nitride and the increase in injected gate current J will continue until the bulk nitride hole current, J . , and the injected gate current are equal.
• this new, three current component model predicts a charge accumu ⁇ lation Q-. distributed adjacent the memory oxide-silicon nitride interface and a dominant (significantly larger) charge accumulation Q_ distributed near the nitride- polysilicon gate interface.
• This model accounts for the unexpected write behavior exhibited by the devices 10 and 100.
• the write threshold vs. nitride data of Fig. 7. With the dominant charge centroid Q 2 near the gate electrode, i.e., at a relatively fixed distance from the electrode which is independent of the nitride thickness, and with a fixed distribution, the voltage needed to neutralize the field due to the trapped charge will be the same no matter what the nitride thickness is.
• the interfacial oxide layer 14 acts as a tun ⁇ neling barrier to the holes from the polysilicon gate and decreases the hole current from the gate (J , ).
• OMPI causes greater build up of negative charge at the nitride- interfacial oxide boundary thereby enlarging the memory window (i.e., increasing the maximum write threshold voltage). Since J , is now much smaller than the nitride hole current J , , this larger difference in currents causes a faster build up of charge at the nitride- interfacial oxide boundary which in turn enables faster writing.
• EAROM APPLICATION As examples of the application of the memory transistor of the present invention, consider a three- gate EAROM memory cell comprised of series-connected field effect transistors.
• the exemplary EAROM is the subject of international patent application No. PCT/US81/ 01762 in the name of the present Applicant.
• the three gate EAROM cell 110 is shown in cross-sectional form in Fig. 14 with various electrical connections shown schematically.
• the cell comprises a series connection of three transistors, Q, , Q-_ and Q.,.
• Q--Q-. are termed transistors although they essentially are field-effect transfer gates or capacitors.
• the n-channel cell 110 has a p-type sub ⁇ strate 111, with n doped regions 117 and 118.
• Field effect gates/capacitors/transistors Q, and Q ⁇ have gate electrodes 122 and 123 corresponding to write and read electrodes V and V respectively.
• MNOS transistor Q freely between Q, and Q-.
• n doped region 117 is connected to bit line electrode V via contact layer 124, and n region 118 is electri- cally common with electrode V .
• Addressing of the exem ⁇ plary three-gate EAROM cell is by the bit line V_ and word write lines V with erasing and writing being
• OMPI performed by a common memory line V and reading being done by a low voltage memory line signal and a read line V is. command signal.
• the cell 110 was constructed with a memory oxide thickness within the range 30-36 Angstroms and a silicon nitride thickness of about 380-400 Angstroms.
• the written threshold VTl was about +(7- 8) volts
• the erased threshold VT0 was about -2 volts, with a programming voltage of +25 volts (WRITE) or -25 volts (ERASE).
• the cell is readily fabricated with a- thin silicon nitride layer 113.
• a 200 Angstrom silicon nitride layer 113 pro ⁇ vides VTl of about +(6-7) volts and VT0 of about -1 volts for a conventional 10-20 Angstrom thick memory oxide 112A.
• the resulting programming voltage is about 12 volts.
• the programming voltage is again about +12 volts and VTl and VT0 are within the ranges given above.
• transistors C- and Q-. are enhancement mode, n-channel devices which conduct when the voltages at their respective gate electrodes V and V exceed their +1 volt gate-to-source threshold voltage. Trans ⁇ istor Q ⁇ .is actuated and programmed through the gate electrode V provoke.
• all transistors Q ⁇ -Q 3 must be on. This is defined here as the logic "0" state of the cell.
• the logic "1" state is defined as the lack of a conduc- tive path between V ⁇ and V ⁇ .
• Fig. 14 also shows functional circuits for programming and reading the cell state.
• Node V g is normally coupled to the system ground, and bit node V is at either ground potential or +5 volts, depending on the position of the switch SW.
• the resistance of resis ⁇ tor R is sufficiently high that the existence of a conductive path between nodes V and V g places node V-, at substantially ground potential.
• V are not constrained (i.e., may be 0V or 5V).
• the high voltage pulse on V shifts the threshold from any existing level to the VTO ERASE state.
• the following truth table provides the various voltage combinations for writing and erasing the cell 110.
• VTl state consider example 3 in Table II.
• a high duty cycle of approximately ten, 1 millisecond WRITE pulses is ap r p xr lied to VM_ r coincident with +5 volts on V_P_i and 0 volts on V_-_> and V ⁇ . a.
• the 0 volt level at V a_. prevents conduction through Q ⁇ , while the combination of voltages
• V receives a +5 volt signal. With both the impurity region 117 and the gate 122 at +5 volts, Q_ remains non- conducting. The absence of conductive paths through Q, or Q-j effectively floats memory transistor Q- and prevents alteration of the erased threshold voltage of Q 2 .
• the multiplicity of short, one millisecond pulses are used to permit controlling writing. That is, initially the application of the WRITE voltage drives the substrate surface into deep depletion. The WRITE voltage therefor is applied primarily across the sub ⁇ strate, and insufficient voltage is applied across the dielectric layers to provide threshold voltage-changing charge carriers to the dielectric. Without the relative ⁇ ly short pulses, however, electron-hole generation would shortly collapse the deep depletion region and write the device to VTl regardless of the state of V and V w . In short, the high duty cycle ensures that V will be written to (remain at) VTO for all combinations of V_ and V except 0,1.
• the diffusion region 117 supplies electrons to the channel of Q Uber to instan- taneously collapse the deep depletion region there.
• the gate bias at V. applies sufficient voltage across the dielectric layers to write Q ⁇ to its VTl threshold.
• the READ mode is performed with a +5 volt command signal on V R, a +5 volt address signal on VW, a high impedance +5 volt signal on V , and a 0 volt READ interrogation signal on V .
• VTl threshold Example 3
• Q- is not conducting because the READ voltage on V is below VTl. Consequently, node V is not grounded to node V . This corresponds to the logic "1" state for the cell.
• the VTO thres ⁇ hold the READ voltage on V.. is sufficient to cause Q to conduct.
• the +5 volt high impedance voltage on bit node V R is grounded through node V_.
• the presence of 0 volts on node V composition during the read mode corresponds to a logic "0" state for the cell.
• each pair such as XX, X and XY,YY has a common line V_ and common bit line V , with line V render also being shared by adjacent columns.
• V and V reserve connect to transistors Q. in respectively
• the Fig. 15 array is designed as a VLSI inte- grated circuit layout.
• lines V ⁇ are formed by doped substrate regions
• bit lines V are metallic conductors
• the read word and memory lines are doped polysilicon.
• the Fig. 15 array can be expanded- to an M row by N column array.
• M row address lines and N column address lines are necessary, respectively, to access the M rows of structural cells and the N column lines.
• the array is block erased, as described, pre ⁇ viously, by applying a negative programming voltage to
• the Fig. 15 organization permits selective pro ⁇ gramming of the cells of a pair using the associated single V_. line and the two V,.. lines associated with the cell pair. For example, if cells XX and YX are to be written 0 and 1, lines V and V are brought to 0 u l W l volts and line V is brought to +5 volts as the positive
• ⁇ 2 WRITE pulses are applied to lines V .
• writing these cells to 1 and 1 is done by apply ⁇ ing the same pulse sequence except that V is also brought to +5 volts.
• the adjacent columnar pair XY,YY are unaffected by the P7RITE sequence so long as V render is at
• bit line signals are applied to line
• V_, and V-, bit line voltages are sensed for the B l B 2 presence of a ground potential created when a conductive path is formed through Qnd and the cell to line V ⁇ .

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• 1982
  • 1982-05-07 WO PCT/US1982/000600 patent/WO1982004162A1/en not_active Ceased
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