WO1984003997A1 - Dispositif ldmos a auto-alignement et son procede de fabrication - Google Patents

Dispositif ldmos a auto-alignement et son procede de fabrication Download PDF

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Publication number
WO1984003997A1
WO1984003997A1 PCT/US1984/000171 US8400171W WO8403997A1 WO 1984003997 A1 WO1984003997 A1 WO 1984003997A1 US 8400171 W US8400171 W US 8400171W WO 8403997 A1 WO8403997 A1 WO 8403997A1
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WO
WIPO (PCT)
Prior art keywords
region
forming
impurity type
dmos
area
Prior art date
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Ceased
Application number
PCT/US1984/000171
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English (en)
Inventor
Antonio R Alvarez
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Motorola Solutions Inc
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Motorola Inc
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Publication of WO1984003997A1 publication Critical patent/WO1984003997A1/fr
Anticipated expiration legal-status Critical
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1404—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase
    • H10P32/1406—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/031—Manufacture or treatment of isolation regions comprising PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/30—Isolation regions comprising PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 

Definitions

  • the present invention relates, in general, to the field of double diffused MOS (DMOS) transistors and to integrated circuits utilizing the same. More particularly, a lateral DMOS (LDMOS) device in accordance with the present invention exhibits an inherently self-aligned channel region allowing for the integration of LDMOS devices having a relatively shorter channel length and, hence, higher gain and superior control than previously described devices. Concomitan ly, the shorter channel length employed provides for the integration of smaller devices and, therefore, a greater number of even faster devices for a given die area.
  • the method of the present invention is fully compatible with standard bipolar processing sequences and eliminates concern over alignment tolerances while simplifying the gate photostep.
  • OMPI dopant concentration profile and the concentration profile of the subsequent N type dopant which forms the NPN emitter concurrently with the formation of the DMOS source and drain.
  • the bulk channel diffusion for the DMOS well is performed followed by the NPN base diffusion, during which minimal oxide is grown in order to mask all P type diffusions from subsequent N type deposition.
  • the patterning of the oxide is carried out in two stages by first selectively opening oxide windows for all N type diffusions with oxide thicker than base oxide, followed by the selective opening of windows for the vertical NPN emitter and DMOS source. In patterning the DMOS source, oxide is removed over the bulk channel diffusion between the source and drift region as well as overlapping into the drift region.
  • the oxide is partially removed over the lateral bulk channel diffusion and part of the drift region, but remains thick enough to mask these regions from the subsequent DMOS source diffusion.
  • the DMOS channel length is determined by the difference between the emitter diffusion and the P-well diffusion, since the oxide window later opened for the DMOS source diffusion or implantation .is essentially the same window initially opened for the P-well formation.
  • DMOS devices fabricated in accordance with this process exhibit a gain constant of approximately 1300, however, still higher gain constants are nonetheless highly desirable.
  • a method and an integrated circuit produced thereby which includes a self-aligned DMOS device having a desired channel length formed by a process comprising the steps of providing a semiconductor substrate of a first impurity type, the substrate presenting a major surface thereof. Thereafter, forming a layer of a second impurity type opposite to the first impurity type on the substrate major surface. Firstly disposing to a first predetermined depth within the layer a region of the first impurity type, the region forming a DMOS well and the first impurity type having a first diffusion rate.
  • an integrated circuit including a self-aligned DMOS device within a semiconductor layer of a given impurity type may be formed by a method comprising the steps of forming an insulating layer overlying the semiconductor layer and removing a predetermined portion of the insulating layer forming an aperture therein.
  • FIG. 1A is a simplified cross sectional view of a portion of an integrated circuit to be fabricated in accordance with the present invention and illustrating the initial stage in the formation of a DMOS P-well through an oxide window by, for example, implantation of boron;
  • FIG. IB is a simplified cross sectional view of that portion of the integrated circuit of FIG. 1A illustrating the initial stage in the formation of a pair of DMOS source regions by, for example, implantation of arsenic through the P-well oxide window of FIG. 1A having a portion thereof previously masked by a photoresist layer?
  • FIG. 1C is a simplified cross sectional view of that portion of the integrated circuit of FIGs. 1A and IB illustrating a completed pair of DMOS devices after subsequent driving in of the P-well and source regions to set the device channel lengths and further illustrating the contact bias and overlying metalizations; and
  • FIG. 2 is a graphic illustration of the gain constant [( V GS ⁇ v ⁇ ) : V ⁇ Dsl achievable in a device in accordance with the present invention in comparison to certain prior art devices not having the desired short channel characteristics attendant those fabricated as herein disclosed.
  • fabrication of a self-aligned LDMOS device in accordance with the present invention begins with the utilization of a substrate 12, which in the embodiment hereinafter described comprises P-semiconductor material. Upon a major surface of substrate 12 is thereafter grown an epitaxial layer 14. Epitaxial layer 14 comprises N-semiconductor material. Thereafter, in a conventional manner, an oxide window 20 is formed on epitaxial layer 14 by patterning of an oxide 18. Oxide window 20 may be formed by any conventional process and is utilized in the forming of P-well 16.
  • P-well 16 is formed by implantation of boron through oxide window 20.
  • a pre-implant oxide of approximately 1,000 angstroms (1000 A) may be formed within oxide window 20 prior to the boron implantation.
  • P-well 16 is formed by implantation at 70 keV resulting in a P-well 16 region of approximately 2200 angstroms (2200 it) .
  • P-well 16 will thereafter partially extend underneath oxide 18 adjacent the periphery of oxide window 20. At this time, it may also be necessary to perform an anneal and drive-in of the silicon surface as a result of the boron implantation step.
  • photoresist 22 is patterned such that a source mask 24 is disposed within oxide window 20 and overlies P-well 16. That portion of photoresist 22 not within oxide window 20 is shown merely as forming the basis for attachment of source mask 24, as oxide 18 alone can mask 24 will mask against the subsequent arsenic implant.
  • arsenic is implanted through the same oxide window 20 depicted in FIG. 1A such that source implant 26 is formed within P-well 16.
  • this implant will be done at 100 keV such that an initial channel length Lj_ is set.
  • Channel length L ⁇ is then presently the distance between source implant 26 and the current edge of P—well 16.
  • channel length j_ will be somewhat less than the desired channel length ultimately formed in the self-aligned LDMOS device of the present invention.
  • FIG. 1C a self-aligned LDMOS structure 10 in accordance with the present invention is shown. That portion of the integrated circuit illus ⁇ trated in FIG. 1C illustrates a simplified construction of a pair of LDMOS devices in the region previously disclosed in FIGs. 1A and IB.
  • the self-aligned LDMOS structure 10 of FIG. 1C follows in processing sequence that portion of the integrated circuit illustrated in FIG. IB subsequent to a removal of photoresist 22 including source mask 24 and an annealing drive-in, and possible oxidation of the implant of P-well 16 and source implant 26.
  • the channel length of self-aligned LDMOS structure 10 is determined. In FIG. 1C, this channel length is illustrated as Lf. As arsenic is a heavier ion than boron, the boron will diffuse more rapidly than arsenic during a subsequent drive-in step. Thus, by driving in both P-well 16 and source implant 26, the channel length of a self-aligned LDMOS structure 10 will increase from ⁇ - of FIG. IB to Lf of FIG. 1C. Thus, the difference in the coefficient of diffusion of the two materials sets the device channel length. By controlling the length of the drive-in time of the implants a consistently reproducible and small channel length Lf may be obtained.
  • drain 28 which may be formed in a conventional manner according to standard bipolar processing sequences.
  • a plurality of isolation regions 30 isolate self-aligned LDMOS structure 10 from adjacent devices.
  • a source contact 32 may be formed within source implant 26 to establish contact to source electrode 40.
  • P-well contact 34 provides contact between P-well 16 and P-well electrode 44.
  • a thin gate oxide 46 overlies the DMOS channel for the provision of gate electrode 38. Gate oxide 46 is typically thermally
  • OMPI grown and provides a clean, highly stable insulation for device operation.
  • Insulating layer 36 serves to isolate source electrode 40, drain electrode 42 and P-well electrode 44.
  • FIG. 2 a comparison between a prior art LDMOS device and a self-aligned LDMOS device in accordance with the present invention is shown.
  • the gain constant for these respective devices is plotted as [(VQ S - V ⁇ ) : .
  • a plot for a prior art LDMOS device having a gain constant of approximately 524 is shown as compared to the self-aligned device of the present invention exhibiting a gain constant of approximately 1618.
  • the self-aligned LDMOS structure 10 of the present invention is process compatible with standard linear processing and produces a high gain LDMOS device that is relatively impervious to photolithographic process variations.
  • the resultant device is faster than the prior art non-self-aligned LDMOS devices as parasitic gate-source capacitance is reduced, while gain is concomitantly increased. Since the gain is greater, for a given gain level, the gate oxide overlying the device channel area can be reduced. This reduction in the gate oxide area translates into higher yields because gate oxide defects have been found to be a major yield limiter in MOS processing.
  • a ⁇ 3:1 increase in gain has been achieved utilizing the self-aligned process herein disclosed. This results in a factor of three reduction in gate oxide area. Assuming Poisson yield statistics, a corresponding 10% increase in yield can be expected due to this reduction in gate oxide defects.
  • the present invention provides for a shorter channel device resulting in an overall smaller structure exhibiting increased device speed.
  • the self- aligned LDMOS device and method of the present invention produces a higher gain constant with a concomitant lower "ON" resistance and further eliminates concern for alignment tolerances while resulting in improved process reproducibility.
  • the device and method of the present invention requires an extra photostep and implant. However, the advantages attendant this extra processing step far outweigh any disadvantages attendant its utilization.

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Dispositif à LDMOS à auto-alignement, son procédé de production et circuit intégré l'incorporant, présentant une région de canal à auto-alignement inhérent permettant d'obtenir une intégration de dispositifs à LDMOS dont la longueur du canal est relativement courte (Lf) et, partant, un gain plus élevé que les dispositifs décrits jusqu'ici. La longueur du canal (Lf) du dispositif est déterminée par la différence de coefficient de diffusion entre le puits P (16) et l'implant de source (26). Celui-ci (26) est obtenu au travers de la même fenêtre d'oxyde (20) utilisée pour former le puits P (16). La longueur de canal (Lf) plus courte résultante permet l'intégration de dispositif plus petit et, partant, d'un nombre plus élevé de dispositifs plus rapides pour une surface donnée de la matrice. Le procédé de la présente invention est totalement compatible avec les séquences de traitement bipolaire standard et élimine tout soucis par rapport aux tolérances d'alignement, tout en simplifiant l'étape de photo-gravure de porte.
PCT/US1984/000171 1983-04-04 1984-02-08 Dispositif ldmos a auto-alignement et son procede de fabrication Ceased WO1984003997A1 (fr)

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US48211083A 1983-04-04 1983-04-04

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0099175A3 (fr) * 1982-06-21 1986-04-23 Eaton Corporation Transistor à effet de champ comportant une électrode de porte sous-divisée
WO1998049732A3 (fr) * 1997-04-28 1999-02-04 Koninkl Philips Electronics Nv Dispositif transistor mos lateral
US6207518B1 (en) * 1999-03-12 2001-03-27 Sanyo Electric Co., Ltd. Method of manufacturing semiconductor device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3764396A (en) * 1969-09-18 1973-10-09 Kogyo Gijutsuin Transistors and production thereof
US3926694A (en) * 1972-07-24 1975-12-16 Signetics Corp Double diffused metal oxide semiconductor structure with isolated source and drain and method
US4001048A (en) * 1974-06-26 1977-01-04 Signetics Corporation Method of making metal oxide semiconductor structures using ion implantation
US4055884A (en) * 1976-12-13 1977-11-01 International Business Machines Corporation Fabrication of power field effect transistors and the resulting structures
US4344081A (en) * 1980-04-14 1982-08-10 Supertex, Inc. Combined DMOS and a vertical bipolar transistor device and fabrication method therefor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3764396A (en) * 1969-09-18 1973-10-09 Kogyo Gijutsuin Transistors and production thereof
US3926694A (en) * 1972-07-24 1975-12-16 Signetics Corp Double diffused metal oxide semiconductor structure with isolated source and drain and method
US4001048A (en) * 1974-06-26 1977-01-04 Signetics Corporation Method of making metal oxide semiconductor structures using ion implantation
US4055884A (en) * 1976-12-13 1977-11-01 International Business Machines Corporation Fabrication of power field effect transistors and the resulting structures
US4344081A (en) * 1980-04-14 1982-08-10 Supertex, Inc. Combined DMOS and a vertical bipolar transistor device and fabrication method therefor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0099175A3 (fr) * 1982-06-21 1986-04-23 Eaton Corporation Transistor à effet de champ comportant une électrode de porte sous-divisée
WO1998049732A3 (fr) * 1997-04-28 1999-02-04 Koninkl Philips Electronics Nv Dispositif transistor mos lateral
US6207518B1 (en) * 1999-03-12 2001-03-27 Sanyo Electric Co., Ltd. Method of manufacturing semiconductor device

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Publication number Publication date
EP0139663A1 (fr) 1985-05-08

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