WO1991007775A1 - Structure a circuits hybrides et procedes de fabrication - Google Patents

Structure a circuits hybrides et procedes de fabrication Download PDF

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Publication number
WO1991007775A1
WO1991007775A1 PCT/US1990/006703 US9006703W WO9107775A1 WO 1991007775 A1 WO1991007775 A1 WO 1991007775A1 US 9006703 W US9006703 W US 9006703W WO 9107775 A1 WO9107775 A1 WO 9107775A1
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WO
WIPO (PCT)
Prior art keywords
layer
interconnect
high density
over
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1990/006703
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English (en)
Inventor
John J. Reche
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Polycon
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Polycon
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Filing date
Publication date
Application filed by Polycon filed Critical Polycon
Publication of WO1991007775A1 publication Critical patent/WO1991007775A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Definitions

  • the present invention relates to the field of hybrid circuits, and more particularly to hybrid circuits for interconnecting unpackaged integrated circuits.
  • Hybrid circuits of various forms are well-known in the prior art. Such circuits have been generally used for the high density packaging of active and passive devices, more recently integrated circuits, discreet components and the like in a high density configuration. The densities that normally have been obtainable in the more conventional hybrid circuits are much higher than obtainable with packaged devices using conventional integrated circuit technology.
  • SMT surface mount technology
  • very large scale and larger integrated circuits generally have a bad yield problem which may only be overcome, at least in part, by providing on chip redundancy.
  • a common approach to the yield problem is to provide redundancy for each functional part of the circuit, thereby increasing the required chip area by approximately 100 percent . While such redundancy can dramatically increase the yields by now requiring only one out of two of each functional block circuits to operate, rather than one out of one which would be required without redundancy, the effect of the redundancy is not only to. increase chip size, but- also to cause relatively long interconnects which substantially slow down the circuit because o the resulting relatively high parasitic capacitance.
  • HDMI technology is somewhat of a mix, in some ways resembling integrated circuit fabrication techniques and in other ways somewhat resembling printed circuit board techniques .
  • conductor line widths are beginning to approach those used in at least older integrated circuit designs, and bonding techniques used to interconnect the chips to the HDMI are those typically used in conventional integrated circuit packaging.
  • the materials used for the insulative layers, typically polymers, and the number of cross-overs required are more similar to that found in printed circuit board fabrication, as opposed to the silicon-oxide layer and the deposited metal interconnect layer of typical integrated circuits .
  • HDMIs various materials may be used for the substrate, including metals, semi-conductors and insulators, each having various advantages and disadvantages for such use.
  • One material of particular interest is silicon, as it obviously has the same thermal expansion as the silicon integrated circuit to be mounted thereon, has reasonable heat transfer
  • the fabrication of an HDMI differs from integrated circuit fabrication in that, as stated before, the various insulative layers in the high density multi-chip interconnect are generally polymer layers not oxide layers .
  • Hybrid circuit structures and methods of fabrication particularly suitable for the fabrication of high density multi ⁇ layer interconnects utilizing silicon substrates are disclosed.
  • a layer of aluminium oxide is put down over the silicon substrate, typically having an oxide layer thereover, which layer of alumina acts as a blocking barrier to any subsequent plasma etching process for etching polymer layers thereover during the subsequent high density multilayer interconnect fabrication steps.
  • Various representative high density multi-layer interconnect structures on silicon substrates and methods of forming the same are disclosed, including the inclusion of an adhesion enhancement layer over the layer of alumina to- enhance the adhesion of a polymer which would not otherwise adhere well directly to the layer of alumina.
  • Figure 1 is a cross-section illustrating the etching of a silicon substrate commonly encountered during the plasma etching of a polymer layer thereon.
  • Figure 2 is a schematic diagram illustrating the blocking effect the present invention layer of alumina over the substrate has on the typical fluorine ion plasma etch used to etch polymer layers thereover.
  • Figure 3 is a schematic diagram similar to Figure 2, though further illustrating the inclusion of an adhesion enhancement layer, preferably a silicon-oxide layer, over the layer of alumina.
  • an adhesion enhancement layer preferably a silicon-oxide layer
  • Figure 4 is a schematic diagram similar to Figures 2 and 3, * though further illustrating a patterned ground plane as part of the structure illustrated in the cross-section thereof.
  • FIG. 1 a schematic cross-section of a portion of a silicon substrate illustrating the problem encountered with prior art fabrication techniques for HDMIs may be seen.
  • silicon substrates 20 having a silicon-oxide layer 22 thereon are appropriate substrates for use in the fabrication of HDMIs. Additional steps in the fabrication process include putting down a thick layer of polymer 24. Thereafter a metalization layer is put down over the polymer layer 24 and patterned, and one or more additional sets of thick polymer and patterned metalization layers are formed thereover. At some point or points in the process, it is common to locally etch through the polymer layer 24 to expose a local region of a substrate.
  • etching of the polymer normally is accomplished with the use of a fluorine ion bearing plasma etching process .
  • Such an etching process while etching the polymer, will also etch the oxide layer 22 and the silicon itself at a relatively high rate. Consequently, in order to achieve the complete removal of the polymer regions desired, some slight over etch will normally be required, resulting in a substantial pit or crevice 26 being formed in the silicon substrate.
  • the substrate 20 is a silicon substrate having a layer of silicon-oxide 22 thereon.
  • a layer of alumina 28 is put down over the silicon-oxide.
  • the alumina provides a mask or barrier for the fluorine ion bearing plasma etch so that in any subsequent etching processes etching windows in the first polymer layer 24, the etching process will be stopped by the alumina so that neither the silicon-oxide layer 22 on the substrate nor the silicon substrate 20 itself will be disturbed by the etching process.
  • the layer of alumina may be put down by sputtering the same onto the oxide layer, or alternatively, may be formed by putting down a layer of aluminum and oxidizing the same in an oxidizing environment as desired. In either event however, the resulting layer of alumina will stop the plasma etching process, protecting the silicon-oxide and the silicon therebelow.
  • a layer of alumina of approximately 2000 Angstroms in thickness to assure the desired integrity of the layer for blocking purposes, though a layer in the range of approximately 500 to 10,000 Angstroms is suitable.
  • the adhesive between the polymer layer 24 and the alumina layer 28 will not be adequate.
  • the adhesion of a benzocyclobutene to the layer of alumina is inadequate to provide a useful and reliable HDMI. Consequently, in such situations in accordance with the present invention, an additional layer is put down which additional layer is selected to provide adhesion by to the aluminum on one side thereof, and to the polymer on the other side thereof.
  • Figure 3 wherein the silicon substrate 20 with the silicon-oxide layer 22 and the alumina layer 28 thereon also includes a silicon- oxide layer 30 on the alumina for adhesion purposes .
  • the silicon-oxide layer 28 being subject to rapid etching of the plasma etch, will be etched thereby during the etching of the polymer layer 24, though the integrity of the .oxide layer for adhesion purposes under the remaining polymer layer 24 will be unaffected by the etching process, thereby achieving the desired adhesion enhancement.
  • Structures of the present invention may take various forms.
  • a conductive ground plane over the substrate before forming the various layers of polymer and metalized interconnect thereover.
  • Such ground planes may be continuous ground planes over the substrate, or alternatively, patterned ground planes as desired.
  • the present invention of course is readily applicable to these structures as well.
  • a silicon substrate 20 with an oxide layer 22 thereover is processed first by providing a layer of alumina 28 over the oxide layer 22. Then, the optional additional layer for adhesion enhancement 30 is provided. Thereafter, referably a patterned ground plane, layer of metal 32 is provided.
  • a window is opened through the polymer layer 24 to expose the ground plane layer 32 to provide contacts thereto, other areas of the polymer layer 24 also being opened (not shown) by the plasma etch process, which process is stopped as explained before, by the layer of alumina 28.
  • This structure as well as that shown in Figure 2 and 3 are of course exemplary only of the various ways the present invention may be utilized, the various figures being schematic only .and illustrating exemplary structures only up to the first relatively thick layer of polymer, even though, depending upon the specific fabrication process used, a patterned metalization layer as. well as additional layers of polymer and patterned metalization may be built up thereover before any windows in the layer 24 are opened, or alternatively, windows in layer 24 may be opened at various stages in the processing.
  • alumina aluminum oxide
  • other materials may be used for the protection of the substrate, provided such materials have the desired properties .
  • the desired properties include chemical resistance to hydrofluoric ions (HF ions) in weak liquid solutions, e.g. a dilute (typically approximately 2%) aqueous solution of HF, or ions in a plasma.
  • HF ions hydrofluoric ions
  • aluminum oxide is impervious to both when properly sputtered, so is hafrium oxide and tungsten trioxide.
  • Other desired characteristics of such materials include being a good electrical insulator, and having good adhesion to the substrate and good adhesion to the subsequent polymer layer to be deposited thereon.
  • the materials may be deposited by sputtering deposition, ion beam or any other vacuum deposition technique, as well as by other techniques.
  • the material may be formed from sol-gels or other organic-metallic (or metallic-organic) materials.
  • Such compounds consist of organic molecules bonded to metal molecules (organic- metallics, sometimes referred to as metallic-organics) .
  • organic- metallics sometimes referred to as metallic-organics
  • Heating the organic-metallic in a oxidizing atmosphere results in metallic oxides being formed and left behind.
  • oxides similar to the ones mentioned for vacuum deposition namely aluminum oxide, hafrium oxide and tungsten trioxide may be formed.

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Des structures à circuits hybrides et des procédés de fabrication sont particulièrement utiles pour fabriquer des interconnexions à couches multiples de haute densité avec des substrats en silicium. Selon le procédé, une couche d'oxyde d'aluminium (28) est déposée sur le substrat en silicium (20), typiquement recouvert d'une couche d'oxyde (22). La couche d'oxyde d'aluminium forme une barrière de blocage pendant des procédés ultérieurs de gravure au plasma appliqués afin de graver des couches polymères (24) surjacentes pendant les étapes ultérieures de fabrication des interconnexions à couches multiples de haute densité. L'invention concerne plusieurs structures représentatives d'interconnexion à couches multiples de haute densité sur des substrats en silicium et leurs procédés de fabrication, y compris l'inclusion d'une couche (30) de promotion de l'adhésion sur la couche d'oxyde d'aluminium afin d'améliorer l'adhésion d'un polymère qui, s'il était directement appliqué sur la couche d'oxyde d'aluminium, n'adhèrerait pas bien à celle-ci.
PCT/US1990/006703 1989-11-16 1990-11-15 Structure a circuits hybrides et procedes de fabrication Ceased WO1991007775A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US43798289A 1989-11-16 1989-11-16
US437,982 1989-11-16

Publications (1)

Publication Number Publication Date
WO1991007775A1 true WO1991007775A1 (fr) 1991-05-30

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PCT/US1990/006703 Ceased WO1991007775A1 (fr) 1989-11-16 1990-11-15 Structure a circuits hybrides et procedes de fabrication

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AU (1) AU6873791A (fr)
WO (1) WO1991007775A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3844831A (en) * 1972-10-27 1974-10-29 Ibm Forming a compact multilevel interconnection metallurgy system for semi-conductor devices
US3979241A (en) * 1968-12-28 1976-09-07 Fujitsu Ltd. Method of etching films of silicon nitride and silicon dioxide
EP0046525A2 (fr) * 1980-08-18 1982-03-03 International Business Machines Corporation Structure planar métal-isolant à plusieurs niveaux comprenant un substrat, un réseau conductif d'interconnexion et une structure conductrice superposée et un procédé pour former une telle structure
US4789648A (en) * 1985-10-28 1988-12-06 International Business Machines Corporation Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias
EP0296707A1 (fr) * 1987-06-12 1988-12-28 Hewlett-Packard Company Incorporation d'une couche diélectrique dans une structure semi-conductrice

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3979241A (en) * 1968-12-28 1976-09-07 Fujitsu Ltd. Method of etching films of silicon nitride and silicon dioxide
US3844831A (en) * 1972-10-27 1974-10-29 Ibm Forming a compact multilevel interconnection metallurgy system for semi-conductor devices
EP0046525A2 (fr) * 1980-08-18 1982-03-03 International Business Machines Corporation Structure planar métal-isolant à plusieurs niveaux comprenant un substrat, un réseau conductif d'interconnexion et une structure conductrice superposée et un procédé pour former une telle structure
US4789648A (en) * 1985-10-28 1988-12-06 International Business Machines Corporation Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias
EP0296707A1 (fr) * 1987-06-12 1988-12-28 Hewlett-Packard Company Incorporation d'une couche diélectrique dans une structure semi-conductrice

Also Published As

Publication number Publication date
AU6873791A (en) 1991-06-13

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