WO1992012509A1 - Appareil de commande d'un dispositif d'affichage plan - Google Patents

Appareil de commande d'un dispositif d'affichage plan Download PDF

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Publication number
WO1992012509A1
WO1992012509A1 PCT/JP1991/001710 JP9101710W WO9212509A1 WO 1992012509 A1 WO1992012509 A1 WO 1992012509A1 JP 9101710 W JP9101710 W JP 9101710W WO 9212509 A1 WO9212509 A1 WO 9212509A1
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WO
WIPO (PCT)
Prior art keywords
signal
display device
horizontal synchronizing
input
period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP1991/001710
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English (en)
Japanese (ja)
Inventor
Satoshi Furuta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fanuc Corp
Original Assignee
Fanuc Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fanuc Corp filed Critical Fanuc Corp
Publication of WO1992012509A1 publication Critical patent/WO1992012509A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G09G5/008—Clock recovery

Definitions

  • the present invention relates to a flat panel display driving device that receives a CRT driving signal and operates the flat panel display.
  • the present invention relates to a driving device for a flat panel display device which is improved so as not to cause a malfunction due to noise mixed in a horizontal synchronization signal.
  • Signals required to drive a flat display device such as a liquid crystal display device, a plasma display device, an EL display device, and an electric-mix display device are used to sequentially address each dot of the flat display device. It is a combination of a dress signal and a dot video signal corresponding to each dot.
  • the signals required to drive the CRT include a horizontal synchronization signal indicating the starting point and ending point of each scanning line, a vertical synchronization signal indicating the starting point and ending point of each picture frame, and a signal at each point on the scanning line.
  • This is a combination with a video signal which is a continuous signal sequentially given to the video signal.
  • a display device used in a numerically controlled machine tool or the like a CRT is generally used in the past, and a signal for driving a display device used in a numerically controlled machine tool or the like is composed of a horizontal synchronization signal and a vertical synchronization signal. It was a combination with a video signal.
  • images displayed on display devices used in numerically controlled machine tools and the like are mainly characters, not images that change continuously and gradually (such as scenery). A combination of a binary signal representing darkness and a clock signal that addresses each dot is sufficient.
  • the video signal used for the display device used in the numerical control machine tool, etc. is the value (TP) obtained by dividing the period T of the horizontal synchronization signal HS by the number of dots P of each rod of the flat display device.
  • This is a pulse train signal having a period.
  • the device is used as a display for numerically controlled machine tools, and the signals used to drive the CRT, namely, the horizontal synchronization signal, the vertical synchronization signal, and the period T of the horizontal synchronization signal are displayed on a flat display device.
  • Means for converting to a combination of a signal suitable for the operation, that is, an address signal for sequentially addressing each dot of the flat display device and a dot video signal corresponding to each dot (a flat display device driving device). ) was developed.
  • the present study relates to an improvement of the signal conversion means (a flat display device driving device that receives a CRT driving signal and converts the signal into a signal suitable for operating the flat display device). Therefore, an example of a conventional driving device for a flat panel display device will be briefly described with reference to the drawings.
  • a clock signal generating means C0 generates a pulse train signal having a period t.
  • This clock signal generating means C0 is a clock signal composed of a pulse train signal having a reference period t as a value (TnoP) obtained by dividing the period T of the horizontal synchronization signal HS by the number of dots P of each row of the flat panel display.
  • a dot signal CS is generated and output to the dot video signal address signal generating means PE and the frequency divider FS.
  • the frequency divider FS receives a clock signal CS having a period t, and multiplies the clock signal CS by the number P of dots of each row of the flat panel display device (t P) to obtain a period (the period of the horizontal synchronization signal HS).
  • the horizontal synchronizing signal HS is also input to the comparing means CP and is compared with the row change signal LC generated by the frequency divider FS. When these periods do not match, the deviation ⁇ T is fed back to the clock signal generation means C0, and the clock signal generation means C0 is controlled so that the row change if signal LC coincides with the horizontal synchronization signal HS.
  • the period t of the signal CS, the horizontal synchronization signal HS, and the dot of each row of the flat panel display Maintain the value (TZP) divided by the number P so that the period of the row change signal LC matches the period of the horizontal synchronization signal HS.
  • IS is a video signal
  • VS is a vertical synchronization signal
  • ES is a dot video signal
  • AS is an address signal.
  • the numerical control device is sometimes used for a welding machine that generates electromagnetic waves, and is often operated in an environment where electromagnetic wave noise frequently occurs even if it does not generate electromagnetic waves by itself. Therefore, if extraneous noise enters the horizontal synchronization signal propagation line, a malfunction may occur. This is because the comparator CP incorrectly determines that the external noise is the horizontal synchronization signal HS and controls the cycle of the row change signal LC to be short, so that the cycle of the clock signal CS may be extremely short. is there.
  • An object of the present invention is to solve this drawback, and in a flat panel display driving device that receives a CRT driving signal and converts the signal into a signal suitable for operating the flat panel display, an external noise source is provided.
  • the purpose is to provide an improvement that prevents malfunctions when used in an existing environment. Disclosure of the invention
  • the purpose of the above is to input a video signal (IS), a horizontal synchronizing signal (HS) and a vertical synchronizing signal (VS), and determine the period (T) of the horizontal synchronizing signal (HS) by the number of dots in each row of the flat display device.
  • a clock signal generating means (CO) for generating a clock signal (CS) having a clock period (t) having a value (T / P) divided by (P) as a clock period (t); The number of dots in each row of the flat panel display is added to the clock signal (CS) generated by the clock signal generation means (CO).
  • a frequency divider that generates a row change signal (LC) having a period (T,) multiplied by (P), and a row change signal generated by the frequency divider (FS)
  • LC cycle (T,) is compared with the externally input horizontal synchronization signal (HS1 cycle (T), and the clock signal generation means (CO) is controlled so that they match.
  • Comparator (CP) and clock signal (CS) Dot image signal (IS), horizontal synchronization signal (HS), and vertical synchronization signal (VS) are input, and a dot video signal A that generates a dot video signal (ES) and an address signal (AS) This is achieved by adding the following elements to a flat panel display driving device having a dress signal generating means (PE).
  • PE dress signal generating means
  • the added element is
  • the horizontal synchronizing signal (HS) is input, and is in the enable state in the initial condition, and becomes the disable state in response to the input of the horizontal synchronizing signal (HS), and the horizontal synchronizing signal (HS) is input.
  • the horizontal synchronization signal (HS) is compared with the comparator (CP) only when the time limit means (B) which returns to the enable state in a predetermined time period shorter than the cycle (T) and the ⁇ time limit means (B) are in the enable state.
  • the switching means (S) to input to and.
  • FIG. 1 is a block diagram of a driving device for a flat panel display according to the related art.
  • FIG. 2 is a block diagram of a driving device for a flat panel display according to one embodiment of the present invention.
  • FIG. 3 is a block diagram of an example of the time limit means according to the gist of the present invention.
  • FIG. 1 is a block diagram of a driving device for a flat panel display according to one embodiment of the present invention.
  • the clock signal generating means C0 is composed of a pulse train signal having a period t of a value (TZP) obtained by dividing the period T of the horizontal synchronizing signal HS by the number of dots P of each row of the flat panel display.
  • GTP a value obtained by dividing the period T of the horizontal synchronizing signal HS by the number of dots P of each row of the flat panel display.
  • the time limiter B starts the time limit operation. Note that the time-limiting means B is enabled in the initial condition, and no matter when the horizontal synchronizing signal H arrives, the switching means inputs the horizontal synchronizing signal HS and transfers it to the comparing means CP. It is in a state of death.
  • the time limit means B changes to the disable state, and the switching means S inputs the horizontal synchronization signal HS.
  • the state is changed to not (read) state. Then, after the disable state is maintained for a certain period that is set slightly shorter than the cycle T of the horizontal synchronization signal HS, the state is restored to the enable state.
  • the time limiter B returns to the enable state a little before the next scheduled time of the arrival of the horizontal synchronization signal HS, and subsequently arrives at the horizontal synchronization signal HS (horizontal synchronization signal HS other than noise).
  • the time period during which the horizontal synchronizing signal HS needs to be input to the comparator CP can be predicted from the beginning, and is limited to the time period during which the frequency divider FS may output the row change signal LC.
  • the horizontal synchronization signal HS arriving at other times may be regarded as extraneous noise. Therefore, the present invention embodies this idea, and for a period of time after the arrival of the horizontal synchronization signal HS (for a short period of time after the horizontal synchronization signal HS is expected to arrive).
  • the initial condition of the time limiter B is a state in which the horizontal synchronization signal H S can be read (enable state). Then, once the horizontal synchronizing signal HS arrives, the period t of the clock signal generating means C0 is controlled based on the signal, and then the horizontal synchronizing signal HS cannot be read (disabled state). I do. This is to prevent the reading of incoming external noises.
  • the first incoming signal is not a normal horizontal sync signal HS but an external noise signal
  • the next incoming normal horizontal sync signal HS is disabled. In the period, this is not read, and the normal horizontal synchronizing signal HS arriving on the second side is read for the first time, which has the disadvantage of causing a time loss, but there is no practical problem.
  • the first incoming signal is not a normal horizontal sync signal HS but an external noise signal
  • the period until the next normal horizontal sync signal HS to be read in comes next. Although it may be abnormally long and may be out of the adjustable range of the clock signal generating means C0, this does not actually cause any trouble.
  • the comparator CP has successfully read the horizontal synchronizing signal H S, it does not read the external noise that subsequently arrives, but reads only the authentic horizontal synchronizing signal H S.
  • Comparison means CP is compared with the period T of the period and the horizontal synchronizing signal HS of the row change signal LC, when a difference exists between them, a signal delta T representing the difference of (T 1 one T) Negative feedback to the clock signal generating means CO, and the value obtained by dividing the cycle T of the clock Z pulse CS by the number T of dots of each row of the flat panel image device by dividing the cycle T of the horizontal synchronizing signal HS ( T / P) is the same as in the prior art.
  • - IS- is a video signal
  • VS is a vertical sync signal
  • ES is a Dossot video signal
  • AS This is an address signal.
  • the time limiter B can be realized by various configurations. An example will be described with reference to FIG.
  • the figure is a block diagram showing an example of the time limiter B according to the gist of the present invention.
  • SM is a monostable multivibrator, which satisfies the function of the time limit means according to the present invention. Further, a combination of a counter and a switching means may be used. Industrial applicability
  • the comparison means (synchronization signal input means) of the driving device for a flat panel display according to the present invention is in a state in which signal reading is stopped except during a time period when a genuine horizontal synchronization signal is scheduled to arrive, It is extremely unlikely that noise is read into the comparison means (synchronization signal input means), and the possibility that the clock signal generation means malfunctions due to noise is extremely small.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Synchronizing For Television (AREA)

Abstract

Appareil de commande d'un dispositif d'affichage plan qui reçoit un signal d'image (IS), un signal de synchronisation verticale (VS) et un signal de synchronisation horizontale (HS), et commande une unité (CO) de génération d'un signal d'horloge en fonction du signal de synchronisation horizontale (HS). Ce signal de synchronisation horizontale (HS) ne peut être introduit que pendant la période au cours de laquelle l'arrivée du signal (HS) est attendue, et l'unité (CO) est mise à l'abri des défaillances provoquées par des bruits.
PCT/JP1991/001710 1991-01-08 1991-12-13 Appareil de commande d'un dispositif d'affichage plan Ceased WO1992012509A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3011562A JPH04251286A (ja) 1991-01-08 1991-01-08 平面表示装置用駆動装置
JP3/11562 1991-01-08

Publications (1)

Publication Number Publication Date
WO1992012509A1 true WO1992012509A1 (fr) 1992-07-23

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Application Number Title Priority Date Filing Date
PCT/JP1991/001710 Ceased WO1992012509A1 (fr) 1991-01-08 1991-12-13 Appareil de commande d'un dispositif d'affichage plan

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JP (1) JPH04251286A (fr)
WO (1) WO1992012509A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013008765A1 (fr) 2011-07-08 2013-01-17 Semiconductor Energy Laboratory Co., Ltd. Module électroluminescent, dispositif électroluminescent et procédé de fabrication du module électroluminescent

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5161808U (fr) * 1974-10-17 1976-05-15
JPS56105963U (fr) * 1980-01-14 1981-08-18
JPS59126372A (ja) * 1983-01-06 1984-07-20 Matsushita Electric Ind Co Ltd 雑音除去装置
JPS59171459U (ja) * 1983-04-30 1984-11-16 日本電気ホームエレクトロニクス株式会社 同期信号処理回路
JPS61156096A (ja) * 1984-12-27 1986-07-15 株式会社コンラックス松本 映像デ−タの表示制御方式
JPS6281175A (ja) * 1985-10-03 1987-04-14 Seiko Epson Corp 水平同期信号再生回路
JPS62154878A (ja) * 1985-12-26 1987-07-09 Mitsubishi Electric Corp 同期信号分離回路

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60186247A (ja) * 1984-03-07 1985-09-21 Hashino Yakuhin:Kk 無塩漬物の製造法
JP2733664B2 (ja) * 1988-04-25 1998-03-30 富士通株式会社 マトリクス表示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5161808U (fr) * 1974-10-17 1976-05-15
JPS56105963U (fr) * 1980-01-14 1981-08-18
JPS59126372A (ja) * 1983-01-06 1984-07-20 Matsushita Electric Ind Co Ltd 雑音除去装置
JPS59171459U (ja) * 1983-04-30 1984-11-16 日本電気ホームエレクトロニクス株式会社 同期信号処理回路
JPS61156096A (ja) * 1984-12-27 1986-07-15 株式会社コンラックス松本 映像デ−タの表示制御方式
JPS6281175A (ja) * 1985-10-03 1987-04-14 Seiko Epson Corp 水平同期信号再生回路
JPS62154878A (ja) * 1985-12-26 1987-07-09 Mitsubishi Electric Corp 同期信号分離回路

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Publication number Publication date
JPH04251286A (ja) 1992-09-07

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