WO1994011823A1 - Memoire a fonction in situ de protection contre la reproduction et de securite de donnees - Google Patents

Memoire a fonction in situ de protection contre la reproduction et de securite de donnees Download PDF

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Publication number
WO1994011823A1
WO1994011823A1 PCT/US1993/010775 US9310775W WO9411823A1 WO 1994011823 A1 WO1994011823 A1 WO 1994011823A1 US 9310775 W US9310775 W US 9310775W WO 9411823 A1 WO9411823 A1 WO 9411823A1
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WO
WIPO (PCT)
Prior art keywords
signal
section
enable
enable signal
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1993/010775
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English (en)
Inventor
Ping Wang
Ching-Shi Jenq
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Silicon Storage Technology Inc
Original Assignee
Silicon Storage Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Storage Technology Inc filed Critical Silicon Storage Technology Inc
Publication of WO1994011823A1 publication Critical patent/WO1994011823A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G06F12/1433—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a module or a part of a module

Definitions

  • the present invention relates to a memory storage device and more particularly to a memory storage device comprised of semiconductor integrated memory circuits such as EEPROM and flash EPROM/EEPROM memory circuits. Furthermore, the present invention relates to a memory storage device having in si tu copy protection and data security features.
  • a memory storage device has in si tu copyright protection and data security feature.
  • the memory storage device has an address port which receives an address signal, a data port which receives an input data signal or provides an output data signal, and a write enable port for receiving a write signal.
  • the storage device comprises an electrically alterable memory storage means for storing information.
  • the storage means has a first section and a second section. The first section of the storage means receives the address signal, the write signal, and has an enable port which receives a first enable signal for enabling or disabling the first section.
  • the second section of the storage means receives the address signal and the write signal, and has an enable port which receives a second enable signal for enabling or disabling the second section.
  • Logic means generates simultaneously the first enable signal for enabling the first section to receive the input data signal or for providing an output data signal therefrom and generates the second enable signal to disable the second section.
  • the logic means also comprises means for simultaneously generating the first enable signal for disabling the first section and generating the second enable signal for enabling the second section to provide an output data signal therefrom in one state.
  • the logic means in another state has means for simultaneously generating the first enable signal to disable the first section and generates the second enable signal for enabling the second section to receive the input data signal.
  • Figure 1 is a schematic block level diagram of the storage device 10 of the present invention.
  • Figure 2 is a schematic logic diagram of one embodiment of a high voltage level detector used in the storage device 10 of the present invention.
  • Figure 3 is one embodiment of the state machine shown in Figure 1.
  • the memory storage device 10 has an address port for receiving an address signal 12.
  • the device 10 also has a data port for receiving an input data signal 14 or for providing an output data signal 14.
  • each of the address signal 12 and data signal 14 is supplied on a plurality of conductors.
  • the device 10 also has a write enable port for receiving a write signal 16.
  • An inverse write signal 18, designated as "write#" is also provided.
  • the device 10 has a first section 20 of electrically alterable memory for storing information.
  • the first section 20 comprises a first array 20 of memory cells of the type shown and described in U.S Patent Application No. 07/467,907 filed on January 22, 1990, which is incorporated herein by reference.
  • the first array 20 is also designated as the normal memory array 20.
  • the first array 20 has an address decoder 22 to which the address signal 12 is supplied.
  • the address decoder 22 also has an enable port which receives a first enable signal 24.
  • the first enable signal 24 enables or disables the first section 20 of memory.
  • the write signal 16 is also supplied to the address decoder 22 of the first array 20 of memory.
  • the device 10 also comprises a second section 26 of electrically alterable memory storage cells.
  • the second section 26 is divided into two arrays of memory cells: second array 30 and third array 40.
  • the second array 30, designated as a user array, has an associated address decoder 32.
  • the address decoder 32 receives the address signal 12 and the write signal 16.
  • the second array 30 has an enable port which receives a second enable signal 34 for enabling or disabling the second array . 30.
  • the third array 40 designated as the manufacturer array, also has an address decoder 42 associated therewith.
  • the address decoder 42 receives the address signal 12 and the write signal 16.
  • the address decoder 42 has an enable port which receives a third enable signal 44 which enables or disables the third array 40.
  • a state machine 50 receives the address signal
  • the state machine 50 In response thereto, the state machine 50 generates an output signal SACC# 54.
  • the SACC# 54 is supplied to a NAND gate 56, to which an HACC# signal 58 is also supplied.
  • the HACC# signal 58 is generated by a high voltage detector for detecting high voltage being supplied to specific pins of the device 10 of the present invention.
  • the output of the NAND gate 56 is then inverted by the inverter 60 and is the first enable signal 24.
  • the output of the NAND gate 56 is also supplied the second enable signal 34.
  • the output of the NAND gate 56 is also supplied to a second NAND gate 62 to which the WRITE# signal 18 is also supplied.
  • the output of the NAND gate 62 is supplied to a third NAND gate 64 to which the HACC# signal 58 is also supplied.
  • the output of the NAND gate 64 is the third enable signal 4 .
  • FIG. 2 there is shown one embodiment of a high voltage detection circuit 70.
  • the high voltage detection circuit may comprise of a string of four inverters 72, 74, 76 and 78.
  • the first inverter 72 has a suitable threshold for detection of the high voltage signal involved.
  • the signal is then inverted by the second inverter 74, a third and fourth inverters to reach conventional CMOS signal levels. In this manner, the high voltage supplied to the device 10 can be detected and the signal HACC# 58 can be generated.
  • FIG 3 there is shown one embodiment of the state machine 50.
  • the state machine 50 serves to detect a combination of the address signal 12, data signal 14 and the write pulse signal 52 to generate the SACC# signal 54. As will be seen, the specific embodiment of the state machine 50 is purely arbitrary.
  • the SACC# signal 54 is generated is dictated entirely by the manufacturer of the device 10. It can range from a simple circuit of the type shown in Figure 3 wherein a certain logic combination of the address signal 12 and data signal 14 sets a flip-flop or register 80 and another certain combination of the address signals 12 and data signals 14 resets the flip-flop 80.
  • the operation of the device 10 will now be described with reference to a specific example wherein the first array of normal memory 20 comprises one megabytes of storage.
  • the address signals 12 comprises 20 signal lines.
  • the address signal 12 ranges from "00000" to "FFFFF", where the numbers are expressed in hexadecimal units.
  • the user array 30 comprises memory cells addressable in the location from “10000” to "30000”.
  • the manufacture array 40 comprises memory cells addressable in the location from "00000” to "0FFFF".
  • no portion of the address of the memory cell in the user array 30 overlaps with the address of the manufacturer array 40, and vice versa.
  • the address space of the memory cells in the second section 26, i.e. the user array 30 and the manufacturer array 40 overlap that of the normal memory array 20.
  • the device 10 of the present invention is particularly suited to be used as a "memory card" .
  • the memory cells of the device 10 of the present invention comprise electrically alterable memory cells
  • the first array 20 of memory cells can be used to store computer programs, such as word processing and spread sheet programs, and distributed on memory card form.
  • the user array 30 is a section in the device 10 which the user can have access to with the storage of his/her data.
  • the manufacturer array 40 is an area of the device 10 containing information such as the production history of the memory cells of the device 10.
  • the manufacturer array 40 can be used by the publisher of the computer program that is stored in the first array 20 to provide a key or a copy protect algorithm to thwart the copying of the program that is stored in the first array 20. The specific manner of accomplishing that function will now be explained.
  • the signals SACC# 54, HACC# 58, and RITE# 18 are all active low signals. That is, these signals represent a logic "1" state when they are low in voltage and a logic "0" state when they are high in voltage.
  • the first enable signal 24, second enable signal 34, and third enable signal 44 are all active high signals. Thus, a logic table for the various signals is set forth on the attached.
  • the first array 20 of normal memory is activated to read or write therefrom when both SACC# 54 and HACC# 58 signals are high.
  • the address signals 12 would activate an address in the normal memory array 20.
  • the write signal 16 would cause memory array 20 to be written into or read from and provide the appropriate signals on the data signal 14.
  • the first enable signal 24 is generated enabling the first array 20
  • the second enable signal 34 and the third enable signal 44 serve to disable the second and third memory arrays 30 and 40 respectively.
  • both the second enable signal 34 and third enable signal 44 are generated to activate the second array 30 and the third array 40 respectively.
  • the first enable signal 24 is generated to disable the reading or writing of data from the first array 20.
  • the generation of the enable signals serve to differentiate between the different arrays of the memory.
  • SACC# signal 54 is generated and WRITE# signal 18 is active low, then the second memory array 30 can be written into.
  • the device 10 of the present invention is used to store computer program in the first array 20 and the device 10 is used to distribute the computer program, then the thwarting of copying occurs as follows.
  • the manufacturer of the software program would store a key program or data in the third array 40, during the process of manufacturing the card. There are three potential cases with respect to the copying of data.
  • the first case is where the copying is from the software manufacturer supplied card 10 (the card 10 of the present invention: hereinafter: “original card”) to a copied card (hereinafter: “copied card”), which is identical to the card 10 of the present invention.
  • the copied card 10 prohibits the writing of data or program, including the key, into the third array 40. Since normally the HACC# signal 58 is accessible only by the manufacturer, only the program in the first array 20 would be copied into the corresponding first array 20 in the second device 10.
  • the key or the copy protection code that is contained in the third array 40 although could be read by the computer to which the device 10 is attached, could not be copied to the second memory card because the HACC# signal 58 is not available.
  • the high voltage signal is normally not supplied to the memory card 10 when the card is used by a user in a "normal" computer.
  • the high voltage signal is present only when the manufacturer publishes the card 10 and stores the key in the third array 30.
  • the program in the first array 20 or the second array 30 looks to the key in the third array 40. Since the key would be missing in the third array 40, the program would stop executing.
  • the copying is from an original card to a copied card similar to the card 10 of the present invention.
  • the copied card has the three arrays 20, 30 and 40, with the second and third arrays 30 and 40 being writable by the user. Since the second and the third arrays 30 and 40 are writable by the user, the user can copy the contents of the second and third array 30 and 40 from the original card 10 to the copied card.
  • the program attempts to write into the area in the third array 40 where the key is located. If the card 10 is an original card, the user cannot write into that portion of the third array 40, and the original key would remain. If the card 10 is a copied card, the result would be an altered key.
  • the contents of third array 40 would be read.
  • the result would be the original key being read back (if the card 10 were the original card) or would be the altered key (if the card 10 were the copied card) .
  • the program can then terminate execution if the key were the altered key.
  • the copied card has the second array 30 and the third array 40 alterable by a programmer, but not by a user.
  • a user operating as a programmer status, copies the contents of the original card 10, including the contents of all three arrays 20, 30 and 40 into the copied card. Since the user has programmer status, the copied card will contain the contents from the third array 40 of the original card 10.
  • the program In the execution of the program from the copied card, the program writes a test code into the third array 40 of the copied card 10.
  • the card from which the program was loaded is a copied card and the program terminates its execution. This is the case where the user executes the program of the copied card while maintaining the programmer status. If the user changes the status to a user status and executes the program from the copied card, then the program writing to the third array 40 would find the key is not altered.
  • the program then writes to a section in the second array 30. If the second section is alterable, then the card from which the program is executing is an original card. If the second array 30 is not alterable, then the card from which the program is executing is a copied card. In that event the program would also terminate its execution.
  • the device 10 provides users of the device 10 a way to access extra memory blocks which are not normally addressable by the conventional address pins.
  • the sections of the memory in the second array 30 and the third array 40 are addressed by the same address locations as in the first array 20.
  • the generation of the first enable signal 24, and the second and third enable signals 34 and 44 respectively control whether or not the first array of memory cells 20 is accessed or the second and third memory arrays 30 and 40 are accessed.
  • the memory is further divided into a user array 30 and a manufacturer array 40 to differentiate a user's portion and a manufacture's portion. Through this division, data security can be easily assured and copy protection can be properly enforced.
  • the SACC# signal 54 can be supplied directly into the memory device 10.
  • the address signals 12 can be used to directly address the second and third arrays 30 and 40, respectively.
  • the direct access can be assigned to different user array or manufacturer array. In fact, direct access may permit addressing of a memory space which overlaps areas accessible by other access modes. In each of the overlapping areas, a different access rights, i.e. read only, read/write, or even write only can be defined.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Storage Device Security (AREA)

Abstract

Une carte mémoire (10) utilise deux sections de cellules de mémoires électriquement modifiables, telles que des cellules EEPROM. La première section (20) reçoit un signal d'adresse (12), un signal d'écriture (16) et un premier signal de validation (24) permettant de valider ou d'invalider la première section (2). La seconde section (26) de la carte mémoire (10) reçoit le signal d'adresse (12), le signal d'écriture (16) et un second signal de validation (34) permettant de valider ou d'invalider la seconde section (26). Un dispositif logique (50) génère simultanément le premier signal de validation (24), afin de permettre à la première section d'y lire ou d'y introduire des signaux de données, et le second signal de validation (34), qui invalide la seconde section (26). Selon un second mode de fonctionnement, le dispositif logique (50) génère simultanément un premier signal de validation (24) destiné à invalider la première section (20) et un second signal de validation (34) qui permet de lire la mémoire de la seconde section (26). Enfin, selon le troisième mode de fonctionnement, le dispositif logique (50) génère le premier signal de validation (24) pour invalider la première section (20) et génère simultanément le second signal de validation (34) permettant d'introduire des données dans la seconde section (26).
PCT/US1993/010775 1992-11-12 1993-11-09 Memoire a fonction in situ de protection contre la reproduction et de securite de donnees Ceased WO1994011823A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US97492992A 1992-11-12 1992-11-12
US07/974,929 1992-11-12

Publications (1)

Publication Number Publication Date
WO1994011823A1 true WO1994011823A1 (fr) 1994-05-26

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3934227A (en) * 1973-12-05 1976-01-20 Digital Computer Controls, Inc. Memory correction system
US3995253A (en) * 1975-03-03 1976-11-30 International Business Machines Corporation Method and apparatus for accessing horizontal sequences, vertical sequences, and rectangular subarrays from an array stored in a modified word organized random access memory system
US5046076A (en) * 1988-09-19 1991-09-03 Dynetics Engineering Corporation Credit card counter with phase error detecting and precount comparing verification system
US5226006A (en) * 1991-05-15 1993-07-06 Silicon Storage Technology, Inc. Write protection circuit for use with an electrically alterable non-volatile memory card
US5265231A (en) * 1991-02-08 1993-11-23 Thinking Machines Corporation Refresh control arrangement and a method for refreshing a plurality of random access memory banks in a memory system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3934227A (en) * 1973-12-05 1976-01-20 Digital Computer Controls, Inc. Memory correction system
US3995253A (en) * 1975-03-03 1976-11-30 International Business Machines Corporation Method and apparatus for accessing horizontal sequences, vertical sequences, and rectangular subarrays from an array stored in a modified word organized random access memory system
US5046076A (en) * 1988-09-19 1991-09-03 Dynetics Engineering Corporation Credit card counter with phase error detecting and precount comparing verification system
US5265231A (en) * 1991-02-08 1993-11-23 Thinking Machines Corporation Refresh control arrangement and a method for refreshing a plurality of random access memory banks in a memory system
US5226006A (en) * 1991-05-15 1993-07-06 Silicon Storage Technology, Inc. Write protection circuit for use with an electrically alterable non-volatile memory card

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