WO2000005874A1 - Detecteurs de pixels actifs possedant des noeuds de stockage multiples - Google Patents

Detecteurs de pixels actifs possedant des noeuds de stockage multiples Download PDF

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Publication number
WO2000005874A1
WO2000005874A1 PCT/US1999/015855 US9915855W WO0005874A1 WO 2000005874 A1 WO2000005874 A1 WO 2000005874A1 US 9915855 W US9915855 W US 9915855W WO 0005874 A1 WO0005874 A1 WO 0005874A1
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Prior art keywords
terminal
separate
coupled
storage nodes
active pixel
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Ceased
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PCT/US1999/015855
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English (en)
Inventor
Richard B. Merrill
Richard F. Lyon
Jeffrey Allen Dickson
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Foveon Inc
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Foveon Inc
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/58—Control of the dynamic range involving two or more exposures
    • H04N25/587—Control of the dynamic range involving two or more exposures acquired sequentially, e.g. using the combination of odd and even image fields
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors

Definitions

  • the present invention relates to active pixel sensors and active pixel sensor arrays. More particularly, the present invention relates to active pixel sensors having multiple storage nodes, and applications, such as still cameras, that employ an array of active pixel sensors having multiple storage nodes.
  • a typical active pixel area-array image sensor is disclosed in Hurwitz et al., "An 800K-Pixel Color CMOS Sensor For Consumer Still Cameras", SPIE Vol. 3019, pp 115-124 and comprises a plurality of rows and columns of pixel sensors.
  • the most common method of exposure for this type of sensor array is to cyclicly scroll through the rows so that the integration duration for each row is the same, but can be shorter than the total readout interval. This method of exposure control is known as an electronic shutter.
  • a still camera having the capability of capturing multiple images in rapid succession would help to secure numerous benefits not provided for by the prior art.
  • multiple images with different focus settings may be used to reconstruct an image that is sharp.
  • multiple images with different exposure settings or sensitivities may be used to reconstruct an image with wide dynamic range.
  • multiple images can be captured with a known time interval between them for the purpose of measuring velocity of objects captured within the images.
  • images stored in rapid succession can be used for temporal bracketing, including capturing images from the recent past before the "shutter release" button is pressed.
  • images may be taken immediately before and after firing an electronic flash in order to capture differently-lighted images. The flash-exposed image and the image exposed in natural light may then be combined.
  • Sixth, multiple images may be captured through separate color filters (e.g., red, green and blue filters) to capture a color image.
  • active pixel sensors having multiple storage nodes suitable for use in an array of storage pixel sensors is disclosed.
  • the array may be used in still camera applications to capture multiple images in rapid succession.
  • the captured images may then be manipulated to construct a new image or for other purposes, such as measuring the velocity of objects within the captured images.
  • the active pixel sensor includes a plurality of storage nodes, one row select line for selecting the plurality of storage nodes, and a plurality of column output lines upon which the images stored in the plurality of storage nodes may be read out.
  • Column circuits may be employed to perform a function on the images stored on the plurality of storage nodes.
  • the active pixel sensor includes a plurality of storage nodes, a plurality of row select lines connected to the plurality of storage nodes and a single column output line upon which the images stored in the plurality of storage nodes may be read out.
  • One or more row decoding circuits may be connected to the row select lines to select a row of one of the stored images within the storage nodes.
  • the active pixel sensor includes a plurality of storage nodes, a plurality of image select signals for selecting the plurality of storage nodes, and a single row select line for placing selected images on a column output line.
  • the use of the image select signals in combination with the row select transistor eliminates the need for the multiple row select signals of the third embodiment.
  • the storage pixel sensor includes multiple storage nodes, multiple row select lines, and multiple column output lines.
  • the active pixel sensor includes two storage nodes connected to a differential amplifier controlled by a single row select line to provide differential current output.
  • Column circuits may be used to directly sense a difference between the two images stored on the two storage nodes.
  • the differential read out circuit may be used for various purposes.
  • FIG. 2 is a schematic diagram of an N-channel MOS implementation of a known active pixel sensor circuit having a single storage node.
  • FIG. 3 is a timing diagram illustrating the operation of the active pixel sensor depicted in FIG. 2.
  • FIG. 4 is a diagram of a photosensor suitable for use according to the present invention.
  • FIGS. 5, 6, 7, 8, 9 and 10 are schematic diagrams of active pixel sensors having multiple storage nodes according to first through six embodiments of the present invention.
  • FIGS. 11 A and 1 IB are alternative timing diagrams for the operation of the active pixel sensors according to the present invention.
  • FIG. 1 is a block diagram of an active pixel imager 10 suitable for use according to the present invention.
  • the active pixel sensors are arranged in rows and columns in a pixel sensor array 12.
  • ADC analog-to-digital converter
  • a row decoder circuit 16 selects rows from the pixel sensor array 12 in response to a row enable signal 22 and signals from the counter 20.
  • the column sampling circuit 18 is also driven from the counter 20 and further includes a multiplexer that couples the sampled columns as desired to the ADC in response to signals from counter 20.
  • the higher-order bits from counter 20 are used to drive the row decoder circuit 14 and the lower-order bits are used to drive column sampling circuit 20 to permit extraction of all pixel information from a row in the pixel sensor array 12 prior to selection of the next row by row decoder circuit 14.
  • Row decoders, column sampling circuits, and counters suitable for use in the imager 10 are well known to those of ordinary skill in the art, and will not be described herein in detail to avoid overcomplicating the disclosure and thereby obscuring the present invention.
  • FIG. 2 a schematic diagram of a known active pixel sensor 30 with a single embedded storage element is shown.
  • the active pixel sensor 30 is implemented with N-channel MOS transistors. Those of ordinary skill in the art will appreciate that the active pixel sensor 30 may otherwise be implemented with all P- channel MOS transistors or a combination of P-channel and N-channel MOS transistors.
  • a photodiode 32 has an anode connected to ground and a cathode connected to the source of N-Channel MOS reset transistor 34.
  • the drain of N- Channel MOS reset transistor 34 is connected to Vref and the gate of N-Channel MOS reset transistor 34 is connected to the global RESET line indicated by reference numeral 24 in FIG. 1.
  • the RESET line is preferably driven to a voltage at least a threshold above Vref to set the cathode of the photodiode 32 to Vref.
  • the cathode of photodiode 32 is also connected to a first source/drain of N- channel MOS transfer transistor 36.
  • a second source/drain of N-Channel MOS transfer transistor 36 is connected to a first terminal of a storage element 38 and also to the gate of N-channel MOS readout transistor 40.
  • a second terminal of the storage element 38 is connected to reference potential shown as ground.
  • the gate of N-Channel MOS transfer transistor 36 is connected to the global XFR line indicated by reference numeral 26 in FIG. 1.
  • the connection of the second source/drain of N-Channel MOS transfer transistor 36 to the first terminal of storage element 38 and also to the gate of N-Channel MOS transistor 40 forms a storage node 42.
  • N-channel MOS readout transistor 40 The drain of N-channel MOS readout transistor 40 is connected to Vcc, and the source of N-channel MOS readout transistor 40 is connected to the drain of N-channel MOS row select transistor 44.
  • the gate of N-channel MOS row select transistor 44 is connected to a ROW SELECT line, one of which is depicted by reference numeral 28 in FIG. 1, and the source of N-channel MOS row select transistor 44 is connected to a column output line.
  • the N-channel MOS transfer transistor 36 to isolate the storage node 42 from further collection of photocharge by the cathode of photodiode 32 when an integration period to be described below has ended, the N-channel MOS readout transistor 40 to sense the charge accumulated at storage node 42, and the storage element 38 to store charge.
  • the N-channel MOS readout transistor 40 to sense the charge accumulated at storage node 42
  • the storage element 38 to store charge.
  • the storage element 38 may be omitted and charge stored on the gate of N- channel MOS readout transistor 40 or that other capacitive means of charge storage may be employed.
  • FIG. 3 illustrates a timing diagram of the RESET, XFR and ROW SELECT signals depicted in FIG. 2.
  • the active pixel 30 is reset by turning on both N-channel MOS reset transistor 34 and N- channel MOS transfer transistor 36 as shown by the HIGH level of both the RESET and XFR signals at 50 and 52. Then the N-channel MOS reset transistor 34 is turned off at the falling edge 54 of RESET 50 so that integration of photocurrent from photodiode 32 can begin.
  • the photocurrent integration period is indicated by reference numeral 56.
  • N-channel MOS transfer transistor 36 While N-channel MOS transfer transistor 36 is turned on, the capacitance of the storage element 38 adds to the capacitance of the photodiode 32 during integration, thereby increasing the charge capacity and the range of the active pixel sensor 30. This also reduces variation in the pixel output due to capacitance fluctuations since gate oxide capacitance from which storage element 38 is formed is better controlled than junction capacitance of the photodiode 32.
  • the N-channel MOS transfer transistor 36 turns off at falling edge 58 of XFR to isolate the voltage level corresponding to the integrated photocharge onto the storage element 38.
  • the photodiode 32 itself is preferably reset to the reference voltage by again turning on N-channel MOS reset transistor 34 as indicated by rising edge 60 of RESET. This action will prevent the photodiode 32 from continuing to integrate during the read out process and possibly overflowing excess charge into the substrate which could effect the integrity of the signal on the storage element 38.
  • Each of the active pixel sensors in a row is read when a ROW SELECT signal pulse as shown in FIG. 3 is applied to the gate of the N-channel MOS row select transistor 44 in an active pixel sensor 30.
  • a voltage related to the voltage found on storage node 42 is sensed by N-Channel MOS readout transistor 40 and placed on the column output line when N-channel row select transistor 44 is turned on.
  • the XFR signal stays low until all of the rows have been read out or another cycle is initiated.
  • a photodiode suitable for use according to the present invention is disclosed in co- pending United States application serial No.
  • the photodiode disclosed therein has a triple- well structure that provides three overlapping photodetectors in the photodiode.
  • each of these overlapping photodetectors may be connected to a different one of the multiple storage nodes in the active pixel sensors.
  • Photosensor 70 includes first and second photodiodes 72 and 74.
  • First and second photodiodes 72 and 74 are arranged in an annular manner, such that first photodiode 72 provides a low sensitivity area in comparison to the high sensitivity area of the larger second photodiode 74. Because the first and second photodiodes 72 and 74 have the same geometric center, they will sample the same average incident photon flux of the image when the spacial signal variation is linear.
  • a dynamic range compression advantage provided by the photosensor 70 is that first and second photodiodes 72 and 74 will sample the photo current during the same time interval. It will be readily appreciated by those of ordinary skill in the art that this property could be very useful, for example, in flash exposures.
  • each of the first and second photodiodes 72 and 74 will generate photo current in proportion to its area.
  • the active area openings and the photo diodes can be made small enough to provide a photo current ratio that is quite large, on the order, for example, of about 50:1— for a 6 micron x 6 micron pixel.
  • each of the photodiodes 72 and 74 in the photosensor 70 may be connected to a separate one of the multiple storage nodes to be described below.
  • the active pixel sensors in an imager 10 such as that illustrated in FIG. 1 may include multiple storage nodes so that an array of pixel sensors each having multiple storage nodes may be used to capture more than a single image.
  • a storage pixel sensor having multiple storage nodes are described below.
  • the embodiments of storage pixel sensors described below are implemented with N-channel MOS transistors. Those of ordinary skill in the art will appreciate that the storage pixel sensors below may otherwise be implemented with P- channel MOS transistors or a combination of N-channel and P-channel MOS transistors.
  • the storage pixel sensor 100 includes a photodiode 102 having an anode connected to ground and a cathode connected to the source of an N-channel MOS reset transistor 104.
  • the gate and drain of N-channel MOS reset transistor 104 are connected to a RESET signal and to Vref, respectively.
  • FIGS. 5-9 each include a plurality of storage nodes 106-1 through 106- n.
  • a first storage node 106-1 connects the first terminal of a storage element 108-1, a first source/drain of N-channel MOS transfer transistor 110-1, and the gate of N-channel MOS readout transistor 112-1.
  • a nth storage node 106-n connects the first terminal of a storage element 108-n, a first source/drain of N-channel MOS transfer transistor 110-n, and the gate of N-channel MOS readout transistor 112-n.
  • the cathode of the photodiode 102 is also connected to a second source/drain of N-channel MOS transfer transistors 110-1 and 110-n.
  • the gates of N-channel MOS transfer transistors 110-1 and 110-n are connected XFRl and XFRn signals, respectively.
  • the storage elements 108-1 and 108-n each have a second terminal connected to a fixed potential shown as ground.
  • FIG. 9 additional storage nodes 106-n/i and 106-(n-j), are depicted to demonstrate that the multiple storage nodes may be matrixed between ROW SELECT 1 through ROW SELECT i and column output lines 1 through j.
  • Storage node 106-n/i connects the first terminal of a storage element 108-n/i, a first source/drain of N-channel MOS transfer transistor 110-n/i, and the gate of N-channel MOS readout transistor 112-n/i.
  • Storage node 106-(n-j) connects the first terminal of a storage element 108-(n-j), a first source/drain of N-channel MOS transfer transistor 1 l ⁇ -(n-j), and the gate of N-channel MOS readout transistor 112-(n-j).
  • the cathode of the photodiode 102 is also connected to a second source/drain of N- channel MOS transfer transistors 110-n/i and 1 l ⁇ -(n-j).
  • the gates of N-channel MOS transfer transistors 110-n i and 1 l ⁇ -(n-j) are connected XFRn i and XFR(n-j) signals, respectively.
  • the storage elements 108-n/i and 108-(n-j) each have a second terminal connected to a fixed potential shown as ground.
  • the first storage node 106-1 connects the first terminal of a storage element 108-1, a first source/drain of N-channel MOS transfer transistor 110-1, and the gate of N-channel MOS readout transistor 112-1.
  • the second storage node 106-2 connects the first terminal of a storage element 108-2, a first source/drain of N-channel MOS transfer transistor 110-2, and the gate of N-channel MOS readout transistor 112-2.
  • the cathode of the photodiode 102 is also connected to a second source/drain of N-channel MOS transfer transistors 110-1 and 110-2.
  • the gates of N-channel MOS transfer transistors 110-1 and 110-2 are connected XFRl and XFRn signals, respectively.
  • the storage elements 108-1 and 108-2 each have a second terminal connected to a fixed potential shown as ground.
  • the active pixel sensors 110-1 through 110-6 are reset and charge is accumulated in a manner similar to that described above with respect to FIG. 2.
  • the operation may be performed differently than described above with reference to FIG. 2, in that the integration periods for the images stored on each of the storage nodes may be made different by applying the XFRl through XFRn signals to the gates of N-channels MOS transfer transistors 110-1 and 110-n, respectively, for different durations or at different times.
  • the single global XFR line as depicted in FIG. 1 there will be XFRl through XFRn global transfer lines.
  • the RESET signal makes a transition at falling edge 150 to begin the accumulation of charge on storage node 106-1.
  • XFRl signal makes a transition at falling edge 152
  • the accumulation of charge on storage node 106-1 stops.
  • the RESET signal is then makes a transition at rising edge 154 to reset the voltage at the cathode of the photodiode 102.
  • the XFRn signal then makes a transition at rising edge 156.
  • the RESET signal makes a transition at falling edge 158, accumulation of charge on storage node 106-n begins.
  • the XFRn signal makes a transition at falling edge 160
  • the accumulation of charge on storage node 106-n stops.
  • the RESET signal makes a transition at falling edge 170 to begin the accumulation of charge on storage nodes 106-1 and 106-2.
  • XFRl signal makes a transition at falling edge 172
  • the accumulation of charge on storage node 106-1 stops, and the accumulation of charge on storage node 106-n continues until the XFRn signal makes a transition at falling edge 174.
  • each N-channel MOS readout transistor 112-1 through 112-n is connected to Vcc, and the source of each N-channel MOS readout transistor 112-1 through 112-n is connected to the drain of an N-channel MOS row select transistor 114-1 through 114-n, respectively.
  • N-channel MOS row select transistors 114-1 through 114-2 are each connected to the same ROW SELECT signal, and the source of N-channel MOS row select transistor 114-1 through 114-2 are connected to the column output lines 116-1 through 116-n, respectively.
  • column circuits (not shown) connected to the column output lines 116-1 through 116-n, respectively, may be used to select a stored image provided on the storage nodes 106-1 through 106-n. Further, column circuits may be used to perform some function on both stored images, such as performing the a linear combination of the two images.
  • each N-channel MOS readout transistor 112-1 through 112-n is connected to Vcc, and the source of each N-channel MOS readout transistor 112-1 through 112-n is connected to the drain of N-channel MOS row select transistors 120-1 through 120-n, respectively.
  • N-channel MOS row select transistors 120-1 through 120-n are each connected to ROW SELECT 1 through ROW SELECTn signals, respectively, and the sources of N-channel MOS row select transistors 120-1 through 120-n are connected to the single column output line 118.
  • active pixel sensor 100-2 In the operation of active pixel sensor 100-2, the image stored on storage node 106-1 will be read out in response to a HIGH ROW SELECT 1 signal , and the image stored on storage node 106-n will be read out in response to a HIGH ROW SELECTn signal. It should be understood that the imager 10 depicted in FIG. 1 will further include additional decoding circuits for providing the ROW SELECT 1 through ROW SELECTn signals. In the embodiment of active pixel sensor 100-3 depicted in FIG.
  • N-channel MOS image select transistors 124-1 through 130-n are connected to IMAGE SELECT 1 through IMAGE SELECTn signals, respectively.
  • the sources of N-channel MOS image select transistors 124-1 through 124-n are connected to the drain of N- channel MOS row select transistors 126.
  • the gate of N-channel MOS row select transistor 126 is connected to a ROW SELECT signal, and the source of N-channel MOS row select transistor 126 is connected to a column output line 122.
  • the image stored on storage node 106-1 will be read out in response to a HIGH ROW SELECT signal and a HIGH IMAGE SELECT 1 signal
  • the image stored on storage node 106-n will be read out in response to a HIGH ROW SELECT signal and a HIGH IMAGE SELECTn signal.
  • the imager 10 depicted in FIG. 1 will further include global IMAGE SELECT 1 through IMAGE SELECTn lines. The use of the global IMAGE SELECT 1 through IMAGE SELECTn signals in combination with the ROW SELECT signal eliminates the need for the additional row decoding required in the second embodiment.
  • N-channel MOS row select transistor 130 is connected to a ROW SELECT signal, and the drain of N-channel MOS row select transistor 130 is connected to a column output line 128.
  • the column output line 128 is connected to the drain of the N-channel MOS row select transistor 130.
  • the current- mode output on column output line 128 is therefore controlled by the IMAGE SELECT 1 through IMAGE SELECTn signals.
  • the column output line 128 output must be kept biased to a high enough voltage that the non-selected N-channel MOS readout transistors 112-1 through 112-2 do not start conducting backward. Further, it should be appreciated that the voltage drivers for the IMAGE Select 1 through IMAGE SELECTn signals must be capable of sinking all the column current from the selected row.
  • the voltages present on storage nodes 106-1 through 106-n/i are read out onto column output lines 132-1 through 132-j, respectively, by the ROW SELECT1 signal, and the voltages present on storage nodes 106-(n-j) through 106-n are read out onto column output lines 138-1 through 132-j, respectively, by the ROW SELECT i signal.
  • the drain of each N-channel MOS readout transistors 112-1 through 112-n are connected to Vcc, and the source of each N-channel MOS readout transistor 112-1 through 112-n is connected to the drain of an N-channel MOS row select transistor 134-1 through 134-n, respectively.
  • N-channel MOS row select transistors 134-1 through 134-n/i are each connected to the ROW SELECT 1 signal, and the gates of N-channel MOS row select transistors 134-(n-j) through 134-n are each connected to the ROW SELECT i signal.
  • the sources of N-channel MOS row select transistors 134-1 through 134-(n-j) are connected to first column output line 132-1, and the sources of N-channel MOS row select transistors 134-n/i through 134-j are connected to the column output line 132-j.
  • charge stored on any of the storage nodes 106-1 through 106-n in is read out in response to the application of the ROW SELECT 1 through ROW SELECT i signals applied to the gate of N-channels MOS row select transistors 134-1 through 134-n to which the storage node 106-1 through 106- n is coupled and by sensing the column output line 132-1 through 132-j to which the storage node 106-1 through 106-n is coupled.
  • the ROW SELECT 1 signal will be asserted and the COLUMN OUTPUT 1 line 138-1 will be chosen.
  • the matrixing of the storage nodes 106-1 through 106-n between several ROW SELECT lines and several column output lines reduces the number of additional row and column lines required. It should also be understood that instead of the single global XFR line depicted in FIG. 1 that there will be XFRl through XFRn global transfer lines.
  • the N-channel MOS row select transistor 136 and N-channel MOS readout transistors 112-1 and 112-2 are configured as a differential amplifier, such that the source of each N-channel MOS readout transistor 112-1 and 112-2 is connected to the drain of N-channel MOS row select transistor 136, the drains of N-channel MOS readout transistor 112-1 and 112-2 are connected to first and second column output lines 140-1 and 140-2, respectively, the source of N-channel MOS row select transistor 136 is connected to a column bias line 138, and the gate of N-channel MOS row select transistor 136 is connected to a ROW SELECT signal.
  • the N-channel MOS read out transistors 112-1 and 112-2 and N-channel MOS row select transistor 136 form a differential amplifier, so that when ROW SELECT signal goes HIGH, the N-channel MOS row select transistor 136 is turned on, and the differential signal on storage nodes 106-1 and 106-2 is read out on column outputs 140-1 and 140-2.
  • the differential read out of the storage nodes 106-1 and 106-2 may be used in a variety of ways. For example, the differential read out may be used to read out a difference relative to a dark frame. In this manner, correlated noises may be removed, leaving only uncorrelated pixel noises.
  • the differential read out may be also used as a processor for detecting image changes.
  • differential read out circuit placed in the active pixel sensor could also be placed in a column circuit. Placing the differential read out circuit in the column circuit would permit frames to be read out before and after a detected change.

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  • Multimedia (AREA)
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  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

Détecteur de pixel actif placé sur un substrat de semi-conducteur et comprenant un photodétecteur, un transistor de remise à zéro, une pluralité de noeuds de stockage et des moyens de sortie. Ce photodétecteur possède une première borne et une deuxième borne, cette première borne étant couplée à un premier potentiel de référence. Le transistor de remise à zéro possède une première borne couplée à la deuxième borne dudit photodétecteur, une deuxième borne couplée à un potentiel de remise à zéro et une troisième borne couplée à une ligne de remise à zéro. La pluralité de noeuds de stockage est couplée à ladite deuxième borne dudit photodétecteur et les moyens servant à sortir une valeur depuis tout noeud de ladite pluralité de noeuds de stockage sont couplés à ces noeuds de stockage.
PCT/US1999/015855 1998-07-22 1999-07-13 Detecteurs de pixels actifs possedant des noeuds de stockage multiples Ceased WO2000005874A1 (fr)

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EP1078390A4 (fr) * 1998-04-16 2001-08-08 Intel Corp Capteur cmos de pixels actifs, a condensateurs de memorisation multiples
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FR2807264A1 (fr) * 2000-03-31 2001-10-05 Matra Marconi Space France Dispositif d'imagerie a pixels actifs et a accumulation
WO2002051130A1 (fr) * 2000-12-21 2002-06-27 Stmicroelectronics Nv Dispositif de detection d'image a verrouillage central
EP1231641A1 (fr) * 2001-02-09 2002-08-14 C.S.E.M. Centre Suisse D'electronique Et De Microtechnique Sa Elément de prise d'images actif avec mémoire analogique pour un capteur d'images
EP1280341A1 (fr) * 2001-07-17 2003-01-29 Eaton Corporation Circuit d'imageur optique avec tolérance de différence entre lumière ambiante et éclairage
US7009648B2 (en) 2000-02-22 2006-03-07 Asulab S.A. Method for operating a CMOS image sensor
WO2007027300A1 (fr) * 2005-08-30 2007-03-08 Motorola Inc. Capteur d’image en couleur avec filtre couleur réglable
WO2007041078A1 (fr) * 2005-10-04 2007-04-12 Lucent Technologies Inc. Appareil d'imagerie optique a expositions multiples
WO2007081743A3 (fr) * 2006-01-13 2007-12-27 Micron Technology Inc Procédé et appareil de détection de la charge de la grille de stockage des pixels pour la stabilisation électronique d'imageurs
WO2008057527A3 (fr) * 2006-11-07 2008-10-02 Eastman Kodak Co Stockage d'images multiples sur capteur
WO2008088477A3 (fr) * 2006-12-20 2009-02-12 Carestream Health Inc Réseau d'imagerie utiliser pour saisir plusieurs images
EP1868377A4 (fr) * 2005-04-07 2010-12-29 Univ Tohoku Capteur de lumiere, dispositif de collecte d image a semi-conducteur et procede pour faire fonctionner le dispositif de collecte d image a semi-conducteur
GB2487943A (en) * 2011-02-09 2012-08-15 St Microelectronics Res & Dev A CMOS pixel sensor with local analogue storage in each pixel circuit for capturing frames in quick succession

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WO2002051130A1 (fr) * 2000-12-21 2002-06-27 Stmicroelectronics Nv Dispositif de detection d'image a verrouillage central
EP1231641A1 (fr) * 2001-02-09 2002-08-14 C.S.E.M. Centre Suisse D'electronique Et De Microtechnique Sa Elément de prise d'images actif avec mémoire analogique pour un capteur d'images
EP1280341A1 (fr) * 2001-07-17 2003-01-29 Eaton Corporation Circuit d'imageur optique avec tolérance de différence entre lumière ambiante et éclairage
EP1868377A4 (fr) * 2005-04-07 2010-12-29 Univ Tohoku Capteur de lumiere, dispositif de collecte d image a semi-conducteur et procede pour faire fonctionner le dispositif de collecte d image a semi-conducteur
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US7965330B2 (en) 2006-01-13 2011-06-21 Micron Technology, Inc. Method and apparatus providing pixel storage gate charge sensing for electronic stabilization in imagers
US8488036B2 (en) 2006-01-13 2013-07-16 Micron Technology, Inc. Method and apparatus providing pixel storage gate charge sensing for electronic stabilization in imagers
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US9554071B2 (en) 2006-01-13 2017-01-24 Micron Technology, Inc. Method and apparatus providing pixel storage gate charge sensing for electronic stabilization in imagers
WO2008057527A3 (fr) * 2006-11-07 2008-10-02 Eastman Kodak Co Stockage d'images multiples sur capteur
WO2008088477A3 (fr) * 2006-12-20 2009-02-12 Carestream Health Inc Réseau d'imagerie utiliser pour saisir plusieurs images
US8558929B2 (en) 2006-12-20 2013-10-15 Carestream Health, Inc. Imaging array for multiple frame capture
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CN103348475A (zh) * 2011-02-09 2013-10-09 意法半导体(R&D)有限公司 传感器的或涉及传感器的改进
US9100605B2 (en) 2011-02-09 2015-08-04 Stmicroelectronics (Research & Development) Limited Global shutter with dual storage
CN103348475B (zh) * 2011-02-09 2016-08-10 意法半导体(R&D)有限公司 传感器的或涉及传感器的改进

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