WO2001011932A1 - Electroplating solution, method for fabricating multilayer printed wiring board using the solution, and multilayer printed wiring board - Google Patents
Electroplating solution, method for fabricating multilayer printed wiring board using the solution, and multilayer printed wiring board Download PDFInfo
- Publication number
- WO2001011932A1 WO2001011932A1 PCT/JP2000/004418 JP0004418W WO0111932A1 WO 2001011932 A1 WO2001011932 A1 WO 2001011932A1 JP 0004418 W JP0004418 W JP 0004418W WO 0111932 A1 WO0111932 A1 WO 0111932A1
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- WO
- WIPO (PCT)
- Prior art keywords
- resin
- printed wiring
- wiring board
- multilayer printed
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/38—Electroplating: Baths therefor from solutions of copper
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3465—Application of solder
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Definitions
- Electrolytic plating liquid method for manufacturing multilayer printed wiring board using the liquid
- the present invention relates to an electrolytic plating liquid used for producing a multilayer printed wiring board, a method for producing a multilayer printed wiring board using the electrolytic plating liquid, and a multilayer printed wiring board.
- Multilayer printed wiring boards so-called multilayer build-up wiring boards, are manufactured by a semi-additive method or the like, and are mounted on a resin substrate, called a core, which is strengthened by a glass cloth of about 0.5 to 1.5 mm. It is manufactured by alternately laminating conductive circuits made of copper or the like and interlayer resin insulating layers. The connection between the conductor circuits via the inter-layer resin insulation layer of the multilayer printed wiring board is made by via holes.
- build-up multilayer printed wiring boards have been manufactured by a method disclosed in, for example, Japanese Patent Application Laid-Open No. Hei 9-130500.
- a through-hole is formed in the copper-clad laminate on which the copper foil is stuck, and then a through-hole is formed by performing electroless copper plating.
- the surface of the substrate is etched into a conductor pattern to form a conductor circuit, and a roughened surface is formed on the surface of the conductor circuit by electroless plating or etching.
- exposure and development processing are performed to form a via hole opening, and then the interlayer resin insulating layer is subjected to UV curing and main curing.
- a thin metal layer is formed, a plating resist is formed on the metal layer, and a thickening is performed by electrolytic plating. After the plating resist is removed, etching is performed to form a conductor circuit connected to the underlying conductor circuit by a via hole.
- solder resist to protect the conductor circuit After forming a layer, plating the area where the opening is exposed for connection with electronic components such as IC chips and mother boards, etc., and then printing solder paste to form solder bumps Complete the manufacture of build-up multilayer printed wiring boards.
- FIG. 25 is a cross-sectional view showing a cross section of a via hole of a conventional multilayer printed wiring board.
- a stacked via structure (a structure in which a via hole is formed directly above a via hole, see Fig. 1) is required as a structure of a built-up multilayer printed wiring board that reduces the wiring distance. ing.
- a stacked via structure a structure in which a via hole is formed directly above a via hole, see Fig. 1
- the present inventors have conducted intensive studies in view of the above problems, and as a result, have found that the use of an electrolytic plating solution containing a specific leveling agent and an additive consisting of a lubricating agent at a specific ratio makes it possible to obtain a via hole opening. That the upper surface of the via hole and the upper surface of the conductor circuit in the same layer can be made substantially flush with each other. Reached.
- the electrolytic plating solution of the present invention is an electrolytic plating solution used for manufacturing a multilayer printed wiring board in which a resin insulating layer and a conductor circuit are sequentially laminated on a substrate on which a conductor circuit is provided.
- a resin insulating layer and a conductor circuit are sequentially laminated on a substrate on which a conductor circuit is provided.
- At least one selected from the group consisting of polyethylene, derivatives thereof, gelatin and derivatives thereof as the leveling agent, and as the brightening agent, sulfur oxide, its related compounds, hydrogen sulfide, It is desirable to use at least one selected from the group consisting of related compounds and other sulfur compounds.
- the method for producing a multilayer printed wiring board according to the first aspect of the present invention includes at least the following steps (a) to (e):
- the method for producing a multilayer printed wiring board according to the second aspect of the present invention includes the following steps (a) to (d):
- the metal layer is preferably formed by performing sputtering, plating, or sputtering and plating.
- the resin insulating layer is a force that is at least one selected from the group consisting of a fluororesin, a polyolefin-based resin and a polyphenylene-based resin, or a resin composite containing a thermoplastic resin and a thermosetting resin. Desirably the body.
- the leveling agent contained in the electrolytic plating solution is selected from the group consisting of polyethylene, derivatives thereof, gelatin and derivatives thereof. And at least one selected from the group consisting of sulfur oxides, its related compounds, hydrogen sulfide, its related compounds, and other sulfur compounds. It is desirable to use one kind.
- the multilayer printed wiring board of the present invention is a multilayer printed wiring board in which a resin insulating layer and a conductive circuit are sequentially laminated on a substrate on which a conductive circuit is provided, and vertically adjacent conductive circuits are connected by via holes.
- the via hole is filled with metal
- the upper surface of the via hole and the upper surface of the conductor circuit in the same layer are substantially on the same plane, and the distance from the bottom surface to the top surface of the via hole is The thickness is 2 to 7 times the thickness of the conductor circuit.
- the resin insulating layer preferably has a dielectric constant at 1 GHz of 3.0 or less.
- the multilayer printed wiring board is desirably manufactured by using the first or second method for manufacturing a multilayer printed wiring board of the present invention.
- FIG. 1 is a sectional view showing one section of the multilayer printed wiring board of the present invention.
- 3 (a) to 3 (d) are cross-sectional views showing a part of the manufacturing process of the multilayer printed wiring board of the present invention.
- 4 (a) to 4 (d) are cross-sectional views showing a part of the manufacturing process of the multilayer printed wiring board of the present invention.
- FIGS. 5A to 5C are cross-sectional views showing a part of the manufacturing process of the multilayer printed wiring board of the present invention.
- 6 (a) to 6 (c) are cross-sectional views showing a part of the manufacturing process of the multilayer printed wiring board of the present invention.
- FIG. 7A is a cross-sectional view showing a part of the manufacturing process of the multilayer printed wiring board of the present invention.
- FIGS. 8A to 8D are cross-sectional views showing a part of the manufacturing process of the multilayer printed wiring board of the present invention.
- FIGS. 9A to 9D are cross-sectional views showing a part of the manufacturing process of the multilayer printed wiring board of the present invention.
- FIGS. 10A to 10C are cross-sectional views showing a part of the manufacturing process of the multilayer printed wiring board of the present invention.
- FIGS. 11 (a) to 11 (c) are cross-sectional views showing a part of the manufacturing process of the multilayer printed wiring board of the present invention.
- 12 (a) to 12 (c) are cross-sectional views showing a part of the manufacturing process of the multilayer printed wiring board according to the present invention.
- 13 (a) and 13 (b) are cross-sectional views showing a part of the manufacturing process of the multilayer printed wiring board of the present invention.
- FIGS. 14A to 14D are cross-sectional views showing a part of the manufacturing process of the multilayer printed wiring board of the present invention.
- FIGS. 15A to 15D are cross-sectional views showing a part of the manufacturing process of the multilayer printed wiring board of the present invention.
- FIGS. 17A to 17C are cross-sectional views showing a part of the manufacturing process of the multilayer printed wiring board of the present invention.
- FIGS. 18 (a) to 18 (c) are cross-sectional views showing a part of the manufacturing process of the multilayer printed wiring board of the present invention.
- FIGS. 19 (a) to 19 (d) are cross-sectional views showing a part of the manufacturing process of the multilayer printed wiring board of the present invention.
- 20 (a) to 20 (d) are cross-sectional views showing a part of the manufacturing process of the multilayer printed wiring board of the present invention.
- 21 (a) to 21 (d) are cross-sectional views showing a part of the manufacturing process of the multilayer printed wiring board of the present invention.
- FIGS. 22A to 22C are cross-sectional views showing a part of the manufacturing process of the multilayer printed wiring board of the present invention.
- FIGS. 23 (a) to 23 (c) are cross-sectional views showing a part of the manufacturing process of the multilayer printed wiring board of the present invention.
- FIG. 24 is a microscope photograph showing a cross section of a via hole of the multilayer printed wiring board of the present invention.
- FIG. 25 is a micrograph showing a cross section of a via hole of a conventional multilayer printed wiring board. Explanation of reference numerals
- the electroplating solution of the present invention is an electroplating solution used for manufacturing a multilayer printed wiring board in which a resin insulating layer and a conductor circuit are sequentially laminated on a substrate provided with a conductor circuit. It contains 1 copper sulfate, 30-200 gZ 1 sulfuric acid, 25-90 mg of chlorine ion, and an additive of at least 1-100 OmgZ 1 consisting of a leveling agent and a brightener. And
- the via hole opening is completely filled with metal, and the upper surface of the via hole and the conductor circuit in the same layer are formed.
- a via hole (hereinafter, such a via hole is also referred to as a field via) whose upper surface is substantially on the same plane can be formed. That is, the electrolytic plating solution of the present invention is most suitable for an electrolytic plating solution for field via.
- the electrolytic plated solution consists 50 to 300 g / 1 of copper sulfate, 30 to 200 8 1 of sulfuric acid, 25 ⁇ 9 OmgZ 1 of chlorine ions, and at least a leveling agent and brightening agent l ⁇ It contains 1000 mg of additives.
- the concentration of sulfuric acid is less than 30 g Z 1
- the liquid resistance becomes large, so that plating is difficult to deposit, and if it exceeds 200 1, copper sulfate tends to be crystallized.
- the chloride ion concentration is less than 25 mg / 1, the gloss of the plating film is lowered, and if it exceeds 9 Omg / 1, the anode is difficult to dissolve.
- a field via can be formed regardless of the opening diameter of the via hole, the material and thickness of the resin insulating layer, the presence or absence of the roughened surface of the resin insulating layer, and the like.
- the electroplating solution contains a high concentration of copper ions, the copper ions are sufficiently introduced into the opening for the via hole. It can be supplied and plated at the via hole opening at a plating speed of 4 ° to 100 ⁇ time, which can speed up the electrolytic plating process.
- the electrolytic plating solution contains sulfuric acid at a high concentration, the solution resistance during plating can be reduced. Therefore, the current density is high, and the growth of the plating film at the opening for the via hole is not hindered, which is suitable for forming a field via structure.
- Desirable composition of the electrolytic plating solution is 100 to 250 g Z1 copper sulfate, 50 to 150 g / 1 sulfuric acid, 30 to 70 mg Zl chlorion, and The composition contains at least 1 to 600 mg of an additive consisting of a leveling agent and a brightening agent.
- the additive only needs to be composed of at least a leveling agent and a brightener, and may contain other components.
- the leveling agent for example, it is desirable to use at least one selected from the group consisting of polyethylene, its derivatives, gelatin and its derivatives.
- the polyethylene derivative is not particularly limited, and includes, for example, polyethylene isophthalate, polyethyleneimine, polyethylene oxide, polyethylene glycol, polyethylene glycol ester, polyethylene glycol ether, polyethylene sulfide, polyether and the like. Can be. Among them, it is preferable to use polyethylene dalicol or gelatin. It is highly versatile and does not damage the resin insulation layer or metal film.
- the brightener for example, it is desirable to use at least one selected from the group consisting of sulfur oxide, its related compound, hydrogen sulfide, its related compound, and other sulfur compounds.
- the oxide sulfur and its related compounds are not particularly limited, and include, for example, sulfonic acid compounds, sulfone compounds, sulfite compounds, and other oxide sulfur compounds.
- the sulfonic acid-based compound is not particularly limited, and examples thereof include sulfobenzoic acid, sulfobenzoate, snorefoanthraquinone, su / lefomethane, sulfoethane, sulfocarbamide, sulfosuccinic acid, sulfosuccinate, sulfoacetic acid, and sulfosalidium.
- Examples include tinoleic acid, snorefosianuric acid, sulfocyan, sulfocyanate, sulfonate, sulfovic acid, sulfophthalic acid, sulfonic acid amide, sulfonic acid imide, and sulfocarbonyl compounds such as sulfocarbanilide. be able to.
- the sulfone compound is not particularly limited, and examples thereof include sulfonal, sulfonyl diacetate, sulfonyl dipheninolemethane, s / reoxynoleic acid, snolefoxylate, sulfonamide, sulfonimide and the like, and sulfonyl chloride compound and the like. Can be mentioned.
- the sulfite compound is not particularly limited, and examples thereof include sulfite, ammonium sulfite, potassium sulfite, getyl sulfite, dimethyl sulfite, sodium hydrogen sulfite, and ester sulfite compounds.
- the above-mentioned other oxide sulfur compounds are not particularly restricted but include, for example, sulfoxide.
- the hydrogen sulfide and its related compounds are not particularly limited, and include, for example, sulfonium compounds and sulfonium salts.
- the other sulfur compounds are not particularly limited, and include, for example, bisdisulphide.
- the electrolytic plating solution of the present invention further comprises a multilayer substrate by containing the above-mentioned brightener.
- the via hole opening can be completely filled with metal, and by containing the above leveling agent, the upper surface of the via hole and the upper surface of the conductor circuit in the same layer are substantially the same. It can be formed in a plane.
- the brightener activates a low current portion of the via hole opening, thereby accelerating plating deposition on the via hole opening and adsorbing the leveling agent on the surface of the conductor circuit. This suppresses the deposition of plating on the surface of the conductor circuit.
- the blending amount of the leveling agent is desirably 1 to 100 OmgZ1, and the blending amount of the brightener is desirably 0.1 to 10 OmgZ1.
- the ratio of the two is preferably 2: 1 to 10: 1.
- the amount of the above-mentioned leveling agent is too small, the amount of the leveling agent adsorbed on the surface of the conductive circuit is small, and plating deposition on the conductive circuit is accelerated.
- the amount of the leveling agent is too large, the amount of the leveling agent adsorbed to the bottom of the via hole opening is large, and the deposition of plating on the via hole opening becomes slow.
- the amount of the brightener is too small, the bottom of the via hole opening cannot be activated, and the via hole opening cannot be completely filled with metal by plating.
- the amount is too large, the deposition of plating on the conductor circuit portion is accelerated, and a step is formed between the upper surface of the conductor circuit and the upper surface of the via hole.
- the electrolytic plating method using the electrolytic plating liquid having such a configuration is not particularly limited, and the following electrolytic plating method and the like can be used.
- the DC electroplating method which is a general electroplating method, or the method of controlling the current to a square-wave pulse current by alternately repeating supply and interruption of the cathode current (PC Plating method), pulse-reverse electric plating method (PR plating method), in which current is controlled using periodic reversal waves by alternately inverting and supplying power source current and anode current supply alternately.
- DC plating method which is a general electroplating method, or the method of controlling the current to a square-wave pulse current by alternately repeating supply and interruption of the cathode current
- PR plating method pulse-reverse electric plating method
- a method of alternately applying a high-density current pulse and a low-density current pulse as a sword current can be used.
- the method for producing a multilayer printed wiring board according to the first aspect of the present invention comprises at least the following steps (a)
- a substrate having a conductive circuit formed on a surface of an insulating substrate is prepared.
- a resin substrate is desirable, and specific examples include a glass epoxy substrate, a polyimide substrate, a bismaleimide triazine resin substrate, a fluororesin substrate, a ceramic substrate, and a copper-clad laminate.
- a through hole is formed in the insulating substrate with a drill or the like, and the wall surface of the through hole and the surface of the copper foil are electrolessly plated to form a surface conductive film and a through hole.
- Copper plating is preferred as the electroless plating.
- a roughened surface is usually formed on the inner wall of the through hole and the surface of the electroless plated film. Examples of the roughening treatment include blackening (oxidation), monoreduction treatment, spray treatment with a mixed aqueous solution of an organic acid and a cupric complex, and treatment with Cu—Ni—P needle-like alloy plating.
- a conductive circuit-shaped etching resist is formed on the electroless-plated substrate, and a conductive circuit is formed by etching.
- a resin filler is applied to the surface of the substrate on which the conductive circuit is formed and dried to a semi-cured state, and then polished to grind the resin filler layer and the upper part of the conductive circuit. Flatten both main surfaces of the substrate. Thereafter, the resin filler layer is completely cured.
- a roughened layer or a roughened surface (hereinafter, also referred to as a roughened layer) is formed on the conductor circuit as necessary.
- the roughening treatment method include blackening (oxidation) monoreduction treatment, spray treatment with a mixed aqueous solution of an organic acid and a cupric complex, and treatment with a Cu—Ni—P alloy.
- a coating layer made of tin, zinc, copper, nickel, cobalt, thallium, lead, etc. is formed on the surface of the roughened layer by electroless plating and vapor deposition.
- an uncured resin layer to be a resin insulating layer is formed on the conductor circuit on which the roughened layer is formed through a post-process.
- thermosetting resin As the material of the resin insulating layer, a thermosetting resin, a thermoplastic resin, a resin obtained by sensitizing a part of the thermosetting resin, or a composite resin thereof can be used.
- the uncured resin layer may be formed by applying an uncured resin, or may be formed by thermocompression bonding an uncured resin film. Further, a resin film in which a metal layer such as a copper foil is formed on one surface of an uncured resin film may be attached. When such a resin film is used, an opening is provided by irradiating a laser beam after etching a metal layer in a via hole forming portion. As the resin film on which the metal layer is formed, a resin-coated copper foil or the like can be used.
- a polyolefin resin a polyphenylene resin (PPE, PPO, etc.), a fluorine resin, and the like are preferable.
- Low dielectric constant This is because it is suitable for forming an edge layer.
- polystyrene-based resin examples include the above-mentioned polyethylene, polypropylene, polyisobutylene, polybutadiene, polyisoprene, 2-norbornene, 5-ethylidene-2-norbornene, and copolymers of these resins.
- system resin examples include ethyl Z tetrafluoroethylene copolymer resin (ETFE), polychlorinated trifluoroethylene (PCTFE), and the like.
- a resin composite containing the thermoplastic resin and the thermosetting resin can also be used as a material of the resin insulating layer.
- thermoplastic resin examples include polysulfone (PSF), polyethersulfone (PES), polyphenylene sulphone (PPS), polyphenylene sulfide (PPES), polyphenylene ether (PPE), and polystyrene.
- PSF polysulfone
- PES polyethersulfone
- PES polyphenylene sulphone
- PPES polyphenylene sulfide
- PPE polyphenylene ether
- polystyrene examples include teliumimide (PI), phenoxy resin, and fluororesin.
- polysulfone PSF
- polyestersulfone PES
- polyether imide PI
- Z or phenoxy resin PSF
- PSF polysulfone
- PET polyestersulfone
- PI polyether imide
- Z or phenoxy resin Z or phenoxy resin
- thermosetting resin examples include an epoxy resin, a phenol resin, and a polyimide resin.
- the thermosetting resin may be a photosensitized resin, specifically, for example, a resin obtained by subjecting a thermosetting group to methacrylic acid, acrylic acid, or the like to an acrylation reaction. .
- acrylated epoxy resin is desirable.
- an epoxy resin having two or more epoxy groups in one molecule is more preferable.
- epoxy resin examples include cresol novolak type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolak type epoxy resin, alkylphenol novolak type epoxy resin, biphenol F type epoxy resin, naphthalene type Epoxy resins, dicyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, alicyclic epoxy resins, and the like. These may be used alone or in combination of two or more. Is also good. Thereby, it becomes excellent in heat resistance and the like.
- thermosetting resin thermoplastic resin 95/5 to 50/50. This is because a high toughness value can be secured without impairing the heat resistance.
- the resin composite may be a photosensitive resin provided with photosensitivity.
- a photosensitive resin When a photosensitive resin is used, an opening for a via hole can be formed by exposure and development.
- Specific examples of the above resin complex include, for example, particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble particles”) dispersed in a resin which is hardly soluble in an acid or an oxidizing agent (hereinafter referred to as a “slightly soluble resin”). And a resin composition for forming a roughened surface.
- the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble resin particles”), inorganic particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble inorganic particles”), and metals soluble in an acid or an oxidizing agent. Particles (hereinafter, soluble metal particles). These soluble particles may be used alone or in combination of two or more.
- the shape of the soluble particles is not particularly limited, and examples thereof include a spherical shape and a crushed shape. Further, the shape of the soluble particles is desirably a uniform shape. This is because a roughened surface having unevenness with a uniform roughness can be formed.
- the average particle size of the soluble particles is desirably 0.1 to 10 / zm. Within this range, two or more different particle sizes may be contained. That is, it contains soluble particles having an average particle size of 0.1 to 0.5 // m and soluble particles having an average particle size of 1 to 3 jum. As a result, a more complicated roughened surface can be formed, and the adhesion to the conductor circuit is excellent.
- the particle size of the soluble particles is the length of the longest portion of the soluble particles.
- the soluble resin particles are not particularly limited as long as they dissolve at a higher rate than the poorly soluble resin when immersed in a solution containing an acid or an oxidizing agent.
- Examples of the specific examples thereof include epoxy resins and epoxy resins. Phenolic resin, polyimide resin, poly T / JP00 / 04418
- Examples include resins made of phenylene resin, polyolefin resin, fluororesin, and amino resin (melamine resin, urea resin, guanamine resin), and may be made of one of these resins. It may be a mixture of the above resins.
- These soluble resin particles include (a) a soluble resin powder having an average particle size of 10 / m or less, (b) an aggregated particle obtained by aggregating a soluble resin powder having an average particle size of 2 / im or less, (c) A mixture of a soluble resin powder having an average particle size of 2 to 10 m and a soluble resin powder having an average particle size of 2 ⁇ m or less, (d) a soluble resin powder having an average particle size of 2 to 10 // m Pseudo particles obtained by adhering at least one of a soluble resin powder and an inorganic powder having an average particle diameter of 2 ⁇ or less to the surface of the particles, (e) an average particle diameter of 0.1 to 0.8 ⁇ A mixture of a soluble resin powder and a soluble resin powder having an average particle size of more than 0.8 / m and less than 2 / zm, and (f) a soluble resin powder having an average particle size of 0.1 to 1. desirable. This is because these can form more
- the soluble resin particles resin particles made of rubber can also be used.
- the rubber include polybutadiene rubber, various modified polybutadiene rubbers such as epoxy-modified, urethane-modified, (meth) acrylonitrile-modified, and (meth) acrylonitrile-butadiene rubber containing a carboxyl group.
- the soluble resin particles are easily dissolved in an acid or an oxidizing agent.
- an acid other than a strong acid can be dissolved, and when dissolving the soluble resin particles using an oxidizing agent, permanganese having a relatively weak oxidizing power is used. It can also dissolve in acids.
- Examples of the soluble inorganic particles include particles made of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds, and silicon compounds.
- Examples of the aluminum compound include alumina and aluminum hydroxide.
- Examples of the calcium compound include calcium carbonate and calcium hydroxide.
- Examples of the potassium compound include potassium carbonate.
- Examples of the magnesium compound include magnesia and doloma. And basic magnesium carbonate.
- Examples of the silicon compound include silica and zeolite. These may be used alone or in combination of two or more.
- soluble metal particles examples include particles made of at least one selected from the group consisting of copper, nickel, iron, zinc, lead, gold, silver, aluminum, magnesium, calcium, and silicon. These soluble metal particles may have a surface layer coated with a resin or the like in order to ensure insulation.
- the combination of the two types of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both have low conductivity, so that insulation between the upper and lower conductor circuits can be ensured, thermal expansion can be easily adjusted with the poorly soluble resin, and cracks occur in the resin insulation layer. This is because no separation occurs between the resin insulating layer and the conductor circuit.
- the hardly soluble resin may be any resin that can maintain the shape of the roughened surface when the roughened surface is formed by using an acid or an oxidizing agent in the resin insulating layer.
- a mixture with a curable resin can be used.
- the soluble particles are substantially uniformly dispersed in the hardly-soluble resin. This is because a roughened surface having unevenness with a uniform roughness can be formed, and adhesion to a conductor circuit including via holes can be ensured.
- a film containing soluble particles only in the surface layer forming the roughened surface may be used. In this case, since the portions other than the surface layer of the film are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the resin insulating layer is reliably maintained.
- the mixing weight ratio of the soluble particles is preferably 5 to 50% by weight, more preferably 10 to 40% by weight, based on the solid content of the hardly soluble resin.
- the mixing weight ratio of the soluble particles is less than 5% by weight, a roughened surface with sufficient roughness may not be formed. If the mixing ratio exceeds 50% by weight, an acid or an oxidizing agent may be used. When forming the roughened surface by dissolving the soluble particles, it dissolves to the deep part of the resin insulation layer, and the insulation between the upper and lower conductor circuits via the resin insulation layer cannot be secured. May cause short circuit.
- the resin composition for forming a roughened surface desirably contains a curing agent and other components in addition to the thermoplastic resin and the thermosetting resin.
- the curing agent examples include an imidazole-based curing agent, an amine-based curing agent, a guanidine-based curing agent, an epoxy product of these curing agents, a microcapsule-encapsulation of these curing agents, and triphenylphosphine.
- organic phosphine compounds such as tetraphenylphosphonium and tetraphenylborate.
- the content of the curing agent is desirably 0.05 to 10% by weight with respect to the resin composition for forming a roughened surface. If the amount is less than 0.05% by weight, when forming the resin insulating layer, the resin composite does not sufficiently cure, and a roughened surface is formed on the surface of the resin insulating layer by using an acid or an oxidizing agent, and the acid and the like are removed. ⁇ ⁇ ⁇ The degree of penetration into the resin film increases, and the insulation of the resin insulation layer may be impaired. On the other hand, if it exceeds 10% by weight, an excessive curing agent component may modify the composition of the resin, which may cause a decrease in reliability. Examples of the other components include fillers such as inorganic compounds and resins that do not affect the formation of the roughened surface.
- Examples of the inorganic compound include silica, alumina, dolomite, and the like.
- Examples of the resin include polyimide resin, polyacryl resin, polyamide imide resin, polyfuylene resin, melanin resin, and the like. And olefin resin. By incorporating these fillers, the thermal expansion coefficient can be matched, the heat resistance and the chemical resistance can be improved, and the performance of the multilayer printed wiring board can be further improved.
- the resin composition for forming a roughened surface may contain a solvent.
- the solvent include ketones such as acetone, methyl ethyl ketone, and cyclohexanone, ethyl acetate, butyl acetate, and aromatic hydrocarbons such as cellosolve acetate, toluene, and xylene. These may be used alone or in combination of two or more.
- a roughened surface can be easily formed on the layer, and when a plating layer is formed using the electrolytic plating solution of the present invention on the resin insulation layer on which the roughened surface is formed, Since no excessive stress is generated in the plating layer and the stress is relieved, cracks and peeling do not occur in the resin insulating layer. In particular, favorable effects can be obtained in the peripheral portion of the field via.
- a resin insulating layer having a via hole opening is formed by performing exposure and development processing or laser processing.
- the opening for the via hole is formed by using a laser beam or an oxygen plasma. In some cases, it is performed by exposure and development processing or laser processing. The exposure and development treatment is performed before the uncured photosensitive resin layer is cured. The laser treatment can be performed before or after thermal curing or light curing.
- a photomask (preferably a glass substrate) on which a circular pattern for forming an opening for a via hole was drawn was placed with the circular pattern side in close contact with the photosensitive resin insulating layer. Then, exposure is performed, and immersion in a developing solution or spraying of a developing solution is performed.
- the laser light to be used is, for example, a carbon dioxide (co 2 ) laser, an ultraviolet laser, an excimer laser,
- YAG laser and the like. Of these, excimer lasers and short-pulse carbon dioxide lasers are preferred.
- the excimer laser can form a large number of via hole openings at once by using a mask or the like in which penetrating light is formed in a portion where the via hole opening is formed, as described later. This is because the carbon dioxide gas laser has a small amount of resin remaining in the opening and little damage to the resin at the periphery of the opening.
- a hologram type excimer laser is used among the excimer lasers. It is desirable.
- the hologram method is a method of irradiating a laser beam to a target object through a hologram, a condenser lens, a laser mask, a transfer lens, and the like. By using this method, a large number of openings can be formed by one irradiation. It can be formed efficiently.
- the pulse interval is 1 0 4 to 1 0 _ 8 Byodea Rukoto is desirable.
- the time for irradiating the laser for forming the opening is preferably 10 to 500 ⁇ sec.
- the through hole of the mask in which the through hole is formed in the portion where the via hole opening is formed needs to be a perfect circle in order to make the spot shape of the laser beam a perfect circle.
- the diameter of the hole is desirably about 0.1 to 2 mm.
- desmearing is preferably performed.
- the desmear treatment can be performed using an oxidizing agent composed of an aqueous solution such as chromic acid and permanganate.
- the oxygen bra Zuma may be treated with a mixed plasma or corona discharge or the like of CF 4 and oxygen.
- the surface can also be modified by irradiating ultraviolet rays using a low-pressure mercury lamp.
- the surface of the resin insulating layer provided with the opening for the via hole is roughened.
- the roughening is performed by dissolving and removing soluble resin particles present on the surface of the resin insulating layer with an acid or an oxidizing agent. .
- phosphoric acid When performing the above acid treatment, phosphoric acid, hydrochloric acid, sulfuric acid, or an organic acid such as formic acid or acetic acid can be used, and it is particularly preferable to use an organic acid. This is because the metal conductor layer exposed from the via hole is hardly corroded when the roughening process is performed.
- chromic acid or permanganate such as potassium permanganate.
- At least one kind of thin metal selected from the group consisting of Cu, Ni, P, Pd, Co and W is formed on the surface of the resin insulating layer and the opening for the via hole. Form a layer.
- the thickness of this metal layer is preferably from 0.1 to 5 zm, more preferably from 0.5 to 2 / zm.
- the metal layer is desirably formed by sputtering, plating, or sputtering and plating.
- the plating resist a commercially available photosensitive dry film or liquid resist can be used.
- the plating resist can be formed by attaching a photosensitive dry film or applying a liquid resist, performing an ultraviolet exposure treatment, and developing with an alkaline aqueous solution.
- an electrolytic plating film is formed on the plating resist non-formed portion formed in (9). This is performed by immersing the substrate on which the metal layer and the plating resist are formed in the electrolytic plating solution.
- the leveling agent contained in the electrolytic plating solution it is desirable to use at least one selected from the group consisting of polyethylene, derivatives thereof, gelatin and derivatives thereof. It is desirable to use at least one selected from the group consisting of sulfur oxides, their related compounds, hydrogen sulfide, their related compounds, and other sulfur compounds as the brightener contained in.
- electrolytic copper plating is desirable, and its thickness is desirably 3 to 25 / zm in the conductor circuit portion other than the via hole. If the thickness is less than 3 zm, the upper surface of the via hole and the upper surface of the conductor circuit in the same layer may not be almost flush with each other. If it is intended to form a conductor circuit having a thickness of more than 25 / im, the plating resist The thickness may be so large that it becomes difficult for the electrolytic plating solution to enter the non-plated resist forming area. More preferably, it is 5 to 15 ⁇ . Further, it is desirable that the distance from the bottom surface to the top surface of the formed via hole is 2 to 7 times the thickness of the conductor circuit portion.
- the method for the electroplating is not particularly limited, it is preferable to use the direct current electroplating as described above.
- the above-mentioned etching is performed by chemical etching using a sulfuric acid / hydrogen peroxide aqueous solution, an aqueous solution of a persulfate such as ferric chloride, cupric chloride, or ammonium persulfate as an etching solution, or physical etching by ion beam etching. Etc. are used.
- the palladium catalyst nucleus exposed on the non-conductive circuit part is dissolved and removed using chromic acid, sulfuric acid, hydrogen peroxide, or the like.
- steps (3) to (11) If necessary, repeat steps (3) to (11) and apply electroless plating or etching to the uppermost conductive circuit under the same conditions as in step (3) above. A roughened layer or surface is formed thereon.
- solder resist layer is formed on the substrate surface including the uppermost conductive circuit.
- solder resist layer include those made of a polyphenylene ether resin, a polyolefin resin, a fluororesin, a thermoplastic elastomer, a solder resist resin composition, or the like.
- the solder resist layer is formed by applying an uncured resin (resin composition) by a roll coater method or the like, and performing the above-described opening treatment and curing treatment.
- solder resist resin composition examples include (meth) acrylate, a novolak type epoxy resin, an imidazole curing agent, a bifunctional (meth) acrylate monomer, and a molecular weight of about 500 to 500 (Meth) Estenole acrylate resin, thermosetting resin composed of bisphenol-type ester resin, etc., photosensitive monomer such as polyvalent acryl-based monomer, paste-like fluid containing glycol ether-based solvent, etc. It is desirable that the viscosity be adjusted to 1 to 10 Pa ⁇ s at 25 ° C.
- Examples of the (meth) acrylates of the above novolak type epoxy resins include epoxy resins obtained by reacting phenolic novolak or credinolenolac glycidinoleone tenore with acrylinoleic acid / methacrylic acid.
- the bifunctional (meth) acrylic acid ester monomer is not particularly limited, and examples thereof include various diols and esters of acrylic acid and methacrylic acid.
- FIG. 1 is a cross-sectional view showing one section of the multilayer printed wiring board of the present invention.
- a first method of manufacturing a multilayer printed wiring board of the present invention as shown in FIG. It is possible to manufacture a printed wiring board in which the opening is completely filled with metal, and the upper surface of the via hole 7 and the upper surfaces of the conductor circuits 4 and 5 in the same layer are substantially flush with each other.
- Printed wiring boards can be manufactured.
- the stacked via structure is a structure in which an upper via hole 7 is provided immediately above the via hole 7.
- the method for producing a multilayer printed wiring board according to the second aspect of the present invention comprises at least the following steps (a) to (d):
- the method for manufacturing a multilayer printed wiring board according to the second aspect of the present invention is different from the method for manufacturing a multilayer printed wiring board according to the first aspect of the present invention only in the steps (c) and (d). Steps other than the above (c) and (d) can be performed using the same method as the first method for producing a multilayer printed wiring board of the present invention. Therefore, here The steps (c) and (d) of the second production method of the present invention will be mainly described.
- a thin metal layer is formed on the insulating layer and the via hole opening in the same manner as in the steps (1) to (8) of the method for manufacturing a multilayer printed wiring board of the first invention. You.
- an electrolytic plating film is formed on the metal layer formed in (1). This is performed by immersing the substrate on which the metal layer is formed in the electrolytic plating solution.
- the leveling agent contained in the electroplating solution it is preferable to use at least one selected from the group consisting of polyethylene, derivatives thereof, gelatin and derivatives thereof. It is desirable to use at least one selected from the group consisting of sulfur oxides, its related compounds, hydrogen sulfide, its related compounds, and other sulfur compounds as the brightener contained in water.
- the thickness thereof is desirably 3 to 25 ⁇ in a conductor circuit portion other than the via hole. If the thickness is less than 3 ⁇ , the upper surface of the via hole and the upper surface of the conductor circuit in the same layer may not be substantially flush with each other, or the conductor circuit may be disconnected during etching. In some cases, the electroplating layer and the metal layer may not be completely removed by the etching. More preferably, it is 5 to 15 ⁇ . It is preferable that the distance from the bottom surface to the top surface of the formed via hole is 2 to 7 times the thickness of the conductive circuit portion.
- the method for the electroplating is not particularly limited, it is preferable to use the direct current electroplating as described above.
- a conductive circuit is formed by performing etching.
- etching resist a commercially available photosensitive dry film or liquid resist can be used.
- the etching resist is peeled off with a strong alkaline aqueous solution, so that the upper conductor circuit and the via hole are formed as independent patterns.
- the above etching is performed by chemical etching using an aqueous solution of persulfate such as aqueous solution of hydrogen sulfate, ferric chloride, cupric chloride, ammonium persulfate, etc. Etching or the like is used.
- persulfate such as aqueous solution of hydrogen sulfate, ferric chloride, cupric chloride, ammonium persulfate, etc. Etching or the like is used.
- the palladium catalyst nucleus exposed on the non-conductive circuit part is dissolved and removed using chromic acid, sulfuric acid, hydrogen peroxide, or the like.
- solder resist layer is formed in the same manner as in the method of manufacturing a multilayer printed wiring board according to the first aspect of the present invention, and solder bumps are formed in the openings of the solder resist layer.
- the production of the multilayer printed wiring board according to the method for producing a multilayer printed wiring board is ended.
- the multilayer printed wiring board of the present invention is a multilayer printed wiring board in which a resin insulating layer and a conductive circuit are sequentially laminated on a substrate on which a conductive circuit is provided, and vertically adjacent conductive circuits are connected by via holes.
- the via hole is filled with metal, the upper surface of the via hole and the upper surface of the conductor circuit in the same layer are substantially flush with each other, and the distance from the bottom surface to the upper surface of the via hole is the thickness of the conductor circuit. It is characterized in that it is 2 to 7 times.
- the multilayer printed wiring board of the present invention since the metal is completely filled in the via hole opening and the upper surface of the via hole and the upper surface of the conductor circuit in the same layer are substantially flush with each other, the conductor circuit including the via hole There is no occurrence of peeling or cracking between the conductor circuit and the resin insulation layer, and no breakage of the conductor circuit in the upper layer of the conductor circuit. Further, the multilayer printed wiring board may have a stacked via structure in which the wiring distance is shortened in order to increase the speed and fineness of the printed wiring board. As the multilayer printed wiring board of the present invention, for example, one having a configuration as shown in FIG. Can be mentioned.
- the distance from the bottom surface to the top surface of the via hole is 2 to 7 times the thickness of the conductor circuit.
- the distance from the bottom surface to the top surface of the via hole exceeds seven times the thickness of the conductor circuit, it is difficult to completely fill the via hole opening with metal, so the top surface of the via hole and the top surface of the conductor circuit on the same layer May not be on substantially the same plane, making it difficult to form a stack via structure.
- the shallower the via hole opening the easier it is to form a field via structure.However, if the distance from the bottom surface to the top surface of the via hole is less than twice the thickness of the conductor circuit, the top surface of the via hole is Disconnection may occur in the conductor circuit when it is higher than the top surface of the circuit or when etching is performed.
- the resin insulating layer of the multilayer printed wiring board desirably has a dielectric constant at 1 GHz of 3.0 or less.
- the resin insulating layer With a dielectric constant of 3.0 or less, it is possible to prevent delays and errors related to electronic signals even when used in a high frequency band of 1 GHz or more.
- the resin used for the resin insulating layer include the same resins as those used in the first or second method for producing a multilayer printed wiring board of the present invention.
- Such a multilayer printed wiring board of the present invention is desirably manufactured by using the first or second method of manufacturing a multilayer printed wiring board of the present invention.
- cresol one novolac type epoxy resin made by Nippon Kayaku Co., molecular weight: 2500
- 25% acrylated product of 80 weight 0 / o resin solution was concentration dissolved in diethylene glycol dimethyl E one ether (DMDG) in 3 5 Parts by weight, photosensitive monomer (Toagosei Co., Ltd., Aronix M315) 3.15 parts by weight, defoamer (Sannopco S-65) 0.5 parts by weight and N-methylpyrrolidone (NMP) 3 .6 parts by weight in container
- DMDG diethylene glycol dimethyl E one ether
- photosensitive monomer Toagosei Co., Ltd., Aronix M315) 3.15 parts by weight
- defoamer Sannopco S-65
- NMP N-methylpyrrolidone
- the resin composite was obtained by mixing the mixed compositions prepared in (i), (ii) and (iii).
- cresol one novolac type epoxy resin made by Nippon Kayaku Co., molecular weight: 2500
- a curing agent As a curing agent, 6.5 parts by weight of an imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals Co., Ltd.) was used.
- the starting material is a copper lamination plate in which 18 ⁇ copper foil 8 is laminated on both sides of a substrate 1 made of glass epoxy resin or BT (bismaleimid triazine) resin with a thickness of 1 mm. 2 (a)).
- the copper-clad laminate was drilled, subjected to an electroless plating process, and etched in a pattern to form a lower conductor circuit 4 and a through hole 9 on both surfaces of the substrate 1.
- the resin filler was pressed into the through hole using a squeegee, and then dried at 100 ° C. for 20 minutes. Next, it corresponds to the conductor circuit non-formed part A mask with an open portion is placed on a substrate, and a layer of resin filler 10 is formed using a squeegee in a conductive circuit non-formed portion, which is a concave portion, at 100 ° C. for 20 minutes. It was dried under the conditions (see Fig. 2 (c)).
- etching may be performed before and after polishing to flatten the land 9 a of the through hole 9 and the roughened surface 4 a formed on the lower conductive circuit 4.
- 5Pa ⁇ s is applied using a roll coater within 24 hours after preparation, left horizontally for 20 minutes, and dried at 60 ° C for 30 minutes (prebake). went. Then, after preparing the resin composite for the upper layer (viscosity: 7 Pa ⁇ s) described in A above, Apply using a roll coater within a period of time, leave it in the horizontal state for 20 minutes, and then dry (pre-bake) it at 60 ° C for 30 minutes to obtain a 35 / ⁇ m thick resin. Layers 2a and 2b of the composite were formed (see Fig. 3 (b)).
- the substrate on which the via hole opening 6 has been formed is immersed in a chromic acid aqueous solution (750 Og / ⁇ ) for 19 minutes to dissolve and remove the epoxy resin particles present on the surface of the resin insulation layer, and remove the surface. It was roughened to obtain a roughened surface. After that, they were immersed in a neutralizing solution (manufactured by Shipley) and washed with water (see Fig. 3 (d)).
- a neutralizing solution manufactured by Shipley
- catalyst nuclei were attached to the surface of the insulating material layer and the inner wall surface of the via hole opening.
- portions other than the conductor circuit were etched by spray etching using an aqueous solution of sulfuric acid and hydrogen peroxide. Subsequently, the resist film was peeled and removed in a 40 gZ1 NaOH aqueous solution at 50 ° C. Thereafter, the substrate was heat-treated at 150 ° C for 1 hour to form a 15 ⁇ thick conductor circuit composed of a metal layer and an electrolytic copper plating film, and a field via (see Fig. 4 (d)). ).
- solder resist layer was cured by performing a heat treatment under the conditions of C for 3 hours, and the solder pad portion (including the via hole and its land portion) with an opening diameter of 200 ⁇ was opened.
- a ⁇ solder resist layer (organic resin insulating layer) 14 was formed.
- a nickel plating layer 15 was formed.
- the substrate was subjected to potassium cyanide (7.6 x 10 _3 mo 1/1), ammonium chloride (1. ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ / ⁇ ), sodium citrate (1.2 x 1 0—imo l /) Nickel plating by immersing in electroless plating solution containing sodium hypophosphite (1.7 x 1 O-'mo 1/1) at 80 ° C for 7.5 minutes On the layer 15, a plating layer 16 having a thickness of 0.03 ⁇ was formed. (18) Thereafter, solder paste is printed in the openings of the solder resist layer 14 and reflowed at 200 ° C. to form solder bumps 17, and a multilayer wiring print having the solder bumps 17 is formed.
- the substrate was manufactured (see Fig. 7 (a)).
- a substrate made of a 0.8 mm thick glass epoxy resin or BT (Bismaleidamide triazine) resin substrate 1 with copper foil 8 of 18 / zm laminated on both sides as a starting material See Figure 8 (a)).
- the copper-clad laminate was drilled, subjected to an electroless plating process, and etched in a pattern to form a lower conductor circuit 4 and a through hole 9 on both sides of the substrate 1.
- a resin filler mainly composed of polyolefin resin is applied to both sides of the substrate using a printing machine to fill the space between the lower-layer conductor circuits 4 and the inside of the through-holes 9, and then heat and dry. (See Fig. 8 (c)). That is, by this step, the resin filler 10 is filled between the lower conductor circuits 4 and in the through holes 9.
- etching may be performed before and after polishing to flatten the land 9a of the through hole 9 and the roughened surface 4a formed on the lower conductor circuit 4.
- thermosetting polyolefin resin sheet with a thickness of 50 ⁇ is applied to both sides of the substrate at a pressure of 0.5 MPa (5 kgf Zcm 2 ) while raising the temperature to 50 to 50 ° C.
- Vacuum lamination was performed to provide a resin insulating layer made of polyolefin resin.
- the degree of vacuum during vacuum bonding was set to 1330 Pa (10 mmHg) (see Fig. 9 (a)).
- the substrate on which the via hole opening 6 was formed was subjected to plasma treatment to roughen the surface of the resin insulating layer (see FIG. 9 (c)).
- plasma treatment was performed for 2 minutes using SV-4540 manufactured by Nippon Vacuum Engineering Co., Ltd. under the conditions of power of 200 W, gas pressure of 0.6 Pa, and temperature of 70 ° C using argon gas as inert gas. Carried out.
- the substrate was conditioned and the catalyst was applied in an alkaline catalyst for 5 minutes.
- portions other than the conductor circuit were etched by spray etching using an aqueous solution of sulfuric acid and hydrogen peroxide. Subsequently, the resist film was peeled and removed in a 40 gZ1 NaOH aqueous solution at 50 ° C. Thereafter, the substrate was subjected to a heat treatment at 150 ° C. for 1 hour to form a 15 ⁇ thick conductor circuit 5 composed of a metal layer and an electrolytic copper plating film, and a field via 7.
- the difference in height from the resin substrate 1 between the upper surface of the formed conductor circuit and the upper surface of the field via was approximately 1 ⁇ or less, and was substantially in the same plane, and no recess was formed on the upper surface of the via hole ( See Figure 10 (c)).
- the above steps (7) to (13) were repeated to form an upper-layer conductor circuit, thereby obtaining an eight-layer multilayer printed wiring board.
- six layers are shown for easy understanding of the structure (see Figs. 11 (a) to 13 (a)).
- the surface conductor circuit was also etched using the same etchant used in the above step (2) to form a roughened surface.
- R6 04 3 parts by weight, also polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., trade name: DPE 6A) 1.5 parts by weight, dispersion defoaming agent (manufactured by San Nopco, trade name: S-65) 0 1.7 Put 1 part by weight in a container and mix with stirring to prepare a mixed composition, and add 2.0 parts by weight of benzofuunone (Kanto Chemical Co., Ltd.) as a photopolymerization initiator to this mixed composition.
- polyvalent acrylic monomer manufactured by Kyoei Chemical Co., trade name: DPE 6A
- dispersion defoaming agent manufactured by San Nopco, trade name: S-65
- Michler's ketone as a sensitizer (manufactured by Kanto Chemical Co., Ltd.) was added at 0.2 parts by weight, and the viscosity was adjusted to 2.0 Pa ⁇ s at 25 ° C. Folder to obtain an resist resins composition.
- solder resist resin composition described in the above (15) on both sides of the multilayer wiring board apply it at a thickness of 20 / m, and at 70 ° C for 20 minutes, after the drying process was carried out under the conditions of 3 0 min 70 ° C, the solder one resist opening portion of the pattern is to thickness of 5mm photomask is brought into close contact to solder one resist layer 1 0 00 m jZcm 2 drawing It was exposed to ultraviolet light and developed with a DMTG solution to form an opening having a diameter of 200 ⁇ m.
- solder resist layer was cured by performing heat treatment at 50 ° C for 3 hours, and the solder pad portion (including the via hole and its land portion) with an opening diameter of 200 zzm was opened. 20 ⁇ solder resist layer (organic resin insulation layer)
- the substrate on which the solder resist layer (organic resin insulating layer) 14 was formed was coated with nickel chloride (2.3 X 1 O ⁇ mo 1/1), sodium hypophosphite (2.8 X 1 O ⁇ mo 1/1) and sodium citrate (1 .. ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ )
- nickel plating layer 15 having a thickness of 5 ⁇ m was formed.
- gold potassium cyanide and the substrate (7. 6 X 1 0- 3 mo 1 Bruno 1), Anmoniumu chloride (1. ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ Bruno 1), sodium Beautique phosphate (1.
- solder paste is printed on the opening of the solder resist layer 14 and reflowed with 20 to form solder bumps 17 to manufacture a multilayer wiring printed board having the solder bumps 17 (See Figure 13 (b)).
- the plating resist was peeled off in an aqueous solution of 40 g / 1 NaOH at 50 ° C. Thereafter, the substrate is heat-treated at 150 ° C for 1 hour, and the metal other than the conductor circuit is removed using an etching solution such as a sulfuric acid-hydrogen peroxide solution. A conductor circuit and a field via having a thickness of 8 ⁇ were formed (see Fig. 16 (d)).
- Bisphenol A type epoxy resin (Epoxy equivalent: 469, Yuka Shell Epoxy Co., Ltd .: 1001) 30 parts by weight, Cresol novolac type epoxy resin (Epoxy equivalent: 21.5, Dainippon Ink & Chemicals, Inc.) 40 parts by weight, Epiclone N-67 3) 40 parts by weight, phenol novolak resin containing a triazine structure (phenolic hydroxyl equivalent: 120, phenolic KA-705052) manufactured by Dainippon Ink and Chemicals, Inc.
- the substrate on which the via hole opening 6 is formed is immersed in a chromic acid aqueous solution (7,500 g / 1) for 19 minutes to dissolve and remove the epoxy resin particles present on the surface of the resin insulating layer, and roughen the surface And a roughened surface was obtained. After that, they were immersed in a neutralizing solution (manufactured by Shipley) and washed with water (see Fig. 20 (d)).
- a neutralizing solution manufactured by Shipley
- catalyst nuclei were attached to the surface of the insulating material layer and the inner wall surface of the via hole opening 6.
- Paste A commercially available photosensitive dry film to the electrolytic copper plated film 1 2, by placing the mask, 1 0 O m exposed with JZC m 2, developed with an 0.8% aqueous solution of sodium carbonate Thus, a plating resist 23 having a thickness of 20 / im was provided (see FIG. 21 (b)).
- the plating resist 23 was peeled off and removed in a 40 g 1 NaOH aqueous solution at 50 ° C. After that, the substrate is heat-treated at 150 ° C for 1 hour, and the metal other than the conductive circuit is removed using an etching solution such as an aqueous solution of sulfuric acid and hydrogen peroxide. A conductor circuit having a thickness of 15 ⁇ and a field via were formed (see Fig. 21 (d)). (8) The same processing as in (1) above was performed on the substrate on which the conductor circuit was formed, and a roughened surface was formed on the surface of the conductor circuit including the field via (see FIG. 22 (a)).
- Example 1 Thereafter, the same steps as (15) to (18) of Example 1 were performed to manufacture a multilayer wiring printed board having solder bumps 17 (see FIG. 23 (c)).
- Example 4 The same procedure as in Example 4 was carried out except that a resin composite film composed of an epoxy resin (thermosetting resin) and a phenolic resin (thermoplastic resin) was used as the resin composite film. A multilayer printed wiring board was manufactured.
- a multilayer printed wiring board was manufactured in substantially the same manner as in Example 1, except that gelatin 40 OmgZ 1 and bisdisulfide 15 Om 1/1 were used as additives for the electrolytic plating solution.
- a multilayer printed wiring board was manufactured in substantially the same manner as in Example 2, except that gelatin bismuth sulfide 150 Om 1/1 was used as an additive for the electrolytic plating solution.
- a multilayer printed wiring board was manufactured in substantially the same manner as in Example 3, except that gelatin 400 mgZl and bisdisulfide 15 Om 1/1 were used as additives for the electrolytic plating solution.
- a multilayer printed wiring board was manufactured in substantially the same manner as in Example 1 except that polyethylene glycol 40 OmgZ 1 and sulfonamide 15 Om 1/1 were used as additives for the electrolytic plating solution.
- Polyethylene glycol 40 OmgZ 1, sulf A multilayer printed wiring board was manufactured in substantially the same manner as in Example 2 except that the sulfonic acid amide 15 Om 1 Z1 was used.
- a multilayer printed wiring board was manufactured in substantially the same manner as in Example 3, except that polyethylene glycol 40 Omg / 1 and sulfonamide amide 15 Om 11 were used as additives for the electrolytic plating solution.
- a multilayer printed wiring board was manufactured in substantially the same manner as in Example 5 except that gelatin 400 mgZl and bisdisulfide 150 m 1/1 were used as additives for the electrolytic plating solution.
- a multilayer printed wiring board was manufactured in substantially the same manner as in Example 5, except that polyethylene glycol 40 OmgZ 1 and sulfonamide 15 Om 11 were used as additives for the electrolytic plating solution.
- a layer of 35 / xm resin composite was formed (see FIGS. 2 (a) to 3 (b)).
- Example 2 Next, in the same manner as (7) of Example 1, except that a photomask film on which a black circle having a diameter of 90 ⁇ was printed was adhered to both sides of the substrate on which the resin composite layer was formed. Thus, a 35 ⁇ thick resin insulation layer having a via hole opening with a diameter of 90 ⁇ was formed (see FIG. 3 (c)). The roughened surface of the lower conductor circuit was exposed at the opening serving as the via hole.
- electrolytic plating was performed on the entire surface of the electroless copper plating film under the following conditions to form an electrolytic plating film 13 having a thickness of 11 ⁇ .
- portions other than the conductor circuit were etched by spray etching using an aqueous solution of sulfuric acid and hydrogen peroxide. Subsequently, the resist film was peeled off and removed in a 401 ° C. aqueous solution at 50 ° C. Thereafter, the substrate was subjected to a heat treatment at 150 ° C. for 1 hour to form a metal layer, an electrolytic copper plating film, a conductive circuit composed of copper, and a field via. (7) The same processing as in (5) above was performed on the substrate on which the conductor circuit was formed, and a roughened surface having a thickness of 2 zm was formed on the surface of the conductor circuit including the field via.
- step (1) of forming the resin composite layer (the steps (1) to (7) of Example 1) is repeated to form a further upper conductive circuit, An eight-layer printed wiring board was obtained.
- the multilayer printed wiring board having the solder bumps obtained in the example and the comparative example was cut with a forceputter, and the cross section was observed with a microscope, and the multilayer printed wiring board according to the example was cut with a cutter.
- the cross section was observed with a microscope, the difference in height from the resin substrate between the upper surface of the conductive circuit and the upper surface of the field via was approximately 1 / im or less on the same plane. Had not been formed.
- the opening for the via hole was not completely filled with metal, and a recess was formed on the upper surface of the via hole.
- the multilayer wiring printed circuit board according to the example had a stacked via structure, and as a result of a conduction test and the like, conduction was also obtained in the stacked via structure.
- the multilayer printed wiring board according to the comparative example as a result of the continuity test and the like, no continuity was obtained in the stacked via structure. Possibility of industrial use
- the metal is completely filled in the opening for the via hole.
- a via hole in which the upper surface of the via hole and the upper surface of the conductor circuit in one layer are substantially coplanar can be formed.
- the metal is completely filled in the via hole opening, and the upper surface of the via hole and the upper surface of the conductor circuit in the same layer are substantially formed.
- Via holes can be formed on the same plane, and a multilayer printed wiring board having a stacked via structure can be manufactured. You.
- the metal is completely filled in the via hole opening, and the upper surface of the via hole and the upper surface of the conductor circuit in the same layer are substantially on the same plane.
- the connection reliability can be improved without the occurrence of peeling cracks between the circuit and the resin insulating layer and the disconnection of the conductor circuit in the upper layer of the conductor circuit.
- the multilayer printed wiring board may have a stack via structure in which the wiring distance is shortened in order to increase the speed and fineness of the printed wiring board.
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrochemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
Claims
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/048,852 US7514637B1 (en) | 1999-08-06 | 2000-07-04 | Electroplating solution, method for fabricating multilayer printed wiring board using the solution, and multilayer printed wiring board |
| EP00942459A EP1207730B1 (en) | 1999-08-06 | 2000-07-04 | Electroplating solution, method for fabricating multilayer printed wiring board using the solution, and multilayer printed wiring board |
| DE60042976T DE60042976D1 (de) | 1999-08-06 | 2000-07-04 | Lösung für die elektrochemische abscheidung, methode, eine leiterplatte unter verwendung dieser lösung herzustellen und mehrschichtige leiterplatte |
| US10/864,400 US7446263B2 (en) | 1999-08-06 | 2004-06-10 | Multilayer printed circuit board |
| US11/056,242 US7993510B2 (en) | 1999-08-06 | 2005-02-14 | Electroplating solution, method for manufacturing multilayer printed circuit board using the same solution, and multilayer printed circuit board |
Applications Claiming Priority (10)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11/224143 | 1999-08-06 | ||
| JP22414399 | 1999-08-06 | ||
| JP2000/156877 | 2000-05-26 | ||
| JP2000156877 | 2000-05-26 | ||
| JP2000/156878 | 2000-05-26 | ||
| JP2000156878 | 2000-05-26 | ||
| JP2000/194619 | 2000-06-28 | ||
| JP2000194620A JP2002050868A (ja) | 1999-08-06 | 2000-06-28 | 多層プリント配線板の製造方法 |
| JP2000/194620 | 2000-06-28 | ||
| JP2000194619A JP4480236B2 (ja) | 1999-08-06 | 2000-06-28 | 電解めっき液、その液を用いた多層プリント配線板の製造方法および多層プリント配線板 |
Related Child Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/048,852 A-371-Of-International US7514637B1 (en) | 1999-08-06 | 2000-07-04 | Electroplating solution, method for fabricating multilayer printed wiring board using the solution, and multilayer printed wiring board |
| US10/864,400 Division US7446263B2 (en) | 1999-08-06 | 2004-06-10 | Multilayer printed circuit board |
| US11/056,242 Division US7993510B2 (en) | 1999-08-06 | 2005-02-14 | Electroplating solution, method for manufacturing multilayer printed circuit board using the same solution, and multilayer printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2001011932A1 true WO2001011932A1 (en) | 2001-02-15 |
Family
ID=27529754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2000/004418 Ceased WO2001011932A1 (en) | 1999-08-06 | 2000-07-04 | Electroplating solution, method for fabricating multilayer printed wiring board using the solution, and multilayer printed wiring board |
Country Status (4)
| Country | Link |
|---|---|
| US (4) | US7514637B1 (ja) |
| EP (2) | EP1207730B1 (ja) |
| DE (2) | DE60042976D1 (ja) |
| WO (1) | WO2001011932A1 (ja) |
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| EP2028915A1 (en) * | 1999-08-12 | 2009-02-25 | Ibiden Co., Ltd. | Multilayer printed wiring board, solder resist composition, method for manufacturing multilayer printed wiring board, and semiconductor device |
| US20100276292A1 (en) * | 2009-04-30 | 2010-11-04 | Moses Lake Industries Inc. | High speed copper plating bath |
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2000
- 2000-07-04 DE DE60042976T patent/DE60042976D1/de not_active Expired - Lifetime
- 2000-07-04 WO PCT/JP2000/004418 patent/WO2001011932A1/ja not_active Ceased
- 2000-07-04 US US10/048,852 patent/US7514637B1/en not_active Expired - Fee Related
- 2000-07-04 DE DE60045566T patent/DE60045566D1/de not_active Expired - Lifetime
- 2000-07-04 EP EP00942459A patent/EP1207730B1/en not_active Expired - Lifetime
- 2000-07-04 EP EP09008814A patent/EP2111087B1/en not_active Expired - Lifetime
-
2004
- 2004-06-10 US US10/864,400 patent/US7446263B2/en not_active Expired - Lifetime
-
2005
- 2005-02-14 US US11/056,242 patent/US7993510B2/en not_active Expired - Fee Related
-
2008
- 2008-02-28 US US12/071,964 patent/US7812262B2/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0419845A2 (en) * | 1989-09-05 | 1991-04-03 | General Electric Company | Method for preparing metallized polyimide composites |
| JPH05308194A (ja) * | 1992-04-30 | 1993-11-19 | Victor Co Of Japan Ltd | 多層印刷配線板の製造方法 |
| JPH1154912A (ja) * | 1997-08-05 | 1999-02-26 | Ngk Spark Plug Co Ltd | 配線基板の製造方法 |
| JPH1168314A (ja) * | 1997-08-21 | 1999-03-09 | Matsushita Electric Ind Co Ltd | 移動体通信機器 |
| JPH11186729A (ja) * | 1997-10-14 | 1999-07-09 | Ibiden Co Ltd | 多層プリント配線板 |
Non-Patent Citations (1)
| Title |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2028915A1 (en) * | 1999-08-12 | 2009-02-25 | Ibiden Co., Ltd. | Multilayer printed wiring board, solder resist composition, method for manufacturing multilayer printed wiring board, and semiconductor device |
| US7910836B2 (en) | 1999-08-12 | 2011-03-22 | Ibiden Co. Ltd. | Multilayered printed circuit board, solder resist composition, and semiconductor device |
| US7916492B1 (en) | 1999-08-12 | 2011-03-29 | Ibiden Co., Ltd. | Multilayered printed circuit board |
| US20100276292A1 (en) * | 2009-04-30 | 2010-11-04 | Moses Lake Industries Inc. | High speed copper plating bath |
| US8262894B2 (en) * | 2009-04-30 | 2012-09-11 | Moses Lake Industries, Inc. | High speed copper plating bath |
Also Published As
| Publication number | Publication date |
|---|---|
| US7514637B1 (en) | 2009-04-07 |
| DE60042976D1 (de) | 2009-10-29 |
| EP1207730A4 (en) | 2006-08-02 |
| US7993510B2 (en) | 2011-08-09 |
| US7446263B2 (en) | 2008-11-04 |
| EP2111087A2 (en) | 2009-10-21 |
| DE60045566D1 (de) | 2011-03-03 |
| US20040226745A1 (en) | 2004-11-18 |
| US7812262B2 (en) | 2010-10-12 |
| EP2111087B1 (en) | 2011-01-19 |
| EP2111087A3 (en) | 2010-03-31 |
| EP1207730A1 (en) | 2002-05-22 |
| US20080230263A1 (en) | 2008-09-25 |
| US20050211561A1 (en) | 2005-09-29 |
| EP1207730B1 (en) | 2009-09-16 |
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