WO2001047111A2 - Circuit de rereferencement couple en mode capacitif avec retroaction positive - Google Patents

Circuit de rereferencement couple en mode capacitif avec retroaction positive Download PDF

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Publication number
WO2001047111A2
WO2001047111A2 PCT/US2000/034784 US0034784W WO0147111A2 WO 2001047111 A2 WO2001047111 A2 WO 2001047111A2 US 0034784 W US0034784 W US 0034784W WO 0147111 A2 WO0147111 A2 WO 0147111A2
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Prior art keywords
circuit
input
inverting circuit
inverting
referencing
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Ceased
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English (en)
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WO2001047111A3 (fr
Inventor
Richard Davis
Jiann-Neng Chen
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Teradyne Inc
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Teradyne Inc
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Publication of WO2001047111A2 publication Critical patent/WO2001047111A2/fr
Publication of WO2001047111A3 publication Critical patent/WO2001047111A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/003—Changing the DC level
    • H03K5/007—Base line stabilisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements

Definitions

  • This invention relates generally to signal re-referencing, and more particularly to logic level re-referencing for digital signals in automatic test systems.
  • FIG. 1 illustrates a conventional technique for conveying digital signals between a first portion 1 10 and a second portion 112 of a test system.
  • the first and second circuit portions 110, 112 may be physically distant from each other, or they may operate from different power supplies or grounds.
  • Level translators 122 and 124 are connected between the first and second circuit portions 110 and 1 12.
  • Each level translator receives an input signal from one circuit portion (e.g., from driver 114 or driver 120) and provides a re- referenced output signal to the other circuit portion (e.g., to receiver 1 16 or 1 18).
  • Each level translator 122, 124 also receives power and ground from both of the circuits portions 110 and 112.
  • the purpose of a level translator is to transform an input signal having one set of logic levels into an output signal having another set of logic levels. For example, assume that a digital signal is to be conveyed from TTL logic levels to ECL logic levels. As is known, TTL logic generally uses +5v and ground for powering digital logic, and ECL logic generally uses ground and -5.2v. Logic high and low levels are approximately 4v and lv, respectively, for TTL. but are approximately ⁇ 0.8v and - 1.8v for ECL. To convey logic signals from TTL to ECL, a level translator respectively transforms high and low logic signals on the TTL side into high and low logic signals on the ECL side.
  • level translators 122, 124 By applying level translators 122, 124 to the system of Fig. 1, the different portions 110 and 112 of the test system can communicate with each other. They communicate, however, at the expense of increased component count and increased complexity.
  • level translators When conveying large numbers of signals, such as data or address busses, level translators begin to constitute a significant portion of an overall system design. Level translators take up space that could otherwise be used for performing more substantive operations. They also consume power and cost money. In addition, when level translators are used to transmit signals that have precise timing relationships to one another, it becomes difficult to maintain equal path delays among the different signals. Circuit board layout becomes particularly complicated.
  • level translators To overcome the expense and complexity of providing separate level translators, many circuit designs have incorporated level translators within integrated circuits. The level translators then reside within the same physical packages that house the devices that receive the level-translated signals. But because conventional level translators require power and ground connections from both of the circuit portions to which they connect (e.g., circuit portions 1 10 and 112), the number of power and ground leads that must be provided on the integrated circuit packages grows considerably. The proliferation of power and ground leads reduces the number of leads that are available for conveying other signals, potentially limiting the functional capabilities of the integrated circuits.
  • What is needed is a way of conveying digital logic signals with less complexity.
  • what is needed is a way of conveying digital logic between different portions of a system without having to convey as many power and ground connections as are required using current techniques.
  • Another object is to re-reference digital logic using fewer power supply or ground connections than are used with current techniques.
  • a logic level re-referencing circuit includes a non-inverting circuit having an input and an output, and a non-inverting transfer characteristic between the input and the output.
  • the logic level re-referencing circuit includes a capacitive element having a first node coupled to the input of the non-inverting circuit and a second node arranged to receive a digital input signal.
  • the digital input signal need not be generated by a device of the same logic family as the non-inverting circuit, and may originate from a source that is physically distant from the non-inverting circuit.
  • the logic level re-referencing circuit further includes a resistive element coupled between the input and the output of the non-inverting circuit. Rising and falling edges of the digital input signal couple through the capacitive element to the input of the non-inverting circuit, where they activate the non-inverting circuit to respectively assume high and low digital logic states. Output states are maintained by feedback through the resistive element.
  • a method for receiving a digital signal includes capacitively coupling rising and falling edges of the digital signal to an input of a non-inverting circuit.
  • the non-inverting circuit has at least one threshold level at the input, and also has an output.
  • the output of the non-inverting circuit respectively assumes high and low states in response to rising and falling edges at the input of a non-inverting circuit crossing the at least one threshold level.
  • the method further includes resistively coupling the output of the non-inverting circuit to the input of the non-inverting circuit, to bias the input of the non-inverting circuit relative to the output.
  • a method of constructing a logic level re-referencing circuit for receiving a digital input signal from a source circuit includes obtaining a commercially available non-inverting circuit.
  • the non- inverting circuit has an input and an output, and a non-inverting transfer characteristic between the input and the output.
  • a capacitive element is coupled in series between the input of the non-inverting circuit and the digital input signal.
  • a resistive element is coupled between the input and the output of the non-inverting circuit.
  • the resulting logic level re-referencing circuit transforms logic levels referenced to the source circuit into logic levels referenced to the non-inverting circuit.
  • the non-inverting circuit is a logic gate incorporated within an integrated circuit, for example, an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).
  • ASIC application-specific integrated circuit
  • FPGA field-programmable gate array
  • Each logic re-referencing circuit includes a non-inverting circuit having an input and an output, and a non-inverting transfer characteristic between the input and the output.
  • Each re-referencing circuit also includes a capacitive element having a first node coupled to the input of the non-inverting circuit and a second node arranged to receive a digital input signal.
  • Each re-referencing circuit further includes a resistive element coupled between the input and the output of the non-inverting circuit. Rising and falling edges of each digital input signal couple through the capacitive element to the input of the non-inverting circuit, where they activate the non-inverting circuit to respectively assume high and low digital logic states. Output states are maintained by feedback through the resistive element.
  • Fig. 1 is a block diagram of a system in which logic levels are translated between two different portions of a digital system, or between two different families of digital logic, according to conventional techniques;
  • Fig. 2a is a simplified schematic of an embodiment of a re-referencing circuit according to the invention.
  • Fig. 2b is a timing diagram of waveforms that can be observed in the re-referencing circuit of Fig. 2a;
  • Fig. 3 is a block diagram of a system in which logic levels are translated between two different portions of the system, or between two different families of digital logic, using re-referencing circuits according to the invention.
  • Fig. 2a illustrates a re-referencing circuit 200 according to the invention.
  • the re-referencing circuit 200 includes a non-inverting circuit 210 having an input 220 and an output 218.
  • the re-referencing circuit 200 also includes a capacitive element 212 coupled between an input node 216 of the re-referencing circuit 200 and the input 220 of the non-inverting circuit 210.
  • the re-referencing circuit further includes a resistive element 214 coupled between the input 220 of the non-inverting circuit 210 and the output 218 of the non-inverting circuit 210.
  • the re-referencing circuit 200 operates in response to an input signal 250 applied to the input node 216.
  • the input signal 250 has high and low voltage levels established by a source circuit (not shown) from which the input signal originates. If the source circuit is a digital circuit belonging to the HCMOS logic family, for example, a high logic level typically equals +5v and a low logic level typically equals Ov. Therefore, the input signal 250 varies between 0 and 5v. If, however, the source circuit is an analog circuit, the voltage levels of the input signal 250 are based upon the characteristics of the analog circuit and do not necessarily correspond to logic levels of any particular logic family. Fig.
  • FIG. 2b illustrates input and output signals 250 and 252 of the re-referencing circuit 200, as well as examples (254, 256) of signals that may appear at the input 220 of the non-inverting circuit 210.
  • the edge capacitively couples through the capacitive element 212 and appears at the input 220 of the non-inverting circuit 210. If the capacitively coupled rising edge at the input 220 crosses a high threshold of the non-inverting circuit 210, the non-inverting circuit 210 assumes a high output state.
  • the output signal 252 has as a voltage level commensurate with the normal high output voltage level of the logic family to which the non-inverting circuit 210 belongs. If the non-inverting circuit 210 is an analog circuit, the output level depends upon the particularities of the analog circuit.
  • the falling edge capacitively couples through the capacitive element 212 and appears at the input 220 of the non-inverting circuit 210. If the capacitively coupled falling edge crosses a low threshold of the non-inverting circuit 210, the non-inverting circuit 210 assumes a low output state. Current feeds back through the resistive element 214, tending to drive the input 220 of the non-inverting circuit to a voltage that substantially equals the voltage at the output. A stable state is established, and that state is maintained until the logic re-referencing circuit 200 subsequently responds to a rising edge on the input signal 250. The stable state is maintained, even if the input signal is disconnected.
  • the input and output signals 250 and 252 appear to have equal voltage swings.
  • the voltage swings of the input and output signals need not be the same, however. If the voltage swing of the input signal 250 is greater than the voltage swing of the output signal 252, the voltage at the input 220 of the non- inverting circuit 210 may appear like the signal 254. Positive edges of the input signal 250 cause the signal 254 to exceed the highest level of the output signal 252. Likewise, falling edges of the input signal 250 cause the signal 254 to exceed, in the negative direction, the lowest level of the output signal 252. After each transition, the signal 254 tends to return to the voltage of the output signal 252, as feedback through the resistive element 214 tends to equalize the input and output voltages of the non- inverting circuit 210.
  • the voltage at the input 220 of the non-inverting circuit 210 may appear like the signal 256. Positive edges of the input signal 250 cause the signal 256 to rise to a value lower than the highest level of the output signal 252. Falling edges of the input signal 250 cause the signal 256 fall to a value higher than the lowest level of the output signal 252. Over time, feedback tends to cause the signal 256 to return to the voltage of the output signal 252.
  • the threshold level, or levels, of the non-inverting circuit 210 significantly affect the operation of the logic re-referencing circuit 200.
  • the non- inverting circuit 210 has a single threshold for high low transitions, the capacitively coupled input signal (e.g., waveforms 254, 256) must cross that threshold to induce both high and low logic states. If the high and low thresholds are different, the non- inverting circuit 210 only goes high in response to rising edges crossing the high threshold, and only goes low in response to falling edges crossing the low threshold level.
  • DC voltage levels of the input signal 250 relative to the output signal 252 are substantially irrelevant to the operation of the re-referencing circuit 200. DC voltage levels of the input signal 250 are not applied to the non-inverting circuit 210, but rather are maintained across the capacitive element 212. Thus, the logic re- referencing circuit 200 behaves substantially the same way for input signals that vary between 0 and 5v as it does for those that vary between 10 and 15v, or between-10 and -5 v.
  • the non-inverting circuit 210 has an input and an output, and a non-inverting transfer characteristic between the input and the output.
  • the gain of the non-inverting circuit 210 should usually be at least one, to ensure that the output signal 252 can reach sufficient levels to meet input requirements of any downstream components.
  • the gain of the non-inverting circuit 210 is high, so that the particular amplitudes of the input and output signals 250, 252 need not be considered when constructing the re-referencing circuit 220.
  • the non-inverting circuit 210 can take a variety of forms. It can be implemented in either analog or digital form, as long as it is capable generating a digital output signal in response to an input signal crossing a threshold.
  • the non-inverting circuit 210 can be implemented using an analog differential amplifier.
  • the non-inverting input of the differential amplifier carries the capacitively coupled input signal (from the input 220), and the inverting input of the differential amplifier receives a reference level. Capacitively coupled edges from the input signal 250 that cross the reference level cause the differential amplifier to change its output state.
  • the non-inverting circuit 210 may constitute a single logic gate.
  • a buffer can be used, an OR gate, an AND gate, or any other gate having a non-inverting transfer characteristic between an input and an output. If a logic gate has one or more unused inputs, the unused inputs should be connected in a manner that enables non-inverting operation of the logic gate between the input and the output.
  • Inverting logic gates can also be used to constitute the non-inverting circuit 210, as long as they are combined in ways that yield an overall non-inverting transfer characteristic. Gates with multiple outputs, for example differential outputs, can also be used, provided that the output that is connected to the resistive element 214 carries an output signal 252 that is non-inverting relative to the input signal 250.
  • the capacitive element 112 is a discrete capacitor or a capacitor fabricated within an integrated circuit.
  • the capacitive element should be chosen to reduce to an acceptable level the effects of stray input capacitance at the input 220 of the non- inverting circuit 210. Typically, this means setting the capacitive element 112 to a capacitance at least five times greater than the input capacitance of the non- inverting circuit 210. For example, if the input 220 of the non-inverting circuit 210 has a stray capacitance of 3 picofarads, the capacitive element 212 should be chosen to have a capacitance of at least 15 picofarads. This is merely a rule of thumb. If very large input signals are expected, some attenuation of input edges can be tolerated, and smaller values of capacitance can be used.
  • the resistive element 114 is a discrete resistor or a resistor fabricated within an integrated circuit.
  • the resistive element 114 should be chosen to reduce to an acceptable level the effects of input bias current of the non-inverting circuit 210.
  • the resistive element 114 should also be large enough to prevent excessive attenuation of the input signal 250.
  • the resistive element 1 14 combines with the capacitive element 1 12 to form a parasitic voltage divider, which can attenuate the input signal 250. Attenuation is reduced to negligible levels by selecting a resistance much greater than the impedance of the capacitive element 1 12 at the highest relevant frequencies of the input signal.
  • the impedance of the capacitive element 112 is about 100 ohms (1 / 2* ⁇ *F*C).
  • the resistance of the resistive element 1 14 should be at least five times greater than this value, or at least 500 ohms.
  • the values of the resistive and capacitive elements 1 12 and 1 14 should also be chosen so that the time constant (R*C) formed by these elements exceeds the propagation delay of the non-inverting circuit. If an input edge trails off before the output of the non-inverting circuit 210 changes state, the circuit may momentarily glitch to a new state, but then immediately return to the old state, thus failing to track the input.
  • Commercial logic gates typically include built-in circuits to protect their inputs from damage arising from electro-static discharge (ESD). We have recognized that ESD circuits can also be used to protect the non-inverting circuit 210 from large voltage swings of the input signal 250, while maintaining normal operation of the re- referencing circuit 200.
  • ESD circuits vary, but commonly include a resistor connected in series with the input of a logic gate and a pair of clamping diodes connected between the input of the logic gate and the positive and negative supplies.
  • One diode has an anode connected to the input of the gate and a cathode coupled to the more positive supply.
  • the other diode has a cathode connected to the input of the gate and an anode connected to the more negative supply.
  • Fig. 3 illustrates a system 300 that uses the re-referencing circuit 200.
  • a first circuit portion 310 communicates with a second circuit portion 312 by sending and receiving digital signals.
  • a driver 314 within the first circuit portion 310 sends an electrical signal to a receiver 318 within the second circuit portion 312, and a driver 320 within the second circuit portion 312 sends an electrical signal to a receiver 316 within the first circuit portion 310.
  • the system 300 uses a re-referencing circuit 200 for each of the receivers 316 and 318, in place of the receivers 1 12, 1 16, which were used in Fig. 1.
  • the system 300 of Fig. 3 does not require explicit level translators. Rather, level translating functions are provided internally to the receivers 316, 318. Moreover, the system 300 of Fig. 3 does not require additional power or ground connections.
  • the re-referencing circuit 200 within an integrated circuit can be accomplished without adding power supply or ground terminals to the integrated circuit package. The terminals that would otherwise be used to convey additional power and ground signals are thus free to convey signals that allow the integrated circuit to perform more substantive functions.
  • the entire re-referencing circuit 200 including the non-inverting circuit 210, the capacitive element 212, the resistive element 214, and any protection circuitry, s incorporated within an integrated circuit.
  • the input signal 250 is then received by the re-referencing circuit 200 via a single input terminal of the integrated circuit, in the same way that signals are received that do not require re-referencing.
  • the re-referencing circuit 200 has been described for use with signals from distant portions of a system or from different logic families.
  • the re-referencing circuit 200 is not limited, however, to these applications. Rather, it can be used for receiving all digital input signals of a circuit, regardless of whether the signals need to be re-referenced.
  • the re-referencing circuit 200 can be a default digital receiver, able to accept a wide range of input signals.
  • Integrated circuits can be constructed using the re-referencing circuit 200 as a default input receiver for receiving all digital input signals.
  • a re-referencing circuit can be constructed from readily available components. By adding an off-the-shelf capacitive element 212 and an off-the-shelf resistive element 114 to a pre-existing, commercially available non-inverting circuit 210, a re-referencing circuit can be readily constructed. According to another variation, the capacitive element 1 12 can be located near the source circuit, which originates the input signal 250, rather than being located close to the non-inverting circuit 210.
  • the voltage swing of the input signal 250 of the re- referencing circuit 200 must be large enough to cross the threshold of the non- inverting circuit 210.
  • this limitation is overcome using a re-referencing circuit 400, shown in Fig. 4.
  • the re-referencing circuit 400 is similar to the re-referencing circuit 200, except that it includes a second resistive element 410 coupled between the input 220 of the non-inverting circuit 210 and DC level 412.
  • the DC level 412 is preferably set to a value that approximately equals the threshold voltage of the non-inverting circuit 210.
  • Feedback from the output of the non-inverting circuit 210 thus tends to drive the input 220 of the non- inverting circuit 210 to a level between the output voltage and the threshold voltage. With the steady-state value of the input 220 closer to threshold, input signals with smaller voltage swings can still cross threshold. Although the second resistive element 410 attenuates the feedback from the output of the non-inverting circuit 410, it does not substantially attenuate the input signal 250. Thus, the re-referencing circuit 400 can be used to translate signals from logic families having small swings to logic families having large swings.
  • the re-referencing circuit 400 can effectively translate ECL levels (lv swing) to HCMOS levels (5v swing).
  • the circuit still operates for input signals having large voltage swings.
  • the DC level 412 can be derived from the power supplies of the non-inverting circuit 210, no additional power supply connections are needed to realize the re-referencing circuit 400. The advantages of requiring only a single input terminal are therefore preserved.
  • the re-referencing circuit 200 can be used to re-reference digital signals that have greater than two discrete logic levels.
  • the non-inverting circuit 210 is provided with multiple input threshold levels and can generate multiple output levels. The output level of the non-inverting circuit 210 depends upon the level of the capacitively coupled input signal 254, 256 with respect to the input threshold voltages. Edges of the input signal 250 couple through the capacitive element 212 and cause the signal at the input 220 of the non-inverting circuit 210 to cross one or more of the threshold levels. The output of the non-inverting circuit is then caused to assume a state that corresponds to the input level. Feedback through the resistive element 214 tends to hold the input in its current state. That state is maintained even if the input signal is disconnected, until another edge of the input signal 250 occurs and crosses a threshold.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Dc Digital Transmission (AREA)
  • Logic Circuits (AREA)

Abstract

Cette invention se rapporte à un circuit et à un procédé servant à recevoir un signal d'entrée numérique référencé sur des niveaux logiques arbitraires, et à réréférencer ce signal d'entrée numérique sur des niveaux logiques locaux. Un circuit de réréférencement comprend à cet effet un circuit non inverseur ayant une entrée et une sortie, et une caractéristique de transfert de non-inversion entre l'entrée et la sortie. Un élément capacitif est connecté en série à ce circuit non inverseur, pour coupler en mode capacitif le signal d'entrée numérique à l'entrée du circuit non inverseur. Le circuit de réréférencement comprend également un élément résistif connecté entre l'entrée et la sortie du circuit non inverseur. Pendant le fonctionnement, le front montant et le front descendant du signal d'entrée numérique se couplent en mode capacitif à l'entrée du circuit non inverseur et traversent un niveau seuil, amenant le circuit non inverseur à modifier son état de sortie. La tension à la sortie du circuit non inverseur se couple en mode résistif en retour à l'entrée du circuit non inverseur, où la tension à l'entrée du circuit non inverseur tente à égaliser la tension à la sortie. Dès lors que l'entrée du circuit non inverseur ne possède pas de connexion en courant continu (CC) avec le signal d'entrée numérique, les niveaux de tension à l'entrée du circuit non inverseur restent référencés sur les tensions d'alimentation du circuit non inverseur, quels que soient les niveaux de tension du signal d'entrée numérique. Un circuit de calage peut être utilisé pour protéger le circuit non inverseur contre les tensions d'entrée ayant de fortes excursions de tension. En outre, un second élément résistif peut être connecté entre l'entrée du circuit non inverseur et un niveau CC, pour atténuer la rétroaction depuis la sortie du circuit non inverseur, permettant ainsi une utilisation avec des signaux d'entrée ayant de faibles excursions de tension.
PCT/US2000/034784 1999-12-21 2000-12-20 Circuit de rereferencement couple en mode capacitif avec retroaction positive Ceased WO2001047111A2 (fr)

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US46814699A 1999-12-21 1999-12-21
US09/468,146 1999-12-21

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003061127A1 (fr) * 2002-01-04 2003-07-24 Teradyne, Inc. Circuit de re-referencement couple en mode capacitif a correction transitoire

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4339727A (en) * 1978-03-07 1982-07-13 Nippon Electric Co., Ltd. Waveform converting circuit
US4255712A (en) * 1978-12-18 1981-03-10 Petrie Adelore F Digital waveform conditioning circuit
US4794283A (en) * 1987-05-26 1988-12-27 Motorola, Inc. Edge sensitive level translating and rereferencing CMOS circuitry
JPH01138813A (ja) * 1987-11-26 1989-05-31 Toshiba Corp Ｅｃｌ―ｃｍｏｓレベル変換回路
EP0364700B1 (fr) * 1988-10-18 1995-05-03 ANT Nachrichtentechnik GmbH Circuit de couplage à un bus
WO1996026590A1 (fr) * 1995-02-23 1996-08-29 Dolphin Interconnect Solutions A/S Circuit d'isolement d'interface pour signaux differentiels

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003061127A1 (fr) * 2002-01-04 2003-07-24 Teradyne, Inc. Circuit de re-referencement couple en mode capacitif a correction transitoire

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