WO2003040902A1 - Circuit integre a semi-conducteur, systeme et procede d'emission de signaux - Google Patents

Circuit integre a semi-conducteur, systeme et procede d'emission de signaux Download PDF

Info

Publication number
WO2003040902A1
WO2003040902A1 PCT/JP2001/009731 JP0109731W WO03040902A1 WO 2003040902 A1 WO2003040902 A1 WO 2003040902A1 JP 0109731 W JP0109731 W JP 0109731W WO 03040902 A1 WO03040902 A1 WO 03040902A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
integrated circuit
signal transmission
semiconductor integrated
transmission method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2001/009731
Other languages
English (en)
Japanese (ja)
Inventor
Takashi Sato
Peter Lee
Goichi Yokomizo
Toshio Shinmi
Shigenori Otake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Hitachi Ltd
Original Assignee
Renesas Technology Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp, Hitachi Ltd filed Critical Renesas Technology Corp
Priority to JP2003542465A priority Critical patent/JPWO2003040902A1/ja
Priority to PCT/JP2001/009731 priority patent/WO2003040902A1/fr
Priority to TW091104185A priority patent/TW589792B/zh
Publication of WO2003040902A1 publication Critical patent/WO2003040902A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0008Synchronisation information channels, e.g. clock distribution lines
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/099Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0998Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator using phase interpolation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un circuit à constante de temps ménagé au niveau de la borne d'entrée d'un second circuit, qui peut être réglé de sorte que la période (bruit T) d'un bruit devant survenir sur la ligne d'alimentation électrique d'un premier circuit puisse correspondre soit à des périodes (Te1 à Te8) de signaux d'horloge, soit à leurs multiples entiers, lorsqu'un signal de plusieurs bits devant être transmis en synchronisation avec le signal d'horloge est émis du circuit de sortie du premier circuit et capté par la borne d'entrée du second circuit.
PCT/JP2001/009731 2001-11-07 2001-11-07 Circuit integre a semi-conducteur, systeme et procede d'emission de signaux Ceased WO2003040902A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2003542465A JPWO2003040902A1 (ja) 2001-11-07 2001-11-07 半導体集積回路装置とシステム及び信号伝送方法
PCT/JP2001/009731 WO2003040902A1 (fr) 2001-11-07 2001-11-07 Circuit integre a semi-conducteur, systeme et procede d'emission de signaux
TW091104185A TW589792B (en) 2001-11-07 2002-03-06 Semiconductor integrated circuit device and system, and signal transmission method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2001/009731 WO2003040902A1 (fr) 2001-11-07 2001-11-07 Circuit integre a semi-conducteur, systeme et procede d'emission de signaux

Publications (1)

Publication Number Publication Date
WO2003040902A1 true WO2003040902A1 (fr) 2003-05-15

Family

ID=11737915

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2001/009731 Ceased WO2003040902A1 (fr) 2001-11-07 2001-11-07 Circuit integre a semi-conducteur, systeme et procede d'emission de signaux

Country Status (3)

Country Link
JP (1) JPWO2003040902A1 (fr)
TW (1) TW589792B (fr)
WO (1) WO2003040902A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE202005021861U1 (de) 2004-02-27 2010-09-23 Neuhofer Jun., Franz Vorrichtung zum Überbrücken eines Höhenunterschiedes zwischen zwei Fußbodenflächen

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8014476B2 (en) 2005-11-07 2011-09-06 Qualcomm, Incorporated Wireless device with a non-compensated crystal oscillator

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0443711A (ja) * 1990-06-08 1992-02-13 Nec Corp 入力バッファ回路
JPH10126453A (ja) * 1996-10-15 1998-05-15 Hitachi Ltd インターフェース回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0443711A (ja) * 1990-06-08 1992-02-13 Nec Corp 入力バッファ回路
JPH10126453A (ja) * 1996-10-15 1998-05-15 Hitachi Ltd インターフェース回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE202005021861U1 (de) 2004-02-27 2010-09-23 Neuhofer Jun., Franz Vorrichtung zum Überbrücken eines Höhenunterschiedes zwischen zwei Fußbodenflächen

Also Published As

Publication number Publication date
TW589792B (en) 2004-06-01
JPWO2003040902A1 (ja) 2005-06-09

Similar Documents

Publication Publication Date Title
DE60141613D1 (de) Konfigurierbarer Modulator
MY123503A (en) Parallel operation of devices using multiple communication standards
AU2003265818A1 (en) Synchronous mirror delay (smd) circuit and method including a ring oscillator for timing coarse and fine delay intervals
WO2002039684A3 (fr) Procede et circuit pour egalisation de preaccentuation dans des communications de donnes haute vitesse
AU2001288532A1 (en) A home network system and method
AU2003226123A8 (en) Single wire serial interface
MY126037A (en) Ic socket
EP2288032A3 (fr) Recupération de données d'horloge au moyen d'une commande de phase sélectionable
EP1176484A3 (fr) Méthode de communication d'un appareil électronique
WO2002097639A3 (fr) Dispositif uart a frequence de regime reglable
EP1701447A3 (fr) Interface d'entrée/sortie et circuit intégré à semi-conducteurs disposant d'une interface d'entrée/sortie
WO2003015252A3 (fr) Systeme de commande d'appareil comprenant un regulateur de courant
MX2007002436A (es) Sistema y metodo para transmision optica.
EP1014615A3 (fr) Transmission à duplex intégral
AU2002257317A1 (en) Pre-emphasis scheme
WO2008027792A3 (fr) Dispositif de communication sur une ligne d'alimentation et procédé muni d'un modem à fréquence décalée
AU2001252567A1 (en) Matched filter and receiver for mobile radio communication system
DE10318603B4 (de) Eingangsempfängerschaltung
EP1249971A3 (fr) Interface de réseau utilisant un retard programmable et un doubleur de fréquence
WO2003040902A1 (fr) Circuit integre a semi-conducteur, systeme et procede d'emission de signaux
WO2004008490A3 (fr) Egalisateur de connexion selectionnable, egalisateur auto-configure, circuit de reception possedant une fonction d'etalonnage d'egalisateur et systeme a caracteristiques de reflexion groupees
SE0004832L (sv) Digitalt bussystem
WO2007055731A3 (fr) Reduction de gigue de signal optique par egalisation electrique dans des systemes de transmission optique
WO2004032199A3 (fr) Recepteur a logique differentielle de reserve nulle a retard constant et procede associe
TW329562B (en) The clock driving circuit and semiconductor IC device

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CN JP KR SG US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2003542465

Country of ref document: JP

122 Ep: pct application non-entry in european phase