WO2003100850A1 - Substrat, tableau de connexions, substrat pour boitier a semi-conducteur, boitier a semi-conducteur et leurs procedes de production - Google Patents

Substrat, tableau de connexions, substrat pour boitier a semi-conducteur, boitier a semi-conducteur et leurs procedes de production Download PDF

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Publication number
WO2003100850A1
WO2003100850A1 PCT/JP2003/003399 JP0303399W WO03100850A1 WO 2003100850 A1 WO2003100850 A1 WO 2003100850A1 JP 0303399 W JP0303399 W JP 0303399W WO 03100850 A1 WO03100850 A1 WO 03100850A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
metal
metal layer
insulating resin
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2003/003399
Other languages
English (en)
Japanese (ja)
Inventor
Osamu Shimada
Toshimasa Nagoshi
Kazuhisa Suzuki
Mitsuo Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2002153578A external-priority patent/JP2003347477A/ja
Priority claimed from JP2002219544A external-priority patent/JP4196606B2/ja
Priority claimed from JP2002231310A external-priority patent/JP4288912B2/ja
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to AU2003220938A priority Critical patent/AU2003220938A1/en
Publication of WO2003100850A1 publication Critical patent/WO2003100850A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present invention relates to a substrate, a wiring board, and a substrate for a semiconductor package used for a semiconductor device.
  • the present invention relates to a semiconductor device, a semiconductor package, and a method for manufacturing the same.
  • the array type is suitable for increasing the number of pins because terminals can be arranged at a relatively large pitch.
  • the array type is generally a PGA (Pin Grid Array) having connection pins, but the connection with the wiring board is an insertion type and is not suitable for surface mounting. For this reason, a package called a surface mountable BGA (Ball Grid Array) has been developed.
  • CSP chip size package
  • This is a package having a connection portion with an external wiring board, that is, an external connection terminal, in the mounting region, not in the peripheral portion of the semiconductor chip.
  • a specific example is that a polyimide film with bumps is adhered to the surface of a semiconductor chip, the chip is electrically connected to the surface of the chip with gold leads, and then potted with epoxy resin and sealed (NIKKEI MATERIALS & TECHNOLOGY 94.4, No. 1 40, p 18-1 9) and a metal bump is formed on the temporary board at a position corresponding to the connection between the semiconductor chip and the external wiring board.
  • Transferred on board Smallest Flip—Chip and ike Package CSP; The
  • All of these semiconductor packages use through holes and via holes for forming external connection terminals in a wiring board (semiconductor package substrate) called an interposer on which a semiconductor chip is mounted.
  • a wiring board semiconductor package substrate
  • interposer on which a semiconductor chip is mounted.
  • through holes and via holes are provided in advance with holes or drills or the like at locations where connection terminals of a base material are to be formed, and external connection terminals are provided by filling with solder or conductive paste. With this method, there is a limit in reducing the diameter of the hole, and a smaller, higher-density, and lower-cost wiring board for a semiconductor package is desired.
  • Japanese Patent Application Laid-Open No. 2002-0443467 describes a semiconductor package in which a metal bump (metal column) formed by half-etching one side of a metal foil is embedded with resin and used for wiring for interlayer connection of a substrate. I have. According to this method, the diameter of the external connection terminal can be easily reduced, and the connection reliability is improved.
  • the MCP Multi Chip Package
  • MCP Multi Chip Package
  • a method of packaging multiple chips in a single package has been developed. Realized on a conventional board called)
  • As c method of forming such a package that has spread attempts to cane realized by one package system that has, after connecting the chip to the wiring board, and forming a wiring thereon Me embedding in resin laminate There are ways to go.
  • the resin layer is formed by pressing a resin sheet as a method of forming the resin layer, there is a problem in the ability of the resin to follow the above-mentioned uneven member. Also, when filling the chip, the pressure applied to the chip may cause the chip to crack.
  • the minimum external dimensions of an area array mounting type BGA or CSP board are determined by the number of external connection terminals, the terminal pitch, the minimum wiring rule of the board, and the wiring rules that can be formed on the wiring board on which it is mounted. In other words, this means that the wiring pitch becomes smaller as the number of terminals increases, and the minimum outer dimensions are determined by the minimum pitch of the wiring that can be formed.
  • connection pads are formed at the end of the circuit that is routed from. This routing of the circuit is one of the factors that keeps the board from shrinking.
  • the current minimum wiring pitch is generally about 50 m pitch. Therefore, if the external connection terminal pitch of BGA or CSP is set to 0.5 mm pitch, the external dimensional force of 400 terminals is about 12 mm square.
  • Figure 5 shows a cross-sectional view of a conventional semiconductor package using a semiconductor package substrate that uses connection with through-holes.
  • the semiconductor chip 105 is mounted on the insulating resin layer 106 on which the connection portion 104 with the through-hole is formed, and is sealed with the sealing material 108.
  • circuits 111 connected to the through-hole plating connecting portions 104 are provided on the upper and lower surfaces of the insulating resin layer 106.
  • the upper and lower circuits 1 1 and 1 1 are provided with NiZAu plating 109.
  • the underside of this board is soldered
  • a solder resist 112 is coated by exposing the ball pad, and a solder bump 110 is provided on the solder pole pad.
  • connection pad for the wire bonding by the gold wire 107 to the semiconductor chip 105 cannot be provided directly above the connection portion 104 having the through hole.
  • the circuit 111 is routed from the hole-plated connection portion 104, and the connection pad 102 is arranged at the tip, that is, at the circuit portion on the insulating resin.
  • the connection with the semiconductor chip 105 by wire bonding is not performed on the circuit 111 directly above the metal pillar 103, but that part is covered with a solder register 112, and the circuit 111 is formed.
  • the connection is performed on the connection pad # 02 on the insulating resin provided at the end of the first part. Disclosure of the invention
  • the present invention proposes a method for easily forming a resin layer on an uneven member used for manufacturing a semiconductor package substrate and other wiring boards.
  • a resin layer is formed on a wiring member, particularly a member having conductive protrusions
  • the resin may contract due to a difference in thermal expansion between the member and the resin. Warpage and swelling occur.
  • a method of suppressing warpage and undulation there is a method of using a low shrinkage resin in which inorganic particles are blended in a high ratio, but this method has a problem in that the adhesiveness between the resin and the member is deteriorated.
  • the present invention further provides a method for forming a resin layer having good adhesiveness and free from warpage and undulations, in addition to a method for forming a resin layer.
  • the present invention provides: 1. a substrate for a semiconductor package, a wiring board, which is manufactured by a process of forming a resin layer on a metal foil having conductive protrusions, and thereafter exposing the conductive protrusions by polishing; Semiconductor substrate, wiring board, chip and passive components manufactured by forming a resin layer on a wiring member consisting of a conductor with conductive protrusions and insulating resin, and then exposing the conductive protrusions by polishing After mounting it on the wiring board, bury it with resin, form a resin layer, and provide wiring on it, as a method of forming a resin layer on a semiconductor package with a built-in element or a wiring board.
  • the present invention relates to the following (1) to (21).
  • the wiring board is a substrate for a semiconductor package
  • the wiring member is a metal foil having a plurality of conductive protrusions on its surface (1) or
  • the drying process of drying the printed insulating resin to a semi-cured state before the cured, but completely cured, and polishing the insulating resin dried to a semi-cured state to expose the tips of the conductive protrusions The method for producing a wiring board according to any one of (1) to (4), further comprising: a polishing step of performing the polishing step; and a curing step of completely curing the insulating resin after the polishing.
  • the insulating resin (2) and the insulating resin (2) which have different components from the insulating resin (1) and are in a fluid varnish state, have different components from the insulating resin (3) in the flowing varnish state.
  • a multilayer insulating resin layer comprising at least three layers of an insulating resin (1) layer, an insulating resin (2) layer, and an insulating resin (3) layer to a thickness such that the conductive protrusions are embedded in the insulating resin.
  • (1) to (4) including a curing step of completely curing all the insulating resins in the multilayer insulating resin layer simultaneously and a polishing step of polishing the multilayer insulating resin layer to expose the tips of the conductive protrusions.
  • an insulating resin having good adhesion to the wiring member is used as the insulating resin (1), and the insulating resin (2) and the insulating resin (3) are used.
  • a resin having a different content of inorganic or organic particles or a resin having a different basic resin structure is formed by printing at an arbitrary position, shape, and thickness, and then the resin is formed.
  • the method according to (7) or (8), wherein a resin layer in which resins having different properties are mixed in an arbitrary portion in the insulating resin is formed by laminating.
  • a method for manufacturing a wiring board with a built-in element comprising: mounting an electronic component on a wiring board, embedding it with an insulating resin, forming an insulating resin layer, and providing wiring on the insulating resin layer. After mounting on a wiring board, an insulating resin in a fluid varnish state before curing is applied by printing to embed electronic components, and the printed insulating resin is cured to form an insulating resin layer. Manufacturing method.
  • the insulating resin (1) in a fluid varnish state on the electronic component mounting surface of the wiring board, and lose fluidity, but dry it to a semi-cured state before complete curing. Insulation that is different from the insulating resin (1) in composition and in a fluid varnish state
  • the resin (2) and the insulating resin (2) have different components and are in a fluid varnish state.
  • At least two types of insulating resin (3) are printed in this order. However, by drying to a semi-cured state prior to complete curing, at least three layers of the insulating resin (1), insulating resin (2), and insulating resin (3) layers can be obtained.
  • an insulating resin having good adhesion to a wiring board and an electronic component is used as the insulating resin (1), and the insulating resin (2) layer and the insulating resin (3) layer are formed.
  • a resin having a different content of inorganic or organic particles or a resin having a different basic resin structure is formed by printing at an arbitrary position, shape, and thickness, and then the resin is formed.
  • the present invention provides a method for forming a resin layer as follows: 1) thinly apply an insulating resin having good adhesiveness to a wiring member in a fluid varnish state before curing; The process of drying into a semi-cured state that has not been cured to form the first layer.2) Blending so that no warpage or undulation occurs on the resin layer of the first layer that is in a semi-cured state without fluidity. The resin was applied as it was in an uncured, varnished liquid state.
  • the present invention also provides a substrate such as a semiconductor package substrate, which can form a smaller semiconductor package without changing the minimum wiring pitch and the number of terminals of BGA and CSP, and the wiring rules of the wiring board.
  • An object of the present invention is to provide a semiconductor package substrate, a semiconductor device and a semiconductor package using the same. Unlike the conventional CSP and BGA boards, which use interlayer wiring by embedding the bumps formed by etching the metal foil and embedding the bumps with resin, they are different from the conventional boards for CPS and BGA where the through-holes are attached. Is completely buried in metal.
  • the present inventors can provide a connection pad immediately above the layer connection, and in the case of CSP or BGA, the minimum wiring is required.
  • the inventors have found that the size can be reduced by simply changing the design of the wiring pattern without changing the pitch, and based on this finding, the present invention has been completed.
  • the present invention relates to the following substrates (22) to (32), a substrate for a semiconductor package, a semiconductor device, and a semiconductor package.
  • the metal pillar is made of the first metal
  • the circuit is made of the second metal having different etching conditions from the first metal
  • the metal foil has the first metal layer and the second metal layer.
  • the insulating resin layer, the circuit, and the metal pillar selectively etch the first metal layer of the metal foil and form the first metal bump on the second metal layer as a metal pillar. Is formed on the surface of the second metal layer on which the first metal bumps are formed, so that the first metal bumps are exposed in the distal end surface and embedded in the insulating resin.
  • the substrate according to (23) which is formed by forming a circuit and then selectively etching a second metal layer to form a circuit.
  • the metal pillar is composed of the first metal layer and the second metal layer having different etching conditions from the first metal layer, and the circuit is formed of the third metal layer having different etching conditions from the second metal.
  • the metal foil has a first metal layer, a second metal layer, and a third metal layer as a second metal layer as an intermediate layer, and includes an insulating resin layer, a circuit, and a metal.
  • the pillar selectively etches the first metal layer of the metal foil to form a first metal bump on the second metal layer, and then selectively etches the second metal layer of the metal foil.
  • a metal bump composed of a first metal layer and a second metal layer that are to be metal pillars, and then, on the surface of the metal foil where the metal bump is formed,
  • the insulating resin layer is formed so that the metal bumps consisting of the layer and the second metal layer are exposed in the insulating resin with the tip end exposed. Then and is formed by forming a circuit by selectively etching a layer of a third metal (2 3) substrate according.
  • the metal pillar is made of the first metal
  • the circuit is made of a second metal layer having different etching conditions from the first metal and a third metal layer having different etching conditions from the second metal.
  • the foil has a first metal layer, a second metal layer, and a third metal layer as a second metal layer as an intermediate layer, and the insulating resin layer, the circuit, and the metal pillar are formed of a metal foil. Selectively etching the first metal layer on the second metal layer to form a first metal bump serving as a metal pillar on the second metal layer, and forming the first metal bump on the second metal layer.
  • a layer of insulating resin is formed on the surface on which the first metal bumps are exposed and the insulating layer is embedded in the insulating resin, and then a third metal layer and a second metal layer are formed.
  • the electronic device includes the substrate according to any one of (22) to (26) and an electronic component mounted on the substrate, and an external connection terminal of the electronic component is provided on the circuit immediately above the metal pillar of the substrate.
  • a semiconductor 1 (book / package) obtained by sealing the semiconductor chip mounting surface side of the semiconductor device according to (28).
  • the present invention provides a method of manufacturing a semiconductor device, such as a semiconductor package substrate, in which external connection terminals are provided on a metal sheet by etching or the like in advance, and the external connection terminals are embedded with a resin serving as a base material.
  • the purpose is to provide a method for improving the adhesion with the device.
  • adhesion between the metal and the resin is an important factor for reliability. Adhesion greatly depends on the type of resin, the type of metal to be bonded, and the state of the metal bonding surface, such as the surface shape. Regarding the surface state of the metal, when the metal is copper and the resin is an epoxy resin, the roughened surface and the roughened surface often have better adhesion.
  • the resin is polyamide-imide resin
  • the glossy surface and the roughened surface often have better adhesion between the glossy surface and the roughened surface.
  • the roughened surface which is reversed from the initial state, has better adhesion.
  • the inventors of the present invention have found that a multilayered metal foil used in the above-mentioned method has a resin as an adhesive surface with the resin. It is important to select a metal layer with good adhesion to the resin, and it is important to select a metal surface state with good adhesion to the resin as the surface to bond with the resin. The present invention has been achieved.
  • the present invention further relates to the following (33) to (58).
  • a resin layer a circuit on at least one side of the resin layer, a plurality of columnar external connection terminals protruding into the resin layer from the circuit to the opposite side of the resin layer, and a resin layer of the circuit and the external connection terminal.
  • a wiring board characterized in that the surface in contact with the resin is roughened.
  • the first metal layer of the multilayer metal foil having at least three layers of the first metal layer, the second metal layer, and the third metal layer in this order is partially covered until the second metal layer is exposed.
  • the first metal layer, the second metal layer, and the third metal layer are layers in which adjacent layers have different etching conditions from each other, and the first metal layer is partially removed by etching, thereby forming a circuit.
  • the other surface of the first layer including the first layer (1) which is a metal layer, the plurality of metal columns (2) on one side of the first layer, and a metal layer having good adhesion to the resin layer. At least one metal layer of the composite metal foil having one or more metal layers (3) formed thereon is successively formed from the first layer until a metal layer having good adhesion to the resin layer is exposed.
  • the first metal layer of the multilayer metal foil having at least three layers of the first metal layer, the second metal layer and the third metal layer in this order is partially removed until the second metal layer is exposed.
  • the first metal layer, the second metal layer, and the third metal layer are adjacent to each other and have different etching conditions, and the first metal layer and the second metal layer are partially removed.
  • a semiconductor package comprising the wiring board according to (49), a semiconductor chip mounted on the wiring board, and a sealing material for sealing a semiconductor chip mounting surface of the wiring board.
  • the external connection terminals of the metal sheet having the sheet portion and a plurality of columnar external connection terminals protruding from one surface of the sheet portion expose the leading ends and are placed in the resin layer.
  • a resin layer is formed so as to be embedded, and then the sheet portion of the metal sheet is partially removed until the resin layer is exposed, thereby forming a circuit connected to the external connection terminal on the resin layer (49). ),
  • the external connection terminals of the sheet portion have a surface strength from which the external connection terminals protrude, and the metal surface has good adhesion to the resin layer.
  • the first metal layer of the multilayer metal foil having at least three layers of the first metal layer, the second metal layer having good adhesion to the resin layer, and the third metal layer in this order is used as the second metal layer.
  • the above metal sheet is produced by partially removing the metal layer until the metal layer is exposed and forming a plurality of columnar external connection terminals on the exposed surface of the second metal layer. Production method.
  • the first metal layer, the second metal layer, and the third metal layer are layers in which adjacent layers have different etching conditions from each other, and the first metal layer is partially removed by etching, thereby forming a circuit.
  • the other surface of the first layer including the first layer (1) which is a metal layer, the plurality of metal columns (2) on one surface of the first layer, and a metal layer having good adhesion to the resin layer. At least one metal layer of the composite metal foil having one or more metal layers (3) formed thereon is successively formed from the first layer until a metal layer having good adhesion to the resin layer is exposed.
  • the first metal layer of the multilayer metal foil having at least three layers of the first metal layer, the second metal layer, and the third metal layer having good adhesion to the resin layer in this order,
  • the metal layer is partially removed until exposed to form a plurality of metal pillars on the exposed surface of the second metal layer, and then the second metal layer is removed except for the portion under the metal pillar until the third metal layer is exposed.
  • the first metal layer, the second metal layer, and the third metal layer are layers whose adjacent layers have different etching conditions from each other, and the first metal layer and the second metal layer are partially removed by etching.
  • a semiconductor chip is mounted on a surface of a circuit board having a circuit manufactured by the method according to any one of (38) to (52) or (52) to (57), and then a semiconductor chip of the circuit board A method of manufacturing a semiconductor package for sealing a mounting surface.
  • the wiring board manufactured by the method of (1) to (10) is referred to as a wiring board A
  • the semiconductor package substrate is referred to as a semiconductor package substrate A
  • the semiconductor package described in the above (13) is referred to as a semiconductor package.
  • a semiconductor package A a semiconductor device manufactured by the method of (14) to (19), a semiconductor device, a substrate of (22) to (26), a substrate C, and a semiconductor device of (27).
  • the semiconductor package substrate is a semiconductor package substrate C
  • the semiconductor devices described in (28), (29) and (30) are semiconductor devices C1, C2 and C3, respectively, and the semiconductor devices described in (31) and (32).
  • the packages are respectively semiconductor packages C1 and C2, the wiring board described in (33) to (36) is a wiring board, the semiconductor package described in (37) is a semiconductor package D, and (49) to (50)
  • the wiring board described in ()) is called a wiring board, and the semiconductor package described in (51) is called a semiconductor package E.
  • FIG. 1 is a cross-sectional view illustrating a step of forming a resin layer on a metal foil having conductive protrusions by the method of manufacturing wiring board A of the present invention.
  • FIG. 2 shows a method of manufacturing a wiring board B according to the present invention.
  • FIG. 4 is a cross-sectional view illustrating a step of forming a resin layer after embedding the semiconductor chip and a step of forming a semiconductor package substrate after embedding the semiconductor chip.
  • FIG. 3 is a cross-sectional view illustrating a step of applying the method of manufacturing a wiring board B of the present invention to a method of manufacturing a three-dimensional semiconductor package having a plurality of semiconductor chips built therein.
  • FIG. 4 is a partial cross-sectional view of one embodiment of the substrate C according to the present invention.
  • FIG. 5 is a cross-sectional view of a conventional semiconductor package using a substrate for a semiconductor package in which interlayer connection is performed by plating through holes.
  • FIG. 6 is a cross-sectional view of a semiconductor package using a conventional semiconductor package substrate.
  • FIG. 7 is a cross-sectional view showing one embodiment of a semiconductor package C1 using the substrate C of the present invention.
  • FIG. 8 is a partial plan view of a wiring pattern of a semiconductor device C1 manufactured using the semiconductor package substrate C manufactured in Example 4.
  • (A) shows a wiring pattern when the substrate substrate C for semiconductor package of the present invention is used, and
  • (b) shows a wiring pattern when a conventional substrate is used.
  • FIG. 9 is a partial plan view of a wiring pattern of a semiconductor device C1 manufactured using the semiconductor package substrate C manufactured in Example 5.
  • (A) shows the wiring pattern when the semiconductor package substrate C of the present invention is used, and
  • (b) shows the wiring pattern when the conventional substrate is used.
  • FIG. 10 is a cross-sectional view of a sheet portion and a metal sheet obtained by roughening a metal sheet having a plurality of columnar external connection terminals on the surface of the sheet portion.
  • FIG. 11 is a process chart showing one embodiment of a process for producing the metal sheet shown in FIG.
  • FIG. 12 is a process chart showing another embodiment of the process for producing the metal sheet shown in FIG.
  • FIG. 13 is a process chart showing one embodiment of a process of manufacturing a semiconductor package D by the manufacturing method of the present invention.
  • reference numerals 1 1st resin layer, 2 2nd resin layer, 3 3rd resin layer, 4 cured 1st resin layer, 5 cured 2nd resin layer, 6 cured 3rd resin layer, 7 metal foil with conductive protrusions, A Conductive protrusion, 8 wiring, 9 gold bump, 10 semiconductor chip (LSI element), BAI electrode, C circuit, 11 wiring pattern formed by additive method, 1 2 solder-resist, 13 underfill material, 14 glass epoxy base Materials, 15 Connections with through-holes, 16 Nickel-gold plated pads, 17 Squeegees, 18 Masks, 19 Die bonding pastes, 20 Conductive pastes, 101 Connection pads on circuits directly above metal pillars, 102 Connection pads provided on the circuit on the insulating resin, 103 metal pillars (etched bump connection), 104 through-hole connection, 105 semiconductor chip, 106 insulating resin layer,
  • the method for producing a wiring board A comprises the steps of: printing a wiring member having a plurality of conductive protrusions on its surface, an insulating resin in a fluid varnish state before curing by printing;
  • the method includes a printing step of applying a coating to a thickness to be embedded, a curing step of curing the printed insulating resin, and a polishing step of polishing the insulating resin to expose the tips of the conductive protrusions.
  • Examples of the wiring board A manufactured by the method of the present invention include other substrates such as a semiconductor package substrate as an interposer used in a semiconductor package and a mother board on which a semiconductor package and other electronic components are mounted. Wiring boards are mentioned.
  • the surface used in the method for manufacturing wiring board A of the present invention has a plurality of conductive protrusions.
  • Examples of the wiring member include the following.
  • Metal foil with conductive protrusions on the surface For example, a three-layer metal foil in which the first and third metal layers have different etching conditions from the second metal layer, and the first metal layer is formed into a columnar bump by etching using a dry film resist The metal foil and the above three layers of metal foil are etched using a dry film resist to form the first metal layer into a columnar bump, and then the second metal layer is removed except for the lower part of the columnar bump. There is a metal foil etched away until the metal layer 3 is exposed.
  • the first and third metal layers at this time are copper and copper alloy
  • examples of the second metal layer include nickel, nickel alloy, titanium, chromium, tin, and zinc.
  • a wiring member made of a conductor having conductive protrusions and an insulating resin For example, a wiring member having an insulating resin layer, conductive layers connected to each other on both surfaces of the insulating resin layer, and conductive protrusions on at least one surface of the insulating resin layer.
  • the resin layer is formed by exposing the end faces of the columnar bumps on the metal foil, the three-layered metal foil is heat-pressed on the resin layer forming surface, and then the first metal layer is similarly formed with the columnar bumps.
  • a conductive paste such as silver paste is printed on the surface of a general double-sided wiring board to form conductive protrusions, or a metal resist is formed by plating deposition using a plating resist or the like. Including.
  • the insulating resin used in the present invention examples include a thermosetting resin such as a polyimide resin, a polyamide imide resin, a silicone resin, a phenol resin, a bismaleimide triazine resin, an epoxy resin, an acrylic resin, and a polyolefin: dilen sulfide.
  • the organic particles that can be blended with the resin include a cured product of the resin described above, and examples of the inorganic particles include alumina particles, silicon dioxide (silica), and glass fibers.
  • the organic or inorganic particles preferably have an average particle size of 0.1 to 20 m.
  • the insulating resin in a fluid varnish state before curing is coated on the surface of the wiring member having the conductive projections with the conductive projections by the insulating resin. Only, apply by printing.
  • the insulating resin in a fluid varnish state preferably has a viscosity of 3 to 70 Pa's during printing.
  • the printing method is a screen printing method using a mesh screen mask, a metal mask, etc., and a method in which a resin is applied to a uniform thickness using a squeegee, blade, etc., directly on the wiring member with a slit or gap. And a method of transferring the resin onto the wiring member after applying the resin onto a drum or a board. A method of performing these operations under vacuum is also effective in eliminating unfilled parts.
  • the polishing step may be performed after the curing step. Further, a curing step may be performed after the polishing step.
  • the edge resin is dried to a semi-cured state before it is completely fluidized, but before it is completely cured, and then the insulating resin is dried to a semi-cured state.
  • a polishing step is performed to polish the resin to expose the tip of the conductive protrusion, and then a curing step is performed to completely cure the insulating resin. This latter method improves polishing efficiency because it is softer than a completely cured resin.
  • the amount of warpage can be controlled by changing the composition of the resin in each layer, the type of resin, the thickness, or the number of layers according to the wiring member forming the insulating resin layer.
  • the insulating resin a single resin layer may be formed by using only one type, or two or more types of insulating resins or resins having the same composition but different filling ratios such as a filler may be used. These may be used to form a multilayer insulating resin layer.
  • a layer having good adhesiveness can be obtained by selecting the resin of the first layer in accordance with the type and surface condition of the member.
  • the insulating resin (1) in a fluid varnish state is printed on the surface of the wiring member having the conductive protrusions, and the fluidity is lost, but it is dried to a semi-cured state before complete curing.
  • the insulating resin (2) and the insulating resin (2) in the fluid varnish state have different components from the insulating resin (1)
  • the insulating resin (3) in the fluid varnish state has different components from the insulating resin (2).
  • At least two types of insulating resin are printed in this order, respectively, and although fluidity is lost, by drying to a semi-cured state before complete curing, a layer of the insulating resin (1) can be obtained.
  • a multilayer insulating resin layer consisting of at least three layers of the insulating resin (2) and the insulating resin (3) is formed to a thickness at which the conductive protrusions are embedded with the insulating resin. Form only. Thereafter, a curing step is performed before or after the polishing step, and all the insulating resins in the multilayer insulating resin layer are completely cured simultaneously.
  • the process of forming the first layer 2) An uncured varnished liquid insulating resin blended from the resin layer of the first layer, which has no fluidity and is in a semi-cured state, so as not to generate warpage or undulation Applying as it is, and drying it to a semi-cured state that also loses fluidity to form the second layer.3)
  • To balance the multilayer insulating resin layer use the same or different insulating resin as the first layer.
  • a multi-layer insulating resin layer is formed by applying a fluid varnish state on the second layer, drying the semi-cured state where the fluidity is lost after application, and forming a third layer.
  • a step of simultaneously curing all the resin layers in the semi-cured state to a completely cured state is performed.
  • the force of blending the inorganic particles at a high ratio in which case, the adhesive force between the resin and the member is reduced.
  • the first layer at the bonding interface is a resin layer containing no or a small amount of inorganic particles, for example, a resin layer containing 1 to 20% by weight in the insulating resin, and the second layer has a high ratio of the inorganic particles to the first layer, for example, A resin layer that is blended at more than 20% by weight and up to 90% by weight in the insulation resin. This makes it possible to form a resin layer having low shrinkage and low thermal expansion with good adhesiveness.
  • the multilayer insulating resin layer has a three-layer structure, it is preferable to use the same insulating resin as the first layer for the third layer.
  • the present invention provides a resin containing a large amount of filler components such as inorganic and organic particles through a stencil mask provided with an optional opening, and then drying and repeating the printing and drying. It can also be used as a method for mixing organic particle components at arbitrary locations. In this case, it is desirable to use the same resin in order to improve the reliability of incoming calls between the layers.
  • polishing the insulating resin in a semi-cured state has a lower hardness than the cured state, so that the polishing efficiency can be increased.
  • the semi-cured state of the resin described herein refers to a state of the resin that has lost its fluidity and has been cured to a polished state and has not yet been completely cured.
  • the thermosetting resin is called the B-stage state, which varies depending on the resin, but generally refers to one with a curing efficiency of ⁇ 30 to 80%.
  • This cure rate can be measured by DSC (differential scanning calorimetry). If the insulating resin is a thermosetting resin, it is dried by heating, and the fluidity is reduced to room temperature (5 to 35 ° C) during polishing. State where elastic deformation or plastic deformation occurs when an external force is applied, and returns to the original state in the case of elastic deformation when the external pressure is removed, and the state in which the deformed state is maintained in the case of plastic deformation can be polished. It is.
  • a semi-cured state can be obtained by appropriately removing the solvent component.
  • removing the solvent there is a method of heating or reducing the pressure.
  • a state that can be polished means that it has no fluidity and undergoes elastic deformation or plastic deformation when an external force is applied, and returns to its original state when elastic deformation occurs when the external pressure is removed. When deformed, the state is such that the deformed state is maintained.
  • the amount of curing can be controlled by the amount of ultraviolet irradiation.
  • the upper portion of the conductive protrusion is prevented from being exposed to ultraviolet rays by masking or the like, and the amount of ultraviolet light irradiation is reduced from the amount of ultraviolet light irradiation of portions other than the conductive protrusion portion.
  • the upper portion of the conductive protrusion can be polished more concentratedly, and the polishing efficiency can be increased.
  • the photosensitive resin is of a type that can remove the exposed portion and the other portion with a chemical solution
  • changing the amount of ultraviolet radiation applied to the upper portion of the conductive protrusion and the other portion allows the resin on the upper portion of the conductive protrusion to be changed. Only the chemical solution can be removed, and the top of the conductive protrusion can be caught without polishing or with slight polishing.
  • a circuit pattern is formed by selectively etching the sheet-like portion of the metal foil on the surface.
  • a semiconductor chip may be mounted on a flat portion of the surface of the metal foil having the conductive protrusions, and may be embedded in the insulating resin together with the conductive protrusions.
  • the end face of the conductive protrusion on the substrate A for semiconductor package A semiconductor package substrate may be further laminated on the exposed surface or the circuit surface to form a semiconductor package substrate A having a multilayer structure.
  • the semiconductor package A of the present invention uses the semiconductor package substrate A manufactured by the method of the present invention. For example, a semiconductor chip is fixed to a surface having a circuit pattern of the semiconductor package substrate A with a die bonding material or the like, and a circuit pattern and a semiconductor chip are bonded by wire bonding, or a semiconductor chip is a flip chip. Bonding and connection to the circuit pattern. Next, the semiconductor package mounting surface of the semiconductor package substrate is sealed with a sealing material, whereby semiconductor package A is obtained.
  • the insulating resin in a fluid varnish state before curing is applied by printing to bury the electronic component, and the printing is performed.
  • the cured insulating resin is cured to form an insulating resin layer, and wiring is provided on the insulating resin layer.
  • the wiring board various wiring boards including the wiring board A obtained by the manufacturing method of the present invention can be used.
  • the insulating resin layer may be a single layer or a multilayer insulating resin layer.
  • Usable resins are the same as those described for the method of manufacturing wiring board A.
  • a fluid varnished insulating resin (1) is printed on the electronic component mounting surface of the wiring board, and the Hana ⁇ Although it is dried to a semi-cured state before it is completely cured, the insulating resin (2) and the insulating resin that are different in composition from the insulating resin (1) and are in a fluid varnish state
  • At least two types of insulating resin (3), which differ in composition from (2) and are in a fluidized varnish state, are printed in this order, respectively, and the fluidity is lost.
  • FIG. 4 shows a cross-sectional view of one embodiment of the substrate C of the present invention.
  • a plurality of metal pillars 103 for interlayer connection are embedded in the insulating resin layer 106 and penetrate to both surfaces of the insulating resin layer 106.
  • a circuit 111 composed of a metal layer is formed on one surface of the insulating resin layer 106 directly above each metal pillar 103, and a connection pad 101 is formed on the circuit 111 directly above the metal pillar 103. Provided on one. That is, the circuit 111 directly above the metal pillar 103 is used as a connection pad.
  • the opposite end face of the surface of the metal pillar 103 on which the circuit 111 is formed forms a circuit that becomes a pad for external connection (for example, a pad for solder bump) by a solder bump or the like.
  • the metal pillar 103 and the circuit 111 are formed by etching a metal foil, and the interlayer connection is completely filled with the metal composed of the metal pillar 103 (see FIG. 4).
  • the substrate C of the present invention usually has a plurality of interlayer connection portions made of metal pillars, but may have only one.
  • the circuit may be on only one surface of the interlayer insulating resin layer. It may be only on the top of the metal pillar, or may be a shape protruding from the surface of the metal pillar to the surface of the insulating resin layer.
  • a circuit may be provided which is routed from immediately above the interlayer connection part and has a connection pad provided at the end.
  • the metal foil used for forming the metal pillar by etching may be a single-layer metal foil composed of one type of metal layer, or a multi-layer metal foil of two or more layers having two or more types of metal layers. Is also good.
  • the circuit directly above the metal pillar may or may not be a metal layer formed on the metal pillar. Alternatively, it may be an exposed surface of a metal column.
  • the substrate C of the present invention uses, for example, a metal foil composed of a metal layer and a carrier layer made of an insulating resin film or an insulating resin plate, and etching the metal foil to form a carrier. It can be manufactured by forming a metal pillar on one layer, providing an insulating resin layer so that the end face of the metal pillar is exposed and embedded in the insulating resin, and then peeling off one carrier. When one carrier is a metal layer, the carrier may be removed by etching after embedding the metal pillars in the insulating resin.
  • the circuit and the metal pillar may be formed by etching a single-layer or multi-layer metal foil, or the circuit and the metal pillar may be formed separately. May be.
  • another metal foil may be laminated on the insulating resin layer and etched to form a circuit. .
  • the circuit and the metal pillar can be formed by etching a single metal foil as follows.
  • the substrate C of the present invention is manufactured using a first metal layer, a metal foil composed of a second metal layer having different etching conditions from the first metal layer, and an insulating resin.
  • a first metal layer of the metal foil is selectively etched away until the second metal layer is exposed, and the first metal bumps serving as metal pillars are formed on the second metal layer.
  • the first metal bumps are so formed that the tip surfaces are exposed and embedded in the insulating resin.
  • the second metal layer is then selectively etched away to form a circuit just above the metal pillar.
  • the metal having different etching conditions means a metal having a high erodibility and a metal having a low erodibility with respect to one type of etchant, or a metal having an erodibility with respect to a different etchant.
  • a carrier such as a reinforcing insulating resin film or an insulating resin plate that can be peeled off after the insulating resin layer is formed may be provided on the second metal layer.
  • the first metal layer and the first metal have different etching conditions.
  • the first metal layer and the second metal layer are formed using a second metal layer and a third metal layer having different etching conditions from the second metal on the second metal layer.
  • a circuit composed of a metal pillar made of and a third metal layer may be formed.
  • the first metal layer of the metal foil is selectively etched to form the first metal bump on the second metal layer, and then the second metal foil is formed.
  • the first metal layer is selectively etched to form a metal bump serving as a metal pillar composed of the first metal layer and the second metal layer.
  • a layer of insulating resin is formed such that the metal bumps are exposed in the insulating resin with their tip surfaces exposed, and then a third metal layer is formed.
  • the layers are selectively etched to form circuits.
  • a first metal layer, a second metal layer having different etching conditions from the first metal, and a third metal having different etching conditions from the second metal on the second metal layer are used as the metal foil.
  • a circuit composed of a first metal column and a second metal layer and a third metal layer may be formed by using the first metal layer.
  • the first metal layer of the metal foil is selectively etched to form a first metal bump serving as a metal pillar on the second metal layer, and then the second metal bump is formed.
  • An insulating resin layer is formed on the surface of the layer on which the first metal bumps are formed, so that the first metal bumps are exposed in the insulating resin while exposing the tip surfaces.
  • a circuit is formed by selectively etching the third metal layer and the second metal layer, respectively.
  • a circuit may be formed at the same time, which is routed from immediately above the metal pillar and has a connection bump at the tip.
  • a surface treatment on the surface of the metal foil on which the metal bumps are formed so as to improve adhesion to the insulating resin. Examples of the surface treatment include a chemical phosphorus-based treatment, a chemical phosphoric acid-based treatment, a chemical formic acid-based treatment, and electrolytic application of metal particles.
  • the first metal one selected from copper, copper alloy, iron-nickel alloy and the like can be used.
  • the first metal is copper or a copper alloy
  • nickel, a nickel alloy, titanium, chromium, tin, zinc, gold, or the like can be used as the second metal
  • the first metal is iron '.
  • titanium, chromium, tin, or the like can be used.
  • Select the third metal from copper, copper alloy, iron-nickel alloy, etc. Can be used.
  • the thickness of the first metal layer forming the metal pillar is preferably from 12 to 100 m, and if it exceeds 100 / im, the etching accuracy when forming the metal bump is low. There is a possibility that the formation of a fine pattern may be difficult. If the thickness is less than 12 ⁇ m, the strength of the metal pillar may be insufficient or the insulating property of the insulating resin may be reduced. More preferably, it is 18 to 70 jUm.
  • the thickness of the second metal layer is preferably 0.05 to 50 m, and if it exceeds 50 im, the etching accuracy during circuit formation is low, and it may be difficult to form a fine pattern.
  • the third metal layer may be eroded due to pits or chips generated in the second metal layer when etching the first metal layer. There is. More preferably, it is 0.1 to 35 m.
  • the thickness of the third metal layer is preferably 1 to 50 m.If the thickness is more than 50 m, the etching accuracy may be reduced at the time of forming a circuit, and it may be difficult to form a fine pattern. If the thickness is less than 1 m, the third metal layer may be eroded due to pits or chips generated in the second metal layer when the first metal is etched. More preferably, it is 5 to 12 m.
  • An insulating resin plate, an insulating film, or a metal foil can be used for one carrier layer.
  • a material selected from an epoxy resin, a polyimide resin, a silicone resin, a phenol resin and the like can be used.
  • a film selected from a polyimide resin, a polyethylene phthalate resin, a polyphenylene sulfide film, or the like can be used.
  • the metal foil one selected from copper foil, copper alloy foil, iron, nickel alloy, and the like can be used.
  • the insulating resin material used for the insulating resin layer is a thermosetting epoxy resin, a polyimide resin, Silicone resin, polyamide imide resin, polyphenylene sulfide resin, photosensitive polyimide resin, acrylic epoxy resin, thermoplastic elastomer such as ethylene, propylene, styrene, butadiene, liquid crystal polymer, etc.
  • thickness of insulating resin layer Is usually the same as the height of the metal pillar formed by etching the first metal layer.
  • the shape of the metal column is not particularly limited as long as it is a solid metal column. It is a cylinder with a width of 50 im and a width of the short side of 20 im or more.
  • the substrate C of the present invention may have only one insulating resin layer, or may be a multilayer wiring board having a plurality of conductive circuit layers laminated below the insulating resin layer via an insulating layer. You may.
  • the substrate C of the present invention can be used in the manufacture of various semiconductor devices, for example, as an interposer used for a semiconductor package, or as a wiring board such as a mother board on which electronic components of the semiconductor package are mounted. it can.
  • Semiconductor device C1 or C2 can be obtained.
  • the semiconductor device C1 is manufactured by wire bonding, for example, a semiconductor chip is fixed on a substrate C with a die bonding material or the like and then mounted on a circuit immediately above the metal pillar of the substrate C.
  • the connection pad thus formed and the connection pad for the semiconductor chip are bonded with a conductor wire such as a gold wire, an aluminum wire, or a copper wire.
  • the gold, solder, lead, copper, tin, silver bumps formed on the connection pads of the semiconductor chip, and their alloys, metals and resins are combined.
  • Metal bumps such as mixed conductive paste, anisotropic conductive film, and bumps made of metal coated on inorganic or organic balls, are connected to the connection pads provided on the circuit directly above the metal pillars of substrate C. Connect directly.
  • the semiconductor packages C1 and C2 of the present invention are obtained by sealing the semiconductor chip mounting surfaces of the semiconductor devices C1 and C2 with a sealing material.
  • the sealing can be performed by molding using an insulating resin, transfer molding, potting, casting, resin sealing by screen printing, or the like.
  • Epoxy resin, silicone resin, phenol, etc. are used as insulating resin used for resin sealing.
  • Resin, epoxy modified resin: L-nor resin or the like can be used.
  • FIG. 7 shows a cross-sectional view of an example of the semiconductor package C1 of the present invention.
  • the metal pillar 103 is embedded in the insulating resin layer 106 of the substrate A and penetrates to both surfaces of the insulating resin layer 106.
  • a circuit 111 made of a metal layer is formed on one surface of the insulating resin layer 106 immediately above the metal pillar 103.
  • NiZAu plating 109 is applied to the surface of the metal pillar 103 exposed on the lower surface side of the insulating resin layer 106 and the surface of the circuit 111.
  • the connection pads (not shown) of the semiconductor chip 105 mounted on the substrate C are connected to the connection pads 101 provided on the circuit immediately above the metal pillars 103 and the power wires 107 by wire bonding. ing.
  • the surface of the substrate C on which the semiconductor chip 105 is mounted is sealed with a sealing material 108.
  • connection pad 101 is provided in the circuit immediately above the metal pillar 103, it is not necessary to provide a connection pad between the wiring and the chip that is routed around the interlayer connection portion.
  • the size of the package can be reduced.
  • the pitch of the other wiring can be increased by the area of the unnecessary wiring for wiring without reducing the size.
  • the resin surface area on the substrate is large, and that the adhesion between the sealing material, the underfill material, and the solder resist is improved thereafter.
  • Another advantage is that when a wire bonding method or a flip-chip connection method using ultrasonic waves is used as the connection method, the circuit immediately above the metal pillar formed by etching is filled with metal under the circuit. Therefore, the lower part of the circuit is harder than the resin part and the ultrasonic wave is easily transmitted. As a result, good bonding properties have been obtained.
  • the number of terminals bonded to the connection pads on the circuit directly above the metal pillars reduces the overall area, and allows room for wiring routing during design.
  • the method of implementing the present invention is very simple, and a pad may be provided on a circuit immediately above a bump when designing a wiring pattern.
  • the present invention also provides a semiconductor device C3 using the substrate C of the present invention as a wiring board such as a mother board.
  • the semiconductor device C3 is mounted on the substrate C and the substrate C.
  • An external connection terminal of the electronic component is connected to a connection pad provided on the circuit immediately above the metal pillar of the substrate C and on the connection pad.
  • Electronic components include semiconductor packages and semiconductor chips. The same advantages as described above can be obtained when connecting to such electronic components as a semiconductor package and a semiconductor chip. Also, in the semiconductor device C3, the electronic component mounting surface side may be sealed.
  • the wiring board D of the present invention has a resin layer, a circuit on at least one side of the resin layer, and a plurality of columnar external connection terminals projecting into the resin layer from the circuit to the opposite side of the resin layer, The surface of the resin layer of the circuit and the external connection terminal that is in contact with the resin is roughened to improve the adhesion to the resin.
  • the circuit preferably has a metal layer having good adhesion to the resin layer or a metal layer which is easily roughened as a layer in contact with the resin layer.
  • the wiring board D of the present invention can be manufactured, for example, using a metal sheet having a sheet portion and a plurality of columnar external connection terminals protruding from one surface of the sheet portion according to the method of the present invention.
  • the surface of the metal sheet having the external connection terminals X is roughened. Due to this roughening, a roughened surface 204 is formed on the surface of the sheet portion W of the metal sheet from which the external connection terminals X protrude and on the surface of the external connection terminals X.
  • the wiring board D of the present invention can be manufactured.
  • Roughening methods include chemical roughening (etching of chemical phosphorous treatment, chemical phosphoric acid treatment, chemical formic acid treatment, etc.), mechanical roughening (blasting, etc.), plasma treatment, metal particles May be applied.
  • the two metals be the same because it is easy to select a resin that provides good adhesion between the metal surface and the resin of the resin layer.
  • a metal sheet having a sheet portion and a plurality of columnar external connection terminals protruding from one side of the sheet portion used in the method of manufacturing the wiring board D includes, for example, a first metal layer, a second metal layer, and a third metal layer. It can be manufactured using a multilayer metal foil having at least three metal layers in this order. That is, the first metal layer of the multilayer metal foil is partially removed until the second metal layer is exposed, thereby forming a plurality of columnar external connection terminals on the exposed surface of the second metal layer. In this way, a metal sheet having a shape in which a plurality of columnar external connection terminals protrude from one side is produced.
  • the second metal layer is preferably a metal layer having good adhesion to the resin layer or a metal layer which is easily roughened.
  • the metal sheet includes a first layer (1), which is a metal layer, a plurality of metal pillars (2) on one surface of the first layer, and a metal layer having good adhesion to the resin layer or an easily roughened metal layer. It can also be manufactured using a composite metal foil including a metal layer and having one or more metal layers (3) formed on the other surface of the first layer. For example, at least one metal layer of the composite metal foil may be successively removed from the first layer until a metal layer having good adhesion to the resin layer or a metal layer easily roughened is exposed. A metal sheet is prepared by removing and removing.
  • a multilayer metal foil having three layers of a first metal layer 201, a second metal layer 202, and a third metal layer 203 in this order is prepared (FIG. 11A).
  • the first metal layer 201 of the multilayer metal foil is partially removed until the second metal layer 202 is exposed, and a plurality of metal columns Y are formed on the exposed surface of the second metal layer 202, and the above-described composite metal Obtain foil (Fig. 11 (b)).
  • the second metal layer 202 is partially removed except for the portion under the metal column Y until the third metal layer 203 is exposed, so that the sheet portion (the third metal layer 203) and the plurality of columnar external connection terminals ⁇ (first A metal sheet (formed of the metal of the metal layer 201 and the metal of the second metal layer 202) is produced (FIG. 11C).
  • the third metal layer 203 As a metal layer having good adhesion to the resin of the resin layer or a layer easily roughened, the metal layer having good adhesion to the resin layer or the metal layer easily roughened is exposed. Can be.
  • a roughened surface 204 is formed.
  • the roughening method may be chemical roughening (such as etching), mechanical roughening (such as blast calorie), plasma treatment, or electrolytic application of metal particles.
  • the first metal layer 201 of the multilayer metal foil is partially removed until the second metal layer 202 is exposed, and a plurality of metal pillars are formed on the exposed surface of the second metal layer 202.
  • the exposed surface of the third metal layer 203 and the surface of the metal pillar are roughened at the same time when the second metal layer 202 is removed as described above.
  • Good. As a method of simultaneously performing removal and roughening, chemical roughening (etching or the like), mechanical roughening (blasting or the like), or plasma treatment may be used. This method is suitable when the second metal layer 202 is relatively thin, and can reduce the number of steps.
  • the first metal layer, the second metal layer, and the third metal layer may be formed by using a multilayer metal foil in which adjacent layers have different etching conditions from each other.
  • the second metal layer can be partially removed by etching, and the circuit can be formed by partially removing the third metal layer by etching.
  • the roughening amount is preferably about 0.3 m to 5 m, although it depends on the type of the resin in the resin layer.
  • the semiconductor package D of the present invention uses the wiring board D of the present invention as a substrate for a semiconductor package, and includes the wiring board D of the present invention, the semiconductor chip mounted on the wiring board D, and the wiring board D.
  • the semiconductor package D of the present invention can be manufactured, for example, according to the above-described method according to the manufacturing method of the present invention.
  • the semiconductor chip is mounted on the surface of the wiring board D having the circuit manufactured by the method described above, and then the semiconductor chip mounting surface of the wiring board D is sealed.
  • FIG. 13 shows one embodiment of a method for manufacturing a semiconductor package D of the present invention.
  • a metal sheet having a sheet portion W and a plurality of columnar external connection terminals X protruding from one side of the sheet portion W is prepared, and the surface of the metal sheet having the external connection terminals X is roughened (see FIG. 13 (a )).
  • the external connection terminal X is embedded by applying a resin 205 on the roughened surface of the metal rack whose surface has been roughened (FIG. 13 (b)).
  • the resin 205 applied to the metal sheet is polished until the end of the external connection terminal X is exposed to form a resin layer Z (FIG. 13 (c)). Partially removing the sheet portion W on the resin layer Z until the resin layer Z is exposed.
  • the circuit 206 connected to the external connection terminal X is formed on the resin layer Z, and (Fig. 13 (d)) on the surface of the circuit 206 and the exposed end faces of the external connection terminals X, if necessary, nickel-gold plating 207, nickel soldering, copper plating, Apply silver plating, etc.
  • Fig. 13 (e) On the surface of the wiring board that has the D circuit 206, attach the die bonding film 208 and attach the semiconductor chip 209 (Fig. 13 (f))
  • the connection pads of the circuit 206 and the connection pads of the semiconductor chip 209 are wire-bonded to each other with a conductor wire such as a gold wire 210, an aluminum wire, or a copper wire.
  • the semiconductor chip mounting surface of wiring board D is . Sealed by sealing material 21 1 by bonding ball 212 solder on the exposed surface of the external connection terminal X, to obtain a semiconductor package D (FIG. 1 3 (h);).
  • connection between the semiconductor chip and the circuit is made by flip-chip bonding
  • gold, solder, lead, copper, tin, silver bumps formed on the connection pads of the semiconductor chip and their alloys, metal and resin are used.
  • Bumps such as mixed conductive paste, anisotropic conductive film, and bumps made of inorganic or organic balls coated with metal, are directly connected to the connection pads provided on the circuit.
  • the present invention also has a resin layer, a circuit on at least one side of the resin layer, and a plurality of columnar external connection terminals protruding into the resin layer from the circuit to the opposite side of the resin layer.
  • a wiring board E having a metal layer having good adhesion to a resin layer as a layer in contact with the resin layer.
  • This wiring board E is a circuit in which a metal layer having good adhesion to the resin layer is provided on the circuit without performing a roughening treatment on a surface of the circuit in contact with the resin layer.
  • the wiring board E is provided on a surface having external connection terminals of a metal sheet having a sheet portion and a plurality of columnar external connection terminals protruding from one surface of the sheet portion.
  • the connection terminal is connected to the external connection terminal by forming the resin layer so that the tip is exposed and embedded in the resin layer, and then partially removing the sheet portion of the metal sheet until the resin layer is exposed. It can be manufactured by forming a circuit on a resin layer.
  • the metal sheet used is such that the surface of the sheet portion from which the external connection terminals protrude is a metal surface having good adhesion to the resin layer.
  • the metal sheet used in this manufacturing method is, for example, manufactured using a multilayer metal foil having at least three layers of a first metal layer, a second metal layer and a third metal layer having good adhesion to a resin layer in this order.
  • the above metal sheet is prepared.
  • partial removal of the first metal layer is performed by etching.
  • the circuit can be formed by partially removing the third metal layer and the second metal layer by etching in this order.
  • the metal sheet includes a first layer (1) as a metal layer, a plurality of metal columns (2) on one surface of the first layer, and a metal layer having good adhesion to a resin layer. It can also be manufactured using a composite metal foil having one or more metal layers (3) formed on the other surface of the layer. That is, by removing at least one metal layer of the composite metal foil from the first layer until a metal layer having good adhesion to the resin layer is exposed, except for the portion under the metal pillar, Can be produced.
  • the multilayer metal foil when the composite metal foil is a multilayer metal foil having at least three layers of the first metal layer, the second metal layer, and the third metal layer having good adhesion to the resin layer in this order, the multilayer metal foil
  • the first metal layer is partially removed until the second metal layer is exposed, and the exposed portion of the second metal layer is removed.
  • the metal sheet can be prepared by forming a plurality of metal columns and then partially removing the second metal layer except for the portion under the metal columns until the third metal layer is exposed.
  • the first metal layer, the second metal layer, and the third metal layer are adjacent layers having different etching conditions from each other, the first metal layer and the second metal layer are partially removed by etching,
  • the circuit can be formed by partially removing the third metal layer by etching.
  • the wiring board E As a substrate for a semiconductor package, the wiring board E, a semiconductor chip mounted on the wiring board E, and a sealing material that seals the semiconductor chip mounting surface of the wiring board E are provided.
  • the semiconductor package E of the invention is obtained.
  • the semiconductor package E of the present invention can be manufactured by the same method as the above-described method of manufacturing the semiconductor package D except that the wiring board of the present invention which is not subjected to a roughening treatment is used.
  • the first metal layer for example, a material selected from copper, a copper alloy, an iron-nickel alloy, or the like can be used.
  • the second metal layer for example, when the first metal layer is copper or a copper alloy, nickel, a nickel alloy, titanium, chromium, tin, zinc, gold, or the like can be used. In the case of an iron-nickel alloy, titanium, chromium, tin or the like can be used.
  • the third metal layer is, for example, when the second metal layer is nickel, a nickel alloy, titanium, chrome, tin, zinc, gold, or the like.
  • the metal layer having different etching conditions means a metal layer having a high erosion property and a metal layer having a low erosion property with respect to one type of etching solution, or a metal having an erosion property with respect to different etching solutions.
  • the metal layer that can be easily roughened examples include copper and copper alloys that are generally used for wiring boards. However, even when the same copper metal is used for chemical roughening, electrolytic copper is used due to differences in grain boundaries. Is easier to roughen than rolled copper.
  • the thickness of the first metal layer forming the metal pillar or the column-shaped external connection terminal is 12 to 1 Preferably, it is 00 m. If it exceeds 100 m, the etching accuracy when forming a metal pillar or an external connection terminal is low.There is a possibility that it is difficult to form a fine pattern, and it is less than 12 m.
  • the strength of the metal pillar or the external connection terminal may be insufficient, or the insulating property of the resin layer may be reduced. More preferably, it is 18 to 0 m. If the thickness of the second metal layer is more than 50 m, which is preferable to be 0.05 to 50 im, the etching accuracy at the time of circuit formation is low, and it may be difficult to form a fine pattern. If it is less than 0.05 m, the third metal layer may be eroded due to pits or chips generated in the second metal layer when etching the first metal layer. More preferably, it is 0.1 to 35 jU m.
  • the thickness of the third metal layer is preferably 1 to 50 im, and if it exceeds 50 irn, the etching accuracy may be reduced at the time of forming a circuit, and it may be difficult to form a fine pattern. If the thickness is less than jUm, the third metal layer may be eroded due to pits or chips generated in the second metal layer when etching the first metal layer. More preferably, it is 5 to 12 im.
  • an insulating resin material is used, for example, thermosetting epoxy resin, polyimide resin, silicone resin, polyamideimide resin, polyphenylene sulfide resin, photosensitive polyimide resin Acrylepoxy resin, thermoplastic elastomers such as ethylene propylene, styrene and butadiene, liquid crystal polymers, and the like.
  • the thickness of the resin layer is usually the same as the height of the first metal layer or the external connection terminals formed by etching the first metal layer and the second metal layer.
  • the shape of the external connection terminal is not particularly limited as long as it is a solid columnar shape, and is usually a cylinder having a radius of 10 to 750 m, and the width of the short side is 20 m2. It is a rectangle of m or more.
  • the wiring boards D and E of the present invention may have only one resin layer, It may be a multi-layer wiring board having a plurality of conductor circuit layers further laminated under a resin layer via an insulating layer.
  • the wiring boards D and E of the present invention can be variously used, for example, as a substrate for a semiconductor package as an interposer used for a semiconductor package, or as a wiring board such as a mother board on which electronic components of the semiconductor package are mounted. It can be used for manufacturing semiconductor devices.
  • the semiconductor package can be sealed by molding using an insulating resin, transfer molding, potting, casting, resin sealing such as screen printing, or the like.
  • an insulating resin used for resin sealing, and for example, epoxy resin, silicone resin, phenol resin, epoxy-modified phenol resin, and the like can be used.
  • Example 1 Substrate A for semiconductor package
  • FIG. 1 is a diagram showing a cross section in each step of forming a multilayer resin layer on a metal foil having conductive protrusions.
  • FIG. 1A shows a step of forming a metal foil 7 having conductive protrusions A and a first resin layer 1 having good adhesiveness.
  • the metal foil 7 having the conductive protrusions A was produced as follows.
  • a three-layer metal foil (manufactured by Nippon Electrolysis Co., Ltd.) consisting of a copper layer with a thickness of 70 m, a nickel layer with a thickness of 0.2 jUm, and a copper layer with a thickness of 10 m was used as a photo-dry film H-K350 (Hitachi)
  • a pattern is formed using a chemical process (manufactured by Kasei Kogyo Co., Ltd.), and a process liquid manufactured by Meltex Co., Ltd.
  • the metal column was made a 0250 im column.
  • an etching solution composed of an aqueous solution of nitric acid and hydrogen peroxide a columnar conductive protrusion of 0250 im composed of copper and nickel is formed. Origin A was formed.
  • the exposed surface of the copper layer of 10 m was subjected to a chemical phosphorus treatment in order to improve the adhesion to the resin.
  • the first resin layer 1 a silicone-modified polyamide-imide resin, Ranar KS 6600 (manufactured by Hitachi Chemical Co., Ltd.) was used.
  • the above resin having a viscosity of 40 Pa's in a fluid varnish state was printed by a printing machine VE-500 (manufactured by Toray Engineering Co., Ltd.).
  • Reference numeral 18 denotes a mask
  • reference numeral 17 denotes a squeegee.
  • the first resin layer 1 was formed by drying at 80 ° C. for 30 minutes to be in a semi-cured state in which fluidity was lost.
  • the thickness of the first resin layer 1 after drying was 20 im.
  • a resin containing 75% of inorganic particles (silicon dioxide) in KS6600 was printed on the first resin layer 1 in a fluid varnish state.
  • the second resin layer 2 in a semi-cured state which was dried at 80 ° C. for 30 minutes and lost fluidity, was formed (FIG. 1 (b)).
  • the thickness of the second resin layer 2 after drying was 30 j ⁇ m.
  • KS 6600 in a fluid varnish state was printed on the second resin layer 2. After the application, it was dried at 80 ° C. for 30 minutes, and was semi-cured to a semi-cured state in which the fluidity was lost, thereby forming a third resin layer 3. Thickness 25 m in a c-metallic foil 7 first resin layer 1 of the third resin layer 3 after drying, the semi-hard state of the second resin layer 2 and 3 layers of the third resin layer 3 resin After the layer is formed, as shown in Fig. 1 (d), the end surface of the embedded conductive protrusion A is exposed on the surface of the insulating resin layer. did.
  • the polishing time was such that the surface of the insulating resin layer on the 250 mm x 250 mm metal foil could be polished with a # 400 abrasive paper in 30 minutes.
  • the same polishing paper was used for 60 minutes.
  • FIG. 2 shows a cross-sectional view of the process of this embodiment. Hereinafter, the process will be described.
  • the metal foil 7 having the conductive protrusions A in FIG. 2 (a) was produced as follows.
  • a three-layer metal foil (manufactured by Nippon Electrolysis Co., Ltd.) consisting of a copper layer having a thickness of 100 im, a nickel layer having a thickness of 0.2 m, and a copper layer having a thickness of 5 m was used as a photo-dry film H—K350 (Hitachi Chemical Industries, Ltd.) Ltd.) to form a pattern using a Meltex Co.
  • er process liquid (ammonia copper complex 20-30 wt 0 / o, chloride Anmoniumu 1 0-20 0/0, and ammonia 1 to 1 0 wt% ) was selectively etched with an alkaline etchant containing (containing) a metal pillar made of copper on the exposed surface of the nickel layer.
  • the metal columns were made to be 025 O ⁇ m cylinders.
  • portions other than the portions below the metal pillars of the nickel layer were selectively removed with an etching solution composed of an aqueous solution of nitric acid and hydrogen peroxide to form cylindrical conductive projections A of 0250 im made of copper and nickel.
  • the exposed surface of the copper layer of 5 jUm was subjected to a chemical phosphorous treatment to improve the adhesion to the resin.
  • AI electrode B is in contact with the copper foil surface where conductive protrusion A is not formed on semiconductor chip 10 of size 6.5 x 6.5 mm and thickness of 0.050 mm on prepared metal foil 7 with conductive protrusions. In this way, it was fixed using a die bonding paste EN-X50N (manufactured by Hitachi Chemical Co., Ltd.) 19. At this time, the die bonding paste was prevented from adhering to the pad portion of the semiconductor chip.
  • EN-X50N manufactured by Hitachi Chemical Co., Ltd.
  • FIG. 2 (b) shows a semi-cured state using a KS 6600 made of a silicone-modified polyamide-imide resin (manufactured by Hitachi Chemical Co., Ltd.) and a resin made of this resin and inorganic particles, as in Example 1.
  • a KS 6600 made of a silicone-modified polyamide-imide resin (manufactured by Hitachi Chemical Co., Ltd.) and a resin made of this resin and inorganic particles, as in Example 1.
  • FIG. 2 (c) is a cross-sectional view showing a circuit C formed by selectively etching a copper layer having a thickness of 5 im. At that time, the copper foil of the mounting portion of the semiconductor chip 10 was etched so that only the pad portion of the chip was exposed.
  • FIG. 2 (d) shows the connection between the exposed AI electrode B of the semiconductor chip and the formed circuit C, so that a conductive paste dodent (made by Nihon Handa Co., Ltd.) is applied to the AI electrode B.
  • FIG. 3 is a cross-sectional view in which a blank is printed and then cured at 180 ° C. for 30 minutes.
  • FIG. 2 (e) prepares a member in which three semi-cured insulating resin layers are formed on a metal foil having conductive protrusions in the same process as in Example 1.
  • FIG. 2 (f) is a cross-sectional view in which the member prepared in FIG. 2 (e) is thermocompression-bonded to the member shown in FIG. 2 (d) under vacuum using a vacuum press device.
  • the resin of the member in FIG. 2 (c) in the semi-cured state is softened once by heating, and the resin is pushed between the circuits by applying pressure, and adheres to the member in FIG. 2 (d).
  • the connection between the layers is made between a conductive protrusion A made of embedded copper and a circuit C formed of a 5 jum copper layer.
  • connection between the layers is in the state where the conductive protrusion A and the circuit C are in contact with each other due to the adhesive force of the surrounding resin, but in order to further improve the connection reliability, the conductive protrusion is required.
  • Attach the solder to the exposed part of A and the circuit C by soldering to increase the adhesion or apply a soldering to the same part.
  • a method is considered in which a conductive adhesive is applied to the exposed portion of the conductive protrusion A or the connection portion of the circuit C or both portions before pressing, and the adhesive is cured simultaneously at the time of pressing.
  • FIG. 2 (g) shows that the insulating resin layer composed of the first resin layer 1, the second resin layer 2, and the third resin layer 3 of the thermocompression-bonded member is completely cured, and the cured resin layer 4 and the cured resin layer 5 are cured.
  • FIG. 4 is a cross-sectional view after a layer made of a cured resin layer 6 is formed.
  • FIG. 3 shows a cross-sectional view of a step in which this embodiment is performed.
  • a double-sided wiring board using a glass epoxy base material 14 as an insulating layer was prepared (FIG. 3 (a)), and an LSI element 10 having gold bumps 9 at terminals on wirings 8 of the double-sided wiring board (thickness 10) The gold bump 9 and the wiring 8 were interconnected by thermocompression bonding (Fig. 3 (b)).
  • the assembly thus produced was treated with a KS6600 (manufactured by Hitachi Chemical Co., Ltd.) made of a silicone-modified polyamideimide resin and a resin made of this resin and an inorganic filler.
  • KS6600 manufactured by Hitachi Chemical Co., Ltd.
  • each resin layer after drying on the solder resist 12 was 40 m for the first resin layer, 60 im for the second resin layer, and 40 m for the second resin layer 3 for 40 m. . After semi-curing, polishing was performed, and then the resin of the insulating resin layer was completely cured.
  • a 0.5 mm pitch semiconductor package substrate C having a cross section shown in FIG. 4 was produced.
  • a 70 m-thick copper layer consisting of a 70 m-thick copper layer, a 0.22 m-thick nickel layer, and a 10 jUm-thick copper layer (made by Nippon Electrolysis Co., Ltd.)
  • a pattern is formed using H-K350 (manufactured by Hitachi Chemical Co., Ltd.), and an A process solution manufactured by Meltex Co., Ltd.
  • Copper was selectively etched with an alkaline re-etching solution composed of a stock solution to form 200 0250 mm copper bumps.
  • the nickel layer is selectively etched leaving just above the copper bumps.
  • the cutting was removed to form a metal pillar 103 composed of a copper layer and a nickel layer.
  • an etching solution composed of a stock solution of Melstrip N-950 (containing 8% by weight of sulfuric acid, 5% by weight of nitric acid and 3.5% by weight of hydrogen peroxide) was used.
  • a chemical phosphorus treatment (a treatment solution manufactured by Ebara Densan Co., Ltd., an NBD II treatment solution (sulfuric acid 7.5% by weight, phosphoric acid 3.8% by weight and hydrogen peroxide 4.0% by weight) were processed by an NBD II processing system) at a line speed of 1.75 mZm in, spray pressure of 9.8 X 10
  • the application was performed under the conditions of 4 Pa (1. OkgfZcm 2 ).
  • an insulating resin KS 6600 (manufactured by Hitachi Chemical Co., Ltd.), which is a liquid silicone-modified polyamideimide resin, is printed with a printing machine VE-500 (manufactured by Toray Engineering Co., Ltd.). After printing and filling the metal pillars 103,80. Three steps of curing were performed for 30 minutes at C, 180 ° C. for 30 minutes, and 220 ° C. for 20 minutes, and polished until the end face of the metal pillar 103 embedded with a commercially available abrasive paper appeared to form an insulating resin layer 106.
  • a copper layer having a thickness of 10 m of metal foil was coated with a process liquid manufactured by Meltex Co., Ltd. (containing 20 to 30% by weight of an ammonia copper complex salt, 10 to 20% by weight of ammonium chloride and 1 to 10% by weight of ammonia).
  • the copper column 1103 was formed on the metal column 103 by selective etching with an alkaline etching solution composed of a stock solution.
  • electrolytic nickel Z gold plating NiZAu plating 109 (manufactured by Daiwa Denki Kogyo Co., Ltd.) is formed on the circuit surface to form a 0.5mm pitch semiconductor package with a cross-sectional structure as shown in Fig. 4.
  • a substrate was prepared.
  • FIG. 8A is a partial plan view showing a wiring pattern of a semiconductor device manufactured using the substrate shown in FIG.
  • a semiconductor chip 105 having a size of 8.5 mm X 8.5 mm and a thickness of 0.3 mm is mounted on this substrate, and a connection node 101 provided on a circuit 111 directly above a metal pillar 103 is provided with:
  • a connection pad (not shown) of the semiconductor chip 105 is connected with a gold wire 107.
  • FIG. 8 Shown in FIG. 8 (b) a partial plan view of a wiring pattern of a semiconductor device manufactured using the (connection pads of the semiconductor chip 105 mounted on a substrate (not shown), all the metal columns 103 Wire bonding is performed to the connection pad ⁇ 02 provided at the tip of the insulating resin of the circuit 113 routed from directly above.As a result, as shown in FIG.
  • connection pad of all 200 pieces at 15 mm is directly above the metal pillar 103, it is 13 x 13 mm, which means that the board is 25% smaller.
  • the portion bonded directly above the metal pillar 103 which was formed by etching with HW2100 (manufactured by Kyushu Matsushita Electric Co., Ltd.), had a wire bonding failure rate of 0.009%. Less than 0.03% of connection pads was Tsu ⁇ Example 5 (semiconductor package substrate C, the semiconductor device C1)
  • FIG. 9A is a partial plan view of a wiring pattern of a semiconductor device manufactured by mounting a semiconductor chip on this substrate and performing wire-to-bonding. For comparison, a board was prepared in which all connection pads were formed on a circuit on insulating resin by circuit pattern routing.
  • Example 6 (b) shows a partial plan view of a wiring pattern of a semiconductor device manufactured by mounting a semiconductor chip on this comparative substrate and performing wire-to-wire bonding.
  • the size of the semiconductor package substrate which is 120 wires directly above the metal pillars for interlayer connection and wire-bonded, is 14 x 14 mm on the comparative substrate, whereas the size of the substrate of this example is 12 x 12 mm. And could be.
  • Example 6 (wiring board D, semiconductor package D)
  • a 70 jUm thick copper layer, a nickel layer with a thickness of 0, and a copper layer with a thickness of 10 m, a 70 j «m copper layer of a three-layer metal foil was applied to Pattern formation using K350 (manufactured by Hitachi Chemical Co., Ltd.) and alkali etching
  • the copper layer is selectively etched by a liquid process (Meltex Co., Ltd., containing 20 to 30% by weight of ammonia copper complex salt, 10 to 20% by weight of ammonium chloride and 1 to 10% by weight of ammonia)).
  • a plurality of 0250 m copper columns were formed on the nickel layer.
  • the nickel layer was selectively etched and removed, leaving a portion below the copper metal pillar, to form a columnar external connection terminal composed of the copper layer and the nickel layer.
  • the exposed surface of the copper layer with a thickness of 10 m and the surface of the external connection terminal were treated with NB DII treatment solution (EBARA (Sulfuric acid 7.5% by weight, phosphoric acid 3.8% by weight and hydrogen peroxide 4.0% by weight), a line speed of 1.75mZ, a spray pressure of 9,8X1 0 4 Li roughened by the applying the condition of Pa, end and side surfaces of the external connection terminal, the thickness issued dew 1 0; on the surface of the copper layer of «m, to give a roughened surface of average 2 m.
  • EBARA sulfuric acid 7.5% by weight, phosphoric acid 3.8% by weight and hydrogen peroxide 4.0% by weight
  • an insulating resin KS 6600 (a product of Hitachi Chemical Co., Ltd.) which is a liquid silicone-modified polyamideimide resin having better adhesion to copper than nickel.
  • KS 6600 a product of Hitachi Chemical Co., Ltd.
  • VE-500 manufactured by Toray Engineering Co., Ltd.
  • the resin was sufficiently cured under the conditions of 180 ° C for 30 minutes and 220 ° C for 30 minutes to form a resin layer.
  • the copper layer having a thickness of 10 ⁇ m was selectively etched with an alkaline etching solution composed of a process liquid manufactured by Meltex Co., Ltd. to form a circuit connected to the external connection terminal.
  • an alkaline etching solution composed of a process liquid manufactured by Meltex Co., Ltd.
  • electrolytic nickel / gold plating (manufactured by Daiwa Electric Industry Co., Ltd.) is formed on the circuit surface and the exposed surface of the external connection terminal, and a semiconductor package substrate having a cross section shown in FIG. 13 (e) is formed.
  • Size: 12 mm X 12 mm was produced.
  • a die bonding film was attached to this substrate, and a semiconductor chip (size 8.6 mm X 8.6 mm) was mounted manually.
  • a 70 m copper layer of 70 jU m thick, a 0.2 m thick nickel layer, and a 10 m thick copper layer was fabricated by photo-drying a 70 m copper layer of Nippon Electrolysis Co., Ltd.
  • a pattern is formed using the film H-K350 (manufactured by Hitachi Chemical Co., Ltd.), and copper is selectively etched by an alkaline etching solution A process (manufactured by Meltex Co., Ltd.).
  • a metal column made of copper of 0250 / m was formed.
  • the exposed nickel layer and metal pillar surface were roughened using NB DII treatment solution (manufactured by Ebara Densan), a surface roughening agent for chemical treatment.
  • Example 6 In order to simultaneously remove the nickel layer of the barrier layer, the processing time was increased to 1.5 times that in Example 1. As a result, the nickel layer is removed except for the portion under the metal pillar, thereby forming a columnar external connection terminal. At the same time, the external connection terminal end face and side surfaces, and the exposed copper layer surface with a thickness of 10 jUm, A roughened surface having an average of 2 im was obtained in the same manner as in Example 6.
  • An insulating resin KS 6600 (manufactured by Hitachi Chemical Co., Ltd.), which is a liquid silicone-modified polyamideimide resin, is printed on the metal foil on which the external connection terminals are formed using a printing machine VE-500 (manufactured by Toray Engineering Co., Ltd.). After completely embedding the external connection terminals, the substrate was dried at 80 ° C for 30 minutes to obtain the B-stage state. After the end faces of the external connection terminals polished with embedded abrasive paper appeared, the resin was sufficiently cured under the conditions of 180 ° C for 30 minutes + 220 ° C for 30 minutes to form a resin layer.
  • Example 6 a circuit was formed with a copper layer having a thickness of 10 m in the same manner as in Example 6.
  • electrolytic nickel plating manufactured by Daiwa Electric Industry Co., Ltd.
  • a die bonding film was attached to this substrate, and a semiconductor chip was mounted manually.
  • wire bonding was performed using a wire bonder HW2100 (manufactured by Kyushu Matsushita Electric Co., Ltd.), After sealing with a sealant, dicing was performed to a predetermined size, and solder balls were soldered with a reflow device to obtain a semiconductor package.
  • a pattern is formed using H-K350 (manufactured by Hitachi Chemical Co., Ltd.), and copper is selectively etched by an alkali etching solution process (manufactured by Meltex).
  • a metal column made of copper of 025 O 0m was formed. Titanium is difficult to etch with a copper chemical roughening solution, so the titanium layer cannot be removed simultaneously with the roughening process.
  • the titanium layer was selectively etched with an ammonium fluoride-based etchant Enstrip (manufactured by Meltex Co.), excluding the portion under the metal pillar, exposing the surface of the 18-m-thick copper layer. External connection terminals were formed on the surface. Thereafter, the same and subsequent roughening processes as in Example 6 were performed to produce a semiconductor package. The adhesion between the resin layer and the copper layer (circuit) was the same as in Example 6.
  • Example 9 wiring board E, semiconductor package E
  • a pattern is formed using H-K350 (manufactured by Hitachi Chemical Co., Ltd.), and the copper layer is selectively etched by an alkaline etching solution A process (manufactured by Meltex).
  • a metal column made of copper of 0250 jU m was formed. Two types of metal sheets were produced, one with the Nigel layer selectively etched (Comparative Example) and one without (Example).
  • the metal sheet on which these two types of external insulating terminals were formed was not subjected to roughening treatment, and after resin printing, was manufactured in the same manner as in Example 6 to form a package.
  • a liquid silicone-modified polyamideimide resin having better adhesion to nickel than copper was used as the resin.
  • test pieces of the same size as those prepared in Example 6 were prepared using the above silicone-modified polyamide-imide resin, and the adhesion strength between the resin layer and the foil was determined for each.
  • the peel strength between the nickel layer and the resin layer was 0.75 kNZ m.
  • the peel strength between the copper layer and the resin layer was 0.50 kN Z m, and the close contact with the nickel layer was better.
  • the adhesion strength between the resin layer and the circuit and the external connection terminal is improved, and a highly reliable and small semiconductor package substrate having a plurality of columnar external connection terminals is provided. Can be provided. Applicability of the invention
  • a metal layer, a member for a wiring board, and a substrate for a semiconductor package in particular, when there is unevenness, a resin layer having good adhesion is formed without causing warpage or undulation. Can be formed. Therefore, the wiring boards A and B manufactured by the method of the present invention, and the semiconductor packages A and B manufactured using them are excellent in flatness without warpage or surface undulation.
  • the adhesion strength between the resin layer and the circuit and the external connection terminal is improved, and the reliability is high.

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  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention concerne un procédé de production d'un tableau de connexions, qui consiste à revêtir, par impression, un élément de câblage présentant à sa surface plusieurs bosses conductrices, avec une résine isolante liquide en vernis, avant polymérisation à une profondeur permettant d'ensevelir les bosses conductrices dans la résine isolante. Le procédé consiste ensuite à polymériser la résine isolante imprimée, puis à polir la résine isolante afin d'exposer les extrémités supérieures des bosses conductrices.
PCT/JP2003/003399 2002-05-28 2003-03-20 Substrat, tableau de connexions, substrat pour boitier a semi-conducteur, boitier a semi-conducteur et leurs procedes de production Ceased WO2003100850A1 (fr)

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AU2003220938A AU2003220938A1 (en) 2002-05-28 2003-03-20 Substrate, wiring board, semiconductor package-use substrate, semiconductor package and production methods for them

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JP2002-153578 2002-05-28
JP2002153578A JP2003347477A (ja) 2002-05-28 2002-05-28 基板、半導体パッケージ用基板、半導体装置及び半導体パッケージ
JP2002-219544 2002-07-29
JP2002219544A JP4196606B2 (ja) 2002-07-29 2002-07-29 配線板の製造方法
JP2002-231310 2002-08-08
JP2002231310A JP4288912B2 (ja) 2002-08-08 2002-08-08 配線板、半導体パッケージ用基板、半導体パッケージ及びそれらの製造方法

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JP2001118950A (ja) * 1999-10-18 2001-04-27 Sumitomo Metal Electronics Devices Inc ビルトアップ多層基板の製造法
JP2001135744A (ja) * 1999-11-05 2001-05-18 Sumitomo Metal Electronics Devices Inc Ｉｃパッケージの製造方法
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6464292A (en) * 1987-09-03 1989-03-10 Sharp Kk Manufacture of printed board
JPH0955577A (ja) * 1995-08-11 1997-02-25 Nec Corp 印刷配線板の製造方法
JPH11163207A (ja) * 1997-12-01 1999-06-18 Hitachi Chem Co Ltd 半導体チップ搭載用基板の製造法および半導体装置
JP2000183283A (ja) * 1998-12-18 2000-06-30 Denso Corp 積層型回路モジュール及びその製造方法
WO2000077850A1 (fr) * 1999-06-10 2000-12-21 Toyo Kohan Co., Ltd. Plaquage destine a former un element intercalaire dans un dispositif a semi-conducteur, un tel element intercalaire, et procede de fabrication associe
JP2001118950A (ja) * 1999-10-18 2001-04-27 Sumitomo Metal Electronics Devices Inc ビルトアップ多層基板の製造法
JP2001135744A (ja) * 1999-11-05 2001-05-18 Sumitomo Metal Electronics Devices Inc Ｉｃパッケージの製造方法
JP2002026048A (ja) * 2000-07-12 2002-01-25 Denso Corp 積層回路モジュールの製造方法

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