WO2003100853A1 - Substrat a multiples couches avec une bobine integree, puce a semi-conducteurs, procedes de facturation - Google Patents

Substrat a multiples couches avec une bobine integree, puce a semi-conducteurs, procedes de facturation Download PDF

Info

Publication number
WO2003100853A1
WO2003100853A1 PCT/JP2003/006648 JP0306648W WO03100853A1 WO 2003100853 A1 WO2003100853 A1 WO 2003100853A1 JP 0306648 W JP0306648 W JP 0306648W WO 03100853 A1 WO03100853 A1 WO 03100853A1
Authority
WO
WIPO (PCT)
Prior art keywords
coil
multilayer substrate
multilayer
forming
built
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2003/006648
Other languages
English (en)
Japanese (ja)
Inventor
Kouichirou Sagawa
Masahiko Oshimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ajinomoto Co Inc
Original Assignee
Ajinomoto Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ajinomoto Co Inc filed Critical Ajinomoto Co Inc
Priority to AU2003241820A priority Critical patent/AU2003241820A1/en
Publication of WO2003100853A1 publication Critical patent/WO2003100853A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type
    • H01F17/0006—Printed inductances
    • H01F17/0033—Printed inductances with the coil helically wound around a magnetic core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/34—Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
    • H01F27/36—Electric or magnetic shields or screens
    • H01F27/363—Electric or magnetic shields or screens made of electrically conductive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/497—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/501—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/34—Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
    • H01F27/36—Electric or magnetic shields or screens
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistors, capacitors or inductors
    • H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistors, capacitors or inductors incorporating printed inductors

Definitions

  • Multilayer substrate with built-in coil, semiconductor chip, and their manufacturing method (Technical field)
  • the present invention relates to a multilayer board (printed board) having a coil having a function as an inductor or a transformer, a semiconductor chip in which a multilayer board (inner poser, electrode wiring layer) is laminated, and a method of manufacturing the same. More specifically, it is a small-sized, multi-layer * 3 ⁇ 4 with a built-in coil that can set the number of turns and the forming direction almost arbitrarily and can suppress noise to other circuit elements.
  • the present invention relates to a semiconductor chip capable of suppressing noise from a coil included in the multilayer substrate, and a method for manufacturing the same.
  • Coils have been used in a wide range of fields, such as antennas and satellites, since ancient times.
  • a structure called an inductor using coils is manufactured in various parts and IC chips, and is widely used.
  • a chip-inducted version of only an inductor for surface mounting is called a chip-inductor, and for example, it has been reported that a mobile phone has more than 20 in one.
  • Parts called VCOs Voltage Controlled 0 sci 11 ator
  • VCOs Voltage Controlled 0 sci 11 ator
  • VCOs are oscillators whose oscillation frequency can be changed according to the applied voltage, and are important components that determine the quality of radio circuits.
  • Devices intended for use in the high-frequency range, such as mobile phones, which have exploded in recent years, are equipped with many of these components. As the so-called miniaturization of electronic devices has progressed, these components have become smaller. Modeling is required. .
  • a transformer for converting the voltage of the supplied current to a predetermined voltage also has a coil structure therein.
  • Transformers are often mounted on a substrate or a semiconductor chip in a Z-shape, and it is needless to say that miniaturization of the transformer is also required.
  • H11-204304 a circuit is known in which a circuit is printed on a green sheet with a conductive paste, laminated, and then fired to form a coil. ing.
  • this method is a single-layer coil, cannot secure a sufficient number of turns, and cannot obtain a sufficient inductance. In order to secure a sufficient number of turns, it is necessary to increase the number of laminations, and there is a limit in terms of cost and size.
  • stray capacitance cannot be ignored when using inductors in the high frequency range.
  • the stray capacitance is generated by the fact that the inductor coil acts as a capacitor by facing in the same plane.
  • problems also arises. This is because the stray capacitance generated between the coils is parallel to the electrodes.
  • Japanese Patent Application Laid-Open No. H11-214646 proposes a method of forming a solenoid coil in a direction perpendicular to the plane of a substrate.
  • this method since a solenoid coil is formed, the magnetic field is confined in the coil, and there is no problem in terms of noise.
  • the formed solenoid coil necessarily has so many # responsibilities.
  • Japanese Patent Application Laid-Open No. H10-284919 proposes a method of forming a coil in a direction perpendicular to the plane of a substrate as in the present invention. With this method, the problem is reduced because the aforementioned stray capacitance is in series with the electrode. This With the structure described above, the problem of noise at the time of mounting on a substrate is almost solved.
  • this method is a single-layer coil as in the case of the above method, it is not expected that a sufficient inductance is obtained.
  • the number of windings can be secured by extending in the direction parallel to the plane of the substrate, it is difficult to increase the density beyond a certain level due to the limitations of the manufacturing accuracy of through holes and conductive holes. Therefore, sufficient inductance cannot be obtained with a practical size.
  • increasing the number of stacked layers causes an increase in the rejection rate, resulting in an increase in cost.
  • Japanese Patent Application Laid-Open No. Sho 62-189970 shows a proposal by Indak Yu, similar to the present invention.
  • Japanese Patent Application Laid-Open No. 4-23710 proposes a transformer as well as an inductor.
  • a spiral circuit portion perpendicular to the substrate is formed by through holes or via holes, there is no specific description of a specific manufacturing method.
  • Japanese Patent Application Laid-Open No. 3-34407 proposes a chip inductor using a multilayer coil similar to the present invention in terms of the structure of the coil itself.
  • this proposal also relates to a chip inductor mounted on the surface of a printed wiring board, and has problems due to being a chip and also has a problem as a manufacturing method. That is, as a manufacturing method, a spiral structure is formed on one plane and laminated, so that a fine spiral structure needs to be formed by printing.
  • the chip inductors that have been studied in recent years are very small, 0.3 mm x 0.3 mm x 0.6 mm, and forming a helical structure on the cross-section by printing does not cause a short circuit due to bleeding. It is very difficult.
  • transformers also use coils.
  • the typical structure of a transformer has two coils with different numbers of turns arranged on both sides of a magnetic body. By adopting such a structure, it is possible to reduce the loss and change the pressure.
  • the coil making direction is perpendicular to the cross section of each coil, it is difficult to provide a magnetic layer between the two coils in the process. The magnetic material had to be reassembled as a single component, making it impossible to form it inside the substrate.
  • the present invention has a small size and the same size, which has less adverse effects such as noise on other components or circuits mounted / formed or built on a wiring board, and reduces mutual crosstalk even when embedded at high density.
  • the task is to make PC work 48 . It is another object of the present invention to provide a semiconductor chip in which such a coil or a transformer is integrally laminated and a method for manufacturing the same.
  • the invention described in claim 1 is a coil formed integrally with a multilayer substrate, the coil including a winding portion parallel to the multilayer substrate and a winding portion perpendicular to the multilayer substrate.
  • a coil supported in the multilayer substrate, and an insulator configured to support the coil, constitute at least a part of an insulating portion of the multilayer substrate, and include a stacked insulating layer.
  • the unit winding of the coil has a spiral pattern that turns in the opposite direction when viewed from the same direction as the other adjacent unit windings, and adjacent unit windings of the coil.
  • the sets of lines are characterized in that they are connected alternately at the tips or at the ends of the spiral pattern.
  • the invention described in claim 2 is a coil formed integrally with the multilayer substrate, the coil including a winding portion parallel to the multilayer substrate and a winding portion perpendicular to the multilayer substrate.
  • the invention described in claim 3 has the feature of the invention described in claim 2 and the unit winding of the coil is viewed from the same direction as another adjacent unit winding.
  • Each of the coils has a spiral pattern that turns in the opposite direction, and the sets of adjacent unit windings of the coil are connected alternately at the tips of the spiral pattern or at the ends thereof. It is characterized by.
  • the invention set forth in claim 4 is characterized in that, in addition to the features of the invention set forth in any one of claims 1 to 3, the coil has a winding portion parallel to the multilayer substrate.
  • PC 648 is formed as a part of the stacked conductive layers, and a winding portion perpendicular to the multilayer is formed as a bump connecting the adjacent conductive layer via the insulating layer.
  • the invention set forth in claim 5 provides, in addition to the features of the invention set forth in any one of claims 1 to 3, the coil is wound in parallel with the multilayer substrate by a build-up method.
  • the wire portion is formed as a part of the stacked conductive layers, and the winding portion perpendicular to the multilayer substrate is formed as a via or a through hole connecting the adjacent conductive layers through the insulating layer. It is characterized by.
  • the invention set forth in claim 6 provides, in addition to the features of the invention set forth in any one of claims 1 to 5, a planar core having a circuit surface in a plane parallel to the multilayer substrate. It is characterized by further having a filter.
  • the invention described in claim 7 has, in addition to the features of the invention described in any one of claims 1 to 6, a plurality of the coils, and the plurality of coils At least one coil is so arranged that the voltage induced in the other coil by the fluctuation of the magnetic field lines generated by the other coil is minimized.
  • the invention described in claim 8 has, in addition to the features of the invention described in any one of claims 1 to 6, a plurality of the coils, and the plurality of coils At least one of the coils is positioned so that a magnetic field line generated by one of the coils penetrates the other coil and a central axis of the other coil is orthogonal to the main coil.
  • the invention described in claim 9 is a coil formed integrally with the multilayer substrate, comprising a plurality of coils including a winding portion parallel to the multilayer substrate and a winding portion perpendicular to the multilayer substrate.
  • the invention described in claim 10 is a plurality of coils integrally formed with the multilayer substrate, wherein the winding portion is parallel to the multilayer substrate and the winding portion is vertical to the multilayer substrate.
  • the invention described in claim 11 is a plurality of coils integrally formed with the multilayer substrate, wherein the winding portion is parallel to the multilayer substrate and the winding portion is vertical to the multilayer substrate. And a plurality of coils supported in the multilayer substrate and arranged such that a main direction of a magnetic field generated by at least one coil penetrates another coil and a central axis of the other coil are orthogonal to each other.
  • a coil, and an insulator that supports the plurality of coils forms at least a part of an insulating portion of the multilayer substrate, and includes an insulating layer that is stacked.
  • the coil includes a winding portion parallel to the multilayer substrate. Is formed as a part of the stacked conductive layers, and a winding part perpendicular to the multilayer substrate is formed as a bump connecting the adjacent conductive layers via the insulating layer. .
  • the invention described in claim 13 is characterized in that, in addition to the features of the invention described in any one of claims 8 to 11, the coil is parallel to the multilayer substrate by a build-up method.
  • Winding part is formed as a part of the laminated conductive layer, and a winding part perpendicular to the multilayer substrate is formed as a via or a through hole connecting the adjacent conductive layer through the insulating layer. It is characterized by that.
  • the invention described in claim 14 is any one of claims 1 to 13
  • at least one of the coils is an inductor.
  • the invention described in claim 15 is characterized by the fact that, in addition to the features of the invention described in any one of claims 1 to 13, at least one of the coils is mutually magnetic. It is characterized by being a transformer consisting of two or more coils coupled to a transformer.
  • the invention described in claim 16 is characterized in that the coil-containing multilayer film according to any one of claims 1 to 15 is laminated on an outer surface.
  • the invention described in claim 17 is a step of forming one insulating layer constituting a multilayer substrate, and forming at least a part of a winding portion of a coil parallel to the multilayer substrate in the multilayer substrate.
  • At least one of the steps forming at least a part of the winding portion of the vertical coil is performed by changing the winding portion of the coil parallel to the multilayer substrate and the winding portion of the coil perpendicular to the multilayer substrate. And a step of appropriately repeating the previously formed multilayered portion until a predetermined coil supported in the multilayer substrate is formed with the portion.
  • Each of the unit windings has a spiral pattern that turns in the opposite direction when viewed from the same direction as another adjacent unit winding, and a set of adjacent unit windings of the predetermined coil. Are alternately connected at the tips or ends of the spiral pattern.
  • the invention described in claim 18 is a method of forming a multilayer substrate, comprising: forming one insulating layer constituting the multilayer substrate; and forming at least a part of a winding portion of a coil parallel to the multilayer substrate into the multilayer substrate. And a step formed on the insulating layer of Forming a vertical connection portion for electrically connecting at least some of the winding portions between the insulating layers, thereby forming at least a portion of a winding portion of the coil perpendicular to the multilayer substrate; Forming a core structure made of the magnetic material described above so as to be disposed inside the coil; forming the insulating layer; forming at least a part of a winding portion of the coil parallel to the multilayer substrate.
  • the step, and / or at least one of the steps forming at least a part of a winding portion of a coil perpendicular to the multilayer substrate is performed by using a winding portion of a coil parallel to the multilayer substrate and a direction perpendicular to the multilayer substrate.
  • the invention according to claim 19 is a method for forming a single insulating layer constituting a multilayer substrate, wherein at least a part of a winding portion of a coil parallel to the multilayer substrate is formed in the multilayer substrate. Forming on the insulating layer, forming a vertical connection portion for electrically connecting at least a part of the winding portion of the coil parallel to the multilayer substrate between the insulating layers, thereby forming the vertical connection portion.
  • the invention described in claim 20 forms one insulating layer constituting a multilayer substrate Forming at least a part of the winding portion of the coil parallel to the multilayer on the insulating layer in the multilayer substrate; and forming at least a portion of the winding portion of the coil parallel to the multilayer substrate. Forming a vertical connection portion for electrically connecting them to each other between the insulating layers, thereby forming at least a part of a winding portion of the coil perpendicular to the multilayer substrate; and forming the insulating layer.
  • a predetermined coil supported in the multilayer substrate is formed by the winding portion of the coil parallel to the multilayer substrate and the winding portion of the coil perpendicular to the multilayer substrate.
  • the coil has a main direction in which the magnetic field lines generated by at least one of the coils penetrate the other coil, and a center of the other coil. It is characterized by a plurality of coils arranged so that their axes are orthogonal to each other.
  • the invention set forth in claim 21 is characterized in that, in addition to the features of the invention set forth in claim 19 or 20, the core structure made of a columnar magnetic material is provided in at least one of the coils.
  • the method further comprises a step formed so as to be disposed inside the object.
  • the invention described in claim 22 is the invention according to any one of claims 17 to 21.
  • the multilayer substrate with a built-in coil is laminated on an outer surface of a semiconductor wafer. And separating the semiconductor element on which the coil built-in multi-layer substrate is stacked in units of semiconductor chips.
  • the invention set forth in claim 23 is characterized in that, in addition to the features of the invention set forth in any one of claims 17 to 21, the multilayer substrate with a built-in coil is provided on the outer surface of the semiconductor chip. It is characterized by being laminated. (Brief description of drawings)
  • FIG. 1 is a perspective view showing a schematic configuration of a multilayer substrate 1 with a built-in coil according to a first embodiment of the present invention. (In the following drawings, the coil part on the board is also shown, and other circuits, wiring, etc. are omitted.)
  • FIG. 2A is a perspective view showing a schematic configuration of a coil-embedded multilayer substrate 2 according to a second embodiment of the present invention, and FIGS. 2B and 2C show other coils. It is a figure showing an example of a structure. .
  • FIG. 3 is a perspective view showing a schematic configuration of a multilayer substrate 3 with a built-in coil according to a third embodiment of the present invention.
  • FIG. 4 is a perspective view showing a schematic configuration of a coil built-in multilayer substrate 4 according to a fourth embodiment of the present invention.
  • FIG. 5 is a perspective view showing a schematic configuration of a coil built-in multilayer substrate 5 according to a fifth embodiment of the present invention.
  • FIG. 6 is a perspective view showing a schematic configuration of a coil built-in multilayer substrate 6 according to a sixth embodiment of the present invention.
  • FIG. 7 is a perspective view showing a schematic configuration of a coil built-in multilayer substrate 7 according to a seventh embodiment of the present invention.
  • FIG. 8 is a perspective view showing a schematic configuration of a multilayer substrate 8 with a built-in coil according to an eighth embodiment of the present invention.
  • FIG. 9 is a perspective view showing a schematic configuration of a coil built-in multilayer substrate 9 according to a ninth embodiment of the present invention.
  • FIG. 10 is a cross-sectional view showing the arrangement of conductors of unit windings adjacent to each other in the coil.
  • FIG. 11 is a perspective view for explaining a manufacturing process of the multilayer substrate 1 with a built-in coil according to the first embodiment of the present invention.
  • FIG. 12 is a perspective view for explaining a manufacturing process of the coil-embedded multilayer substrate 3 according to the third embodiment of the present invention.
  • FIG. 13 is a perspective view for explaining a manufacturing process of the coil-embedded multilayer substrate 6 according to the sixth embodiment of the present invention.
  • FIG. 14 is a perspective view for explaining the manufacturing process of the coil-embedded multilayer substrate 7 according to the seventh embodiment of the present invention.
  • FIG. 15 is a perspective view of the initial stage of manufacturing the coil built-in multilayer substrate 1 according to the first embodiment of the present invention.
  • FIG. 16 is a perspective view showing an example of a method for manufacturing the coil-embedded multilayer substrate 1 according to the first embodiment of the present invention.
  • FIG. 17 is a perspective view showing an example of a method of manufacturing the coil-embedded multilayer substrate 1 according to the first embodiment of the present invention.
  • FIG. 18 is a perspective view showing an example of a method for manufacturing the coil-embedded multilayer substrate 1 according to the first embodiment of the present invention.
  • FIG. 19 is a perspective view showing an example of a method of manufacturing the coil-embedded multilayer substrate 1 according to the first embodiment of the present invention.
  • FIG. 20 is a perspective view illustrating an example of a method for manufacturing the coil-embedded multilayer substrate 1 according to the first embodiment of the present invention.
  • FIG. 21 is a perspective view illustrating an example of a method for manufacturing the coil-embedded multilayer substrate 1 according to the first embodiment of the present invention.
  • FIG. 22 is a perspective view illustrating an example of a method for manufacturing the coil-embedded multilayer substrate 1 according to the first embodiment of the present invention.
  • FIG. 23 is a perspective view showing an example of a method for manufacturing the coil-embedded multilayer substrate 1 according to the first embodiment of the present invention.
  • FIG. 24 shows an IC chip of the coil-embedded multilayer substrate 1 according to the first embodiment of the present invention.
  • FIG. 6 is a cross-sectional view of a first stage of manufacturing on a fin.
  • FIG. 25 is a cross-sectional view for explaining via formation.
  • FIG. 26 is a cross-sectional view for describing formation of a conductive pattern for forming a circuit.
  • FIG. 27 is a cross-sectional view for explaining the formation of the second insulating layer.
  • FIG. 28 is a cross-sectional view for explaining the formation of the second conductive pattern.
  • FIG. 29 is a cross-sectional view for explaining the formation of the third layer.
  • FIG. 30 is a cross-sectional view of a multilayer substrate with a built-in coil 1 according to the first embodiment of the present invention formed on an IC chip.
  • FIG. 31 is a cross-sectional view of a via.
  • FIG. 32 is a cross-sectional view showing an example of a multilayer with a built-in coil »1 according to the first embodiment of the present invention formed on an IC chip.
  • FIG. 33 is a cross-sectional view showing an example of the multilayer substrate 1 with a built-in coil according to the first embodiment of the present invention formed on a chip.
  • FIG. 34 is a conceptual diagram for explaining a preferable arrangement of a plurality of coils for minimizing noise due to mutual induction in the multilayer substrate with a built-in coil according to the present invention.
  • FIG. 35 is a perspective view of a vertical coil.
  • FIG. 36 is a plan view of the vertical coil.
  • FIG. 37 is a cross-sectional view of the vertical coil taken along the line AA.
  • FIG. 38 is a perspective view of a flat coil.
  • FIG. 39 is a plan view of the planar coil.
  • FIG. 40 is a cross-sectional view of the planar coil taken along the line BB.
  • FIG. 41 is a graph showing the signal passing characteristics of the vertical coil.
  • FIG. 42 is a graph showing the signal passing characteristics of the planar coil.
  • FIG. 43 is a plan view of a vertical coil (inter-coil distance 0.1 mm) arranged in parallel according to the first embodiment.
  • FIG. 44 is a graph illustrating the signal passing characteristics of the vertical coils (distance between coils: 0.1 mm) arranged in parallel according to the first embodiment.
  • FIG. 45 is a perspective view of a parallel-arranged planar coil (inter-coil distance 0.1 mm) according to the second embodiment. .
  • FIG. 46 is a graph showing the signal passing characteristic of the planar coil (the distance between the coils is 0.1 mm) arranged in parallel according to the second embodiment.
  • FIG. 47 is a perspective view of a vertical coil and a planar coil arranged adjacent to each other on the multilayer substrate with a built-in coil according to the third embodiment.
  • FIG. 48 is a graph illustrating signal passing characteristics of a vertical coil and a planar coil arranged adjacent to each other on the multilayer substrate with a built-in coil according to the third embodiment.
  • FIG. 49 is a perspective view of a vertical coil (distance between coils: 0.2 mm) arranged in parallel according to the first embodiment.
  • FIG. 50 is a graph illustrating the signal passing characteristics of the vertical coils (distance between coils: 0.2 mm) arranged in parallel according to the first example.
  • FIG. 51 is a perspective view of a plane coil (distance between coils: 0.2 mm) arranged in parallel according to the second embodiment.
  • FIG. 52 is a graph showing the signal passing characteristic of a planar coil (distance between coils: 0.2 mm) arranged in parallel according to the second embodiment.
  • FIG. 1 is a perspective view showing a schematic configuration of a multilayer substrate 1 with a built-in coil.
  • the multilayer substrate 1 with a built-in coil includes a coil 1a and a multilayer substrate 1c.
  • the coil 1a is a component that provides inductance and is formed as a part of the conductive layer in each forming step of the plurality of insulating layers and conductive layers in the multilayer substrate.
  • Coil 1 “a” has a central axis parallel to the multilayer substrate, and includes a winding portion parallel to the multilayer substrate and a winding portion perpendicular to the multilayer substrate (in this specification, such a central axis is parallel to the multilayer substrate).
  • the coil is called “vertical coil.")
  • the coil la is formed in a form in which unit windings having a repeating pattern of conducting wires having a rectangular or circular cross section are electrically and continuously connected in series (hereinafter, such as The coil is called a “multi-layer coil”.)
  • the form of the coil 1a and its unit winding in the present specification shall broadly include any form for providing inductance.
  • the unit windings of the coil 1a each have a spiral pattern that turns in the opposite direction when viewed from the same direction as other adjacent unit windings, and the unit windings adjacent to each other are:
  • the spiral patterns are connected to each other at the tips or ends.
  • a winding portion of the coil 1a parallel to the multilayer is formed as a part of a conductive layer to be laminated, and a winding portion perpendicular to the multilayer substrate is adjacent to the multilayer substrate via an insulating layer. Formed as bumps, vias, through holes, etc., connecting the conductive layers to be formed.
  • the multilayer substrate lc is formed by laminating insulating layers. In the actual step of forming the multilayer substrate 1c, insulating layers and conductive layers are alternately stacked. Then, the portion of the conductive layer becomes a part of the coil 1a, and the other portion of the insulating layer becomes the multilayer substrate 1c.
  • FIG. 11 is a schematic perspective view showing a manufacturing process by laminating the multilayer substrate 1 with a built-in coil.
  • the coil-embedded multilayer substrate 1 is manufactured by forming each part of the coil 1a on each of the insulating layers 1c, and then laminating and integrating them.
  • Built-in coil A circuit including another coil or the like may be formed on the layer substrate 1 in a direction extending parallel to the multilayer substrate, or on the upper or lower side of the multilayer substrate.
  • FIG. 2A is a perspective view showing a schematic configuration of the multilayer substrate 2 with a built-in coil.
  • the multilayer substrate 2 with a built-in coil has a structure in which a magnetic material 2d is arranged inside the coil 2a.
  • Each component of the multilayer board with a built-in coil 2 corresponds to the component of the multilayer board with a built-in coil 1 in which the reference numeral is changed from 1 to 2.
  • the magnetic body 2d is disposed inside the coil 2a, there is an advantage that the inductance of the coil 2a can be increased.
  • Figures 2 (b) and (c) are examples of other coil structures.
  • the coil is constituted only by the winding portion in the direction parallel or orthogonal to the center axis of the coil.
  • FIGS. 3A and 3B are perspective views showing a schematic configuration of the multilayer substrate 3 with a built-in coil.
  • the multilayer board 3 with a built-in coil has a coil 3 a whose central axis is parallel to the multilayer board, and a coil 3 a in which the center direction of the generated magnetic field is orthogonal to the coil 3 a and is parallel to the multilayer board.
  • the coil 3d is a multilayer coil.
  • FIGS. 4A and 4B are perspective views showing a schematic configuration of the multilayer substrate 4 with a built-in coil.
  • the multilayer substrate 4 with a built-in coil The coil 4a whose axis is parallel to the multilayer board and the coil 4b whose center axis is parallel to the multilayer board.
  • the voltage induced in the other coil by the fluctuation of the magnetic field generated by one of the coils is minimized.
  • a structure in which the magnetic field lines generated by any one coil penetrate the other coil and the central axis of the other coil is orthogonal to the other coil
  • the main direction of the magnetic field lines passing through the coil is, for example, the direction of a vector obtained by averaging the vectors of the magnetic field lines passing through the coil.
  • the coils 4d and 4d are multilayer coils.
  • FIG. 34 is a conceptual diagram for explaining a preferred arrangement of a plurality of coils for minimizing noise due to mutual induction in the multilayer coil 1 with a built-in coil according to the present invention.
  • FIG. 34 shows an arrangement in which the voltage induced in the second coil is minimized when the magnetic field lines generated by the first coil fluctuate.
  • the main direction in which the lines of magnetic force generated by the first coil penetrate the second coil and the center axis of the second coil are orthogonal to each other.
  • FIGS. 5A and 5B are perspective views showing a schematic configuration of the multilayer board 5 with a built-in coil.
  • the embodiment shown in FIG. 5A has a configuration in which a planar coil 5c having a circuit surface in a plane parallel to the multilayer substrate is added to the embodiment shown in FIG. 4A.
  • the embodiment shown in FIG. 5 (b) has a configuration in which a planar coil 5c having a circuit surface in a plane parallel to the multilayer substrate is added to the embodiment shown in FIG. 4 (b).
  • FIG. 6 is a perspective view showing a schematic configuration of the multilayer substrate 6 with a built-in coil.
  • the multilayer board 6 with a built-in coil is composed of a coil 6a whose central axis is parallel to the multilayer board and a coil 6 whose central axis is on the same straight line and whose central axis is parallel to the multilayer board. It has a structure arranged inside. By arranging the two coils in this manner, mutual inductance can be generated between the two coils, and a transformer can be formed. In this case, the efficiency of the transformer can be further increased by arranging the magnetic material along the central axis of both coils.
  • FIGS. 7A and 7B are perspective views showing a schematic configuration of the multilayer substrate 7 with a built-in coil.
  • the multilayer board 7 with a built-in coil includes a coil 7 a having a central axis parallel to the multilayer board and an adjacent coil 7 b having a central axis parallel to the coil 7 a in a multilayer board 7 c. Further, it has a structure in which a magnetic body 7d or 7e for magnetically coupling both coils efficiently is arranged. By arranging two coils in this way, a mutual inductance can be generated between the two coils, and a transformer can be formed.
  • the magnetic body can be placed between both coils like the magnetic material 7d shown in Fig. 7 (a), and for more efficient magnetic coupling, it is shown in Fig. 7 (b).
  • the coils may be arranged so as to have an annular shape having a portion penetrating the central axis of both coils like the magnetic body 7e.
  • FIG. 8 is a perspective view showing a schematic configuration of the multilayer substrate 8 with a built-in coil.
  • the multilayer substrate 8 with a built-in coil includes a coil 8a whose central axis is parallel to the multilayer substrate and a multilayer substrate 8c.
  • the unit winding of the coil la has a spiral structure conductor parallel to the multilayer board
  • the structure is like two in a plane. With such a structure, a very dense coil can be formed in a limited volume, and the inductance can be increased.
  • FIG. 9 is a perspective view showing a schematic configuration of a coil-embedded multilayer substrate 9 according to a ninth embodiment of the present invention. In the coil-embedded multilayer substrate 9, the magnetic material 9d is arranged between the two spiral-structured conductors of the unit winding, so that a larger inductance can be obtained.
  • the multilayer boards 1 to 9 with a built-in coil are preferably used as an ink poser for mounting a semiconductor chip constituting a printed circuit board, a monolithic IC, or the like, or as an electrode wiring layer of the semiconductor chip.
  • the coil-embedded multilayer boards 1 to 9 can be formed with other circuit elements inside or mounted outside, and are composed of such other circuit elements and the coil-embedded multilayer boards 1 to 9 It is possible to configure a semiconductor in which the function of the circuit is added to the function of the semiconductor chip itself.
  • the number of windings of the coil-embedded multilayer substrates 1 to 9 can be easily and almost arbitrarily set by adjusting the extension direction of the coil, and the self and mutual inductance can be freely changed.
  • the inductance can be set flexibly by adjusting the area where the unit winding interlinks with the magnetic field as a whole or partially. Further, by arranging a magnetic material inside the coil, the inductance can be increased.
  • the multilayer boards 1 to 9 with built-in coils function as an inductor or a transformer when a voltage is applied from an external circuit through the terminals on both sides of the coil.
  • FIG. 41 is a graph showing the signal passing characteristics of the vertical coil determined by simulation.
  • FIG. 42 is a graph showing the signal passing characteristics of the planar coil obtained by the simulation.
  • FIG. 44 shows a graph in which the signal passing characteristics of a vertical coil (first embodiment) having a parallel arrangement of 0.1 mm and having the structure shown in FIG. S 21, S 31, and S 41 in FIG. 44 are, respectively, terminals T 1 to T 2, terminals T 1 to T 3, and terminals ⁇ 1 to ⁇ in FIG. 43. Indicates the degree of signal transmission to 4 (the same applies to the following figures).
  • FIG. 41 is a graph showing the signal passing characteristics of the vertical coil determined by simulation.
  • FIG. 42 is a graph showing the signal passing characteristics of the planar coil obtained by the simulation.
  • FIG. 44 shows a graph in which the signal passing characteristics of a vertical coil (first embodiment) having a parallel arrangement of 0.1 mm and having the structure shown in FIG. S 21, S 31, and S 41 in FIG. 44 are, respectively, terminals T
  • FIG. 46 is a graph showing the signal passing characteristics of the plane coil (the second embodiment) in parallel arrangement with the distance between the coils of 0.1 mm whose structure is shown in FIG.
  • FIG. 48 shows a graph in which the signal passing characteristics of the vertically arranged coil and the planar coil (third embodiment) whose structures are shown in FIG. 47 are obtained by simulation.
  • FIG. 50 shows a graph in which the signal passing characteristics of a vertical coil (first embodiment) having a parallel arrangement with a distance between coils of 0.2 mm whose structure is shown in FIG.
  • FIG. 52 shows a graph in which the signal passing characteristics of the planar coil (the second embodiment) of which the distance between the coils is 0.2 mm and whose structure is shown in FIG. From these results, in the third embodiment shown in FIG.
  • the values of S 31 and S 41 are higher than those of the first example shown in FIG. 43 and the second example shown in FIG.
  • Signal leakage is about 5 dB lower. Therefore, from the viewpoint of signal leakage, the third embodiment shown in FIG. 47 has a higher signal arrangement than the first embodiment shown in FIG. 43 and the second embodiment shown in FIG. It can be seen that the leakage is improved.
  • the degree of improvement in signal leakage is superior to the first embodiment shown in FIG. 49 and the second embodiment shown in FIG. 51 in which the distance between the coils is 0.2 mm. It can be seen from the signal passing characteristics in Fig. 5 ⁇ and Fig. 52. It should be noted that signal leakage is actively used to couple It can be seen that when functioning as a lance or the like, the first and second embodiments are more suitable than the third embodiment.
  • the method of manufacturing the multilayer substrate with a built-in coil according to the present invention will be specifically described with a focus on the coil portion for simplifying the description.
  • the inner layer (second layer) shown in Fig. 11 is often prepared by drilling holes in a double-sided copper-clad laminate, making the through holes conductive by plating, and performing surface subtraction by subtractive methods. A known method can be applied.
  • an insulating layer and a conductive layer are formed on both sides of the second layer, and the patterning and electrical connection are performed.
  • an insulating layer is formed on the substrate of the second layer (comprising la and lb).
  • the insulating layer may be a glass epoxy or aramide resin based pre-predader, a liquid or film-like thermoplastic or thermosetting resin composition, or a copper foil with resin, generally called a resin-coated copper foil. What integrated the umami layer etc. can be used.
  • the formation of the insulating layer is performed, for example, as follows. As shown in Fig. 15 (a), the prepregs 10 and the unpatterned copper foil 11 on both sides of the second layer substrate, or resin as shown in Fig. 15 (b) A copper foil 12 is attached, and these are collectively laminated and cured by a lamination press method as shown in FIG. 16 to produce an integrated insulating layer and conductive layer. (Alternatively, as shown in Figure 17 The liquid composition is applied by a known and conventional method such as screen printing, curtain coating, spray coating and the like, and cured by uv, electron beam, heat or the like. Alternatively, the insulating composition 13 is obtained by pasting the film-shaped composition on the substrate by a method such as roll or lamination, and curing it by a predetermined method.
  • a via is formed.
  • Vias 14 are formed at predetermined positions on the substrate obtained by the above method using a drill, a laser, or the like.
  • Fig. 18 (a) shows the case where prepreg 10 and copper foil 11 are used as the insulating layer and conductive layer.
  • Fig. 18 (b) shows copper foil 12 with resin and Fig. 18 (c).
  • a liquid or film-like thermoplastic or thermosetting resin composition 15 is used.
  • a conductive paste containing conductive powder such as silver or copper in vias 16 is embedded by printing, dispensing, etc., and cured by a predetermined method.
  • a usual through-hole printing that is, a method of forming a plating layer 17 by applying a plating catalyst in a via, then performing an electroless plating, and then performing an electrolytic plating. Electrical connection is also achieved.
  • an insulating layer is formed using a liquid or film-like composition, as shown in FIG. 19 (c), for example, copper foil 11 is pressed to form a conductive layer outside the insulating layer, and After masking the position of the blind via, conductive paste 1
  • the blind via may be made conductive first.
  • a catalyst is applied to the substrate on which the insulating layer and the blind via have been formed, subjected to an electroless printing process, and then if necessary. Then, by performing electrolytic plating, the formation of the conductive layer 18 and the conductivity of the blind via can also be performed at a time.
  • the blind vias can be made conductive by using a conductive base.
  • the insulating layer, the conductive layer, and the electrical connection can be collectively performed by the following method. That is, as shown in FIG. 20, after forming a conductive bump 19 having a sharp tip at a predetermined position on the second layer substrate circuit using a conductive paste or the like, the pre-preg 10 and the copper foil 1 are formed. 1 (Fig. 20 (a)) or film-shaped insulator 20 and copper foil 11 (Fig. 20 (b)), or press work after placing copper foil 12 with resin (Fig. 20 (c)) ), The pointed conductive bumps 19 penetrate the insulating layer to realize connection with the conductive layer.
  • the blind via is preferably filled with a conductive material such as a conductive paste or a plating, so that the entire cross section of the coil is a conductive material.
  • a conductive material such as a conductive paste or a plating
  • the coil formed using the method of the present invention such as low noise, mechanical strength, and freedom of design can be used. The characteristics do not change at all, and can be used without any problem depending on the frequency band.
  • the hole filling is used.
  • through-holes or blind vias may be filled by plating to smooth the surface.
  • the layers can be laminated at once by the following method.
  • a four-layer coil using a glass epoxy prepreg as the insulating layer will be described. That is, as shown in FIG. 21, a predetermined position on the base material side of the copper-clad single-sided glass epoxy substrate 21 is punched using a laser or the like. Subsequently, electric plating is performed using the copper foil 11 as an electrode, and the resulting hole is filled with a plating 17. Then, low melting point metal bumps 22 are successively formed by the plating method.
  • the copper foil 11 is etched into a predetermined pattern as shown in FIG.
  • the same insulator composition 23 as that used for the insulating layer is thinly applied and semi-cured.
  • the one shown in FIG. 22 manufactured from this single-sided substrate is the outermost layer, that is, the first and fourth layers.
  • the substrate of the second layer and the outermost layer of FIG. 22 are aligned, and the composition which has been semi-hardened by pressing is removed from the bump portion, and the interlayer At the same time as forming the insulating layer, the bump portion is electrically connected to the conductor in the inner layer, and a coil having a four-layer structure is manufactured.
  • the thickness of the insulating layer can be arbitrarily set according to the application, but from the viewpoint of insulation reliability, it is preferably about 10 to 300 microns in practical use.
  • the thickness of the conductor can be arbitrarily set according to the application as in the case of the insulating layer, but practically, it is preferably about 5 microns or 200 microns.
  • the coil of the present invention can obtain a larger inductance.
  • the formation of the magnetic core structure is performed by applying a paste containing iron, ferrite, etc. to the relevant parts o
  • the manufacturing process of the coil portion has been described.
  • other circuits and wiring required as a target are formed on each layer where the coil is formed as necessary. . Therefore, each step is appropriately selected from several methods so as to be consistent with the formation of other circuits and wirings.
  • FIG. 10 is a cross-sectional view of a spiral circuit of a coil showing an example of this case. The above problem can be solved by manufacturing the coil with a structure in which the respective patterns of the first circuit surface and the second circuit surface are repeated.
  • each layer is formed independently, as shown in an example in FIG. 11, and the spiral structure is formed at the time of lamination. Defects such as short circuits do not occur essentially. Also, about half of each helical structure is formed by a so-called through hole. The through hole has a circular cross section, so there are no corners and the resistance can be kept low. Furthermore, delamination does not occur on the spiral circuit surface after the lamination is performed, and no delamination occurs.
  • the stray capacitance cannot be ignored when using the inductor in the high frequency range.
  • the stray capacitance is generated by the fact that the inductor coil acts as a capacitor by facing in the same plane.
  • this problem is reduced because the stray capacitance of the inductor is considered to be in series with the electrode surface.
  • the structure in which the coil surfaces are shifted as shown in FIG. 10 can be easily manufactured without using any special technique. By using this structure, the stray capacitance can be essentially reduced. This makes it possible to keep the self-resonant frequency of the inductor high.
  • multilayer boards with built-in coils of various embodiments can be manufactured.
  • an insulator and a conductor may be laminated as shown in FIG.
  • the coil-embedded multilayer substrate 6 shown in FIG. 6 may be formed by stacking an insulator and a conductor.
  • the multilayer substrate with a built-in coil 7 shown in FIG. 7A may be formed by laminating an insulator, a conductor, and a magnetic material.
  • any of the above-described multilayer boards with a built-in coil can be formed on a semiconductor chip constituting a monolithic IC or the like. With such a configuration, elements such as coils can be incorporated in the semiconductor with a high degree of integration. From this, the process of forming a coil whose central axis is parallel to the plane of the substrate on the semiconductor substrate will be described below.
  • a multilayer substrate 1 with a built-in coil shown in FIG. 1 is formed on a so-called electrode wiring layer above a silicon wafer having a transistor formed thereon and an electrode portion formed of tungsten or the like.
  • the semiconductor is not limited to silicon, and any known semiconductor material such as gallium arsenide can be used.
  • a lowermost insulating layer 25 is formed on a silicon wafer 24 on which transistors and electrode portions are formed.
  • the silicon oxide film can be formed by a vapor phase method such as CVD, or by post-baking an organic material such as polyimide or benzocyclobutene, which has recently been attracting attention, after spin coating.
  • holes 26 are formed in necessary places using various lasers. The hole 26 is a place for making an electrical connection with a specific part of the semiconductor wafer 24 or a lower electrode part.
  • a conductive pattern 27 is formed.
  • a commonly used layer of aluminum or copper is formed by a vapor phase method such as CVD or a wet method such as plating.
  • PC crane 48 Next, it is exposed, etched and patterned.
  • the conductive layer may be formed after the patterned resist layer is formed first.
  • the hole 26 formed in the step shown in FIG. 25 is also electrically conductive, and the first layer and the second layer are electrically connected.
  • the surface is usually planarized by physical polishing, or a method called CMP which combines chemical polishing and physical polishing.
  • a second insulating layer 28 is formed.
  • a hole is formed again, and a second conductive pattern 29 is formed by forming a conductive pattern.
  • a third insulating layer 30 is formed by the above-described method, a hole is formed, conduction is performed, and a patterning is performed to form a third conductive pattern 31 and a second layer is formed. Take the third layer conduction.
  • this operation is repeated to form a fourth insulating layer 32, as shown in FIG. 30, and then perform drilling, conduction, and patterning to form a fourth conductive pattern 33. .
  • this operation it is possible to easily increase or decrease the number of evenings, increase or decrease the number of rows (layers), or form multiple coils having different extension directions.
  • the hole (via hole) 34 is filled with a conductor 35.
  • a structure generally called a so-called via that is, a structure having a via hole on a filled via hole can be formed again, and the side of the coil can be made straight.
  • a stacked via structure cannot be formed by a commonly used method, that is, a method in which a via hole is not filled with a conductor. At that time, the manufactured coil has a cross-section in which the via-hole connection portion is stepped as shown in FIG. Even with such a structure, there is a practical problem, especially when used in the high frequency range.
  • the silicon wafer 24 and the multilayer substrate including the coil are separated into semiconductor chip units. You.
  • the silicon wafer 24 Before laminating a multilayer substrate having a coil built in the silicon wafer 24, the silicon wafer 24 can be cut into chips.
  • a multilayer substrate having a built-in coil may be laminated on the outer surface of the semiconductor chip cut in advance in the same manner as in the above-described process.
  • the multilayer substrate with a built-in coil of the present invention can change the number of windings (the number of layers) arbitrarily in the same process with a small size and the same process.
  • it not only has a built-in coil that can change the forming direction arbitrarily, but also has no adverse effects such as noise generation on other parts and circuits. It has an unprecedented advantage that crosstalk between coils can be avoided.
  • the so-called tombstone phenomenon that occurs when a coil is mounted in close proximity, which is seen in a chip inductor having a similar structure as a coil, does not occur. Because of such features of the multilayer substrate of the present invention, it can be said that this type of coil, which was rarely omitted in the past, has reached the stage of practical use for the first time.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

L'invention concerne un substrat à multiples couches avec une bobine intégrée, peu influencée par le bruit et l'empreinte magnétique, ou une capacité parasite attribuée à la bobine intégrée. L'invention traite également d'un procédé de fabrication de ce dernier. Le substrat à multiples couches comprend une bobine formée de manière solidaire avec ce substrat, et comprend une partie d'enroulement parallèle au substrat, et une partie d'enroulement verticale par rapport à ce dernier. En outre, il comprend un isolant supportant la bobine formant au moins une partie d'une partie isolante du substrat et formée de plusieurs couches isolantes empilées. Ce substrat se caractérise en ce que la bobine se compose de divers enroulements comportant chacun un motif de spiral dont le sens est opposé à celui des enroulements adjacents, lorsqu'on les regarde dans le même sens, et en ce que l'extrémité de tête du motif en spirale de l'enroulement est reliée à une extrémité de tête d'un enroulement unitaire adjacent, et l'extrémité arrière de la spirale de l'enroulement adjacent est reliée à l'extrémité arrière de cette autre unité adjacente, et ainsi les enroulements sont reliés.
PCT/JP2003/006648 2002-05-29 2003-05-28 Substrat a multiples couches avec une bobine integree, puce a semi-conducteurs, procedes de facturation Ceased WO2003100853A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003241820A AU2003241820A1 (en) 2002-05-29 2003-05-28 Multilayer substrate with built-in coil, semiconductor chip, methods for manufacturing them

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002156261A JP2005347286A (ja) 2002-05-29 2002-05-29 コイル内蔵多層基板、半導体チップ、及びそれらの製造方法
JP2002-156261 2002-05-29

Publications (1)

Publication Number Publication Date
WO2003100853A1 true WO2003100853A1 (fr) 2003-12-04

Family

ID=29561465

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2003/006648 Ceased WO2003100853A1 (fr) 2002-05-29 2003-05-28 Substrat a multiples couches avec une bobine integree, puce a semi-conducteurs, procedes de facturation

Country Status (4)

Country Link
JP (1) JP2005347286A (fr)
AU (1) AU2003241820A1 (fr)
TW (1) TW200410376A (fr)
WO (1) WO2003100853A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012521089A (ja) * 2009-03-18 2012-09-10 アギア システムズ インコーポレーテッド 磁気結合が低減された集積回路インダクタ
US20230008016A1 (en) * 2021-07-12 2023-01-12 Samsung Electro-Mechanics Co., Ltd. Coil component

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5433199B2 (ja) * 2008-10-21 2014-03-05 学校法人慶應義塾 電子回路
US20120314389A1 (en) * 2011-03-25 2012-12-13 Ibiden Co., Ltd. Wiring board and method for manufacturing same
US9113569B2 (en) * 2011-03-25 2015-08-18 Ibiden Co., Ltd. Wiring board and method for manufacturing same
JP5767495B2 (ja) 2011-03-29 2015-08-19 パナソニック株式会社 可変インダクタ及びこれを用いた半導体装置
JP2013070035A (ja) * 2011-09-22 2013-04-18 Ibiden Co Ltd 多層プリント配線板
US9275950B2 (en) * 2012-05-29 2016-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Bead for 2.5D/3D chip packaging application
JP6306288B2 (ja) * 2013-05-13 2018-04-04 日東電工株式会社 コイルプリント配線基板、受電モジュール、電池ユニットおよび受電通信モジュール
JP5907124B2 (ja) 2013-07-24 2016-04-20 株式会社村田製作所 高周波部品およびフィルタ部品
JP5970714B2 (ja) 2013-10-30 2016-08-17 株式会社村田製作所 電子部品
JP6327639B2 (ja) * 2014-04-18 2018-05-23 日本電信電話株式会社 直交型ソレノイドインダクタ
JP6582401B2 (ja) * 2014-12-01 2019-10-02 富士電機株式会社 信号伝達装置
JP6989465B2 (ja) 2018-09-05 2022-01-05 株式会社東芝 磁気カプラ及び通信システム
JP7219136B2 (ja) * 2019-03-27 2023-02-07 本田技研工業株式会社 半導体装置
TWI754576B (zh) * 2021-04-08 2022-02-01 恆勁科技股份有限公司 電感結構
TWI769073B (zh) * 2021-09-01 2022-06-21 恆勁科技股份有限公司 電子封裝件
WO2023048105A1 (fr) * 2021-09-21 2023-03-30 ローム株式会社 Puce de transformateur
JP2024064086A (ja) * 2022-10-27 2024-05-14 Tdk株式会社 積層型電子部品
WO2025154346A1 (fr) * 2024-01-19 2025-07-24 国立大学法人 東京大学 Dispositif à semi-conducteur et puce à semi-conducteur

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04237106A (ja) * 1991-01-21 1992-08-25 Nippon Telegr & Teleph Corp <Ntt> 集積化インダクタンス素子及び集積化トランス
JPH0555043A (ja) * 1991-08-22 1993-03-05 Fujitsu Ltd 小型コイルとその製造方法，磁気ヘツドの製造方法及び磁気記憶装置
EP0588503A2 (fr) * 1992-09-10 1994-03-23 National Semiconductor Corporation Circuit intégré d'élément de mémoire magnétique et sa méthode de fabrication
JPH08250333A (ja) * 1995-03-14 1996-09-27 Taiyo Yuden Co Ltd インダクタアレイ
JPH0945866A (ja) * 1995-08-02 1997-02-14 Hitachi Ltd マイクロ波集積回路
JPH10154795A (ja) * 1996-11-19 1998-06-09 Advanced Materials Eng Res Inc 半導体チップにおけるインダクター及びその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04237106A (ja) * 1991-01-21 1992-08-25 Nippon Telegr & Teleph Corp <Ntt> 集積化インダクタンス素子及び集積化トランス
JPH0555043A (ja) * 1991-08-22 1993-03-05 Fujitsu Ltd 小型コイルとその製造方法，磁気ヘツドの製造方法及び磁気記憶装置
EP0588503A2 (fr) * 1992-09-10 1994-03-23 National Semiconductor Corporation Circuit intégré d'élément de mémoire magnétique et sa méthode de fabrication
JPH08250333A (ja) * 1995-03-14 1996-09-27 Taiyo Yuden Co Ltd インダクタアレイ
JPH0945866A (ja) * 1995-08-02 1997-02-14 Hitachi Ltd マイクロ波集積回路
JPH10154795A (ja) * 1996-11-19 1998-06-09 Advanced Materials Eng Res Inc 半導体チップにおけるインダクター及びその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012521089A (ja) * 2009-03-18 2012-09-10 アギア システムズ インコーポレーテッド 磁気結合が低減された集積回路インダクタ
US20230008016A1 (en) * 2021-07-12 2023-01-12 Samsung Electro-Mechanics Co., Ltd. Coil component

Also Published As

Publication number Publication date
JP2005347286A (ja) 2005-12-15
TW200410376A (en) 2004-06-16
AU2003241820A1 (en) 2003-12-12

Similar Documents

Publication Publication Date Title
US6872893B2 (en) Wiring board provided with passive element and cone shaped bumps
WO2003100853A1 (fr) Substrat a multiples couches avec une bobine integree, puce a semi-conducteurs, procedes de facturation
US7170384B2 (en) Printed circuit board having three-dimensional spiral inductor and method of fabricating same
US7855626B2 (en) Inductor and electric power supply using it
KR100862544B1 (ko) 고주파 모듈 장치
JP5005427B2 (ja) 多層プリント配線板の製造方法
WO2004021373A1 (fr) Dispositif a inductance, substrat multicouches a dispositif a inductance incorpore, puce semi-conductrice, et dispositif a inductance a puce
US20160284462A1 (en) Coil-embedded integrated circuit substrate and method of manufacturing the same
JP2008171965A (ja) 超小型電力変換装置
JP3436525B2 (ja) 多層基板と電子部品と多層基板の製造方法
WO2004021374A1 (fr) Element inducteur variable, substrat multicouches a element inducteur variable incorpore, puce semi-conductrice, et element inducteur variable a puce
JP2004127966A (ja) インダクティブ素子とその製造方法
JP2005347782A (ja) Ｌｃ直列共振回路、ｌｃ直列共振回路内蔵基板、及びそれらの製造方法
JP4515477B2 (ja) 受動素子を備えた配線板の製造方法
JP2005347287A (ja) 多層基板内シールド線、半導体チップ、電子回路素子、及びそれらの製造方法
JP2006013117A (ja) インダクタ構造体
JP2005347781A (ja) Ｌｃ並列共振回路、ｌｃ並列共振回路内蔵多層基板、及びそれらの製造方法

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NI NO NZ OM PH PL PT RO RU SC SD SE SG SK SL TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP