WO2003102786A3 - Datenverarbeitungsschaltung und verfahren zum übertragen von daten - Google Patents

Datenverarbeitungsschaltung und verfahren zum übertragen von daten Download PDF

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Publication number
WO2003102786A3
WO2003102786A3 PCT/EP2003/005641 EP0305641W WO03102786A3 WO 2003102786 A3 WO2003102786 A3 WO 2003102786A3 EP 0305641 W EP0305641 W EP 0305641W WO 03102786 A3 WO03102786 A3 WO 03102786A3
Authority
WO
WIPO (PCT)
Prior art keywords
rail
processing circuit
data
technique
dual
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2003/005641
Other languages
English (en)
French (fr)
Other versions
WO2003102786A2 (de
Inventor
Astrid Elbe
Norbert Janssen
Holger Sedlak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to AU2003232840A priority Critical patent/AU2003232840A1/en
Priority to JP2004509804A priority patent/JP3999229B2/ja
Publication of WO2003102786A2 publication Critical patent/WO2003102786A2/de
Publication of WO2003102786A3 publication Critical patent/WO2003102786A3/de
Priority to US11/004,658 priority patent/US6970016B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)
  • Bus Control (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Eine Datenverarbeitungsschaltung umfaßt einen Single-Rail-Bus (10) mit einer Single-Rail-Leitung (12), einen Dual-Rail-Bus (14) mit einer ersten Dual-Rail-Leitung (14a) für Datenbits und einer zweiten Dual-Rail-Leitung (14b) für invertierte Datenbits sowie eine Umsetzungseinrichtung (16) zum Überführen von Signalen auf dem Single-Rail-Bus in Signale auf dem Dual-Rail-Bus und umgekehrt. Durch Einsetzen sowohl der Single-Rail-Technik als auch der Dual-Rail-Technik mit Precharge oder Pre-Discharge oder ohne Precharge in einer Datenverarbeitungsschaltung wird ein optimaler Kompromiß zwischen Sicherheit einerseits und Chipflächenverbrauch und Leistungsverbrauch andererseits erreicht, indem Bereiche, in denen sicherheitskritische Daten verarbeitet werden, in Dual-Rail-Technik ausgeführt werden, während Bereiche, in denen weniger sicherheitskritische Daten verarbeitet werden, in Single-Rail-Technik ausgeführt werden, und wobei Schnittstellen zwischen diesen Bereichen mit einer Umsetzungseinrichtung versehen werden.
PCT/EP2003/005641 2002-06-04 2003-05-28 Datenverarbeitungsschaltung und verfahren zum übertragen von daten Ceased WO2003102786A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU2003232840A AU2003232840A1 (en) 2002-06-04 2003-05-28 Data processing circuit and method for transmitting data
JP2004509804A JP3999229B2 (ja) 2002-06-04 2003-05-28 データ処理回路およびデータ伝送方法
US11/004,658 US6970016B2 (en) 2002-06-04 2004-12-03 Data processing circuit and method for transmitting data

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10224742.0 2002-06-04
DE10224742A DE10224742B4 (de) 2002-06-04 2002-06-04 Datenverarbeitungsschaltung und Verfahren zum Übertragen von Daten

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/004,658 Continuation US6970016B2 (en) 2002-06-04 2004-12-03 Data processing circuit and method for transmitting data

Publications (2)

Publication Number Publication Date
WO2003102786A2 WO2003102786A2 (de) 2003-12-11
WO2003102786A3 true WO2003102786A3 (de) 2004-05-13

Family

ID=29594248

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2003/005641 Ceased WO2003102786A2 (de) 2002-06-04 2003-05-28 Datenverarbeitungsschaltung und verfahren zum übertragen von daten

Country Status (6)

Country Link
US (1) US6970016B2 (de)
JP (1) JP3999229B2 (de)
AU (1) AU2003232840A1 (de)
DE (1) DE10224742B4 (de)
TW (1) TW200307870A (de)
WO (1) WO2003102786A2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004027372B4 (de) * 2004-06-04 2006-03-30 Infineon Technologies Ag DPA-resistente konfigurierbare Logikschaltung
DE102004053127B4 (de) * 2004-11-03 2006-07-27 Infineon Technologies Ag Schaltungsanordnung mit schaltbarer Ladungsneutralität und Verfahren zum Betreiben einer Dual-Rail-Schaltungsanordnung
FR2880217A1 (fr) 2004-11-03 2006-06-30 Infineon Technologies Ag Montage a mode de securite et a mode d'economie d'energie.
US8074193B2 (en) * 2009-03-11 2011-12-06 Institute of Computer Science (ICS) of the Foundation for Research & Technology Hellas-Foundation for Research and Technology Hellas (FORTH) Apparatus and method for mixed single-rail and dual-rail combinational logic with completion detection
EP2523385B1 (de) * 2011-05-05 2017-07-12 Proton World International N.V. Verfahren und Schaltung für kryptografische Operation
US10630293B2 (en) * 2017-03-31 2020-04-21 Adanced Micro Devices, Inc. High speed transmitter
FR3076925B1 (fr) 2018-01-16 2020-01-24 Proton World International N.V. Fonction cryptographique

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0715262A1 (de) * 1994-12-02 1996-06-05 BULL HN INFORMATION SYSTEMS ITALIA S.p.A. Adapter/Wandler für differentiale und unsymetrische SCSI-Schnittstelle
US5608883A (en) * 1993-02-01 1997-03-04 Digital Equipment Corporation Adapter for interconnecting single-ended and differential SCSI buses to prevent `busy` or `wired-or` glitches from being passed from one bus to the other
EP0788059A1 (de) * 1996-01-31 1997-08-06 Kabushiki Kaisha Toshiba Treiberschaltungsvorrichtung
EP1197872A2 (de) * 2000-10-06 2002-04-17 Broadcom Corporation Bus, der auf einer Flanke eines Taktsignals abtastet und auf der anderen Flanke treibt

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3631992A1 (de) 1986-03-05 1987-11-05 Holger Sedlak Kryptographie-verfahren und kryptographie-prozessor zur durchfuehrung des verfahrens
DE3763872D1 (de) * 1986-03-05 1990-08-30 Holger Sedlak Kryptographie-verfahren und kryptographie-prozessor zur durchfuehrung des verfahrens.
JP2812097B2 (ja) * 1992-09-30 1998-10-15 日本電気株式会社 半導体記憶装置
JP2000048570A (ja) * 1998-07-28 2000-02-18 Mitsubishi Electric Corp 半導体記憶装置
US6236240B1 (en) * 1999-01-29 2001-05-22 Texas Instruments Incorporated Hold-time latch mechanism compatible with single-rail to dual-rail conversion
US6265923B1 (en) * 2000-04-02 2001-07-24 Sun Microsystems, Inc. Dual rail dynamic flip-flop with single evaluation path
KR100486261B1 (ko) * 2002-09-16 2005-05-03 삼성전자주식회사 스큐가 없는 듀얼 레일 버스 드라이버

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5608883A (en) * 1993-02-01 1997-03-04 Digital Equipment Corporation Adapter for interconnecting single-ended and differential SCSI buses to prevent `busy` or `wired-or` glitches from being passed from one bus to the other
EP0715262A1 (de) * 1994-12-02 1996-06-05 BULL HN INFORMATION SYSTEMS ITALIA S.p.A. Adapter/Wandler für differentiale und unsymetrische SCSI-Schnittstelle
EP0788059A1 (de) * 1996-01-31 1997-08-06 Kabushiki Kaisha Toshiba Treiberschaltungsvorrichtung
EP1197872A2 (de) * 2000-10-06 2002-04-17 Broadcom Corporation Bus, der auf einer Flanke eines Taktsignals abtastet und auf der anderen Flanke treibt

Also Published As

Publication number Publication date
DE10224742B4 (de) 2004-07-08
US20050116740A1 (en) 2005-06-02
DE10224742A1 (de) 2004-01-08
JP3999229B2 (ja) 2007-10-31
US6970016B2 (en) 2005-11-29
AU2003232840A1 (en) 2003-12-19
JP2005534212A (ja) 2005-11-10
AU2003232840A8 (en) 2003-12-19
WO2003102786A2 (de) 2003-12-11
TW200307870A (en) 2003-12-16

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