WO2003105222A1 - Procede pour etablir le contact par raccords de composants electroniques sur un substrat isolant et module composant fabrique selon ce procede - Google Patents

Procede pour etablir le contact par raccords de composants electroniques sur un substrat isolant et module composant fabrique selon ce procede Download PDF

Info

Publication number
WO2003105222A1
WO2003105222A1 PCT/DE2003/001795 DE0301795W WO03105222A1 WO 2003105222 A1 WO2003105222 A1 WO 2003105222A1 DE 0301795 W DE0301795 W DE 0301795W WO 03105222 A1 WO03105222 A1 WO 03105222A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
dielectric layer
holes
component
connections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE2003/001795
Other languages
German (de)
English (en)
Inventor
Marcel Heerman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens Dematic AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Dematic AG filed Critical Siemens Dematic AG
Priority to AU2003240426A priority Critical patent/AU2003240426A1/en
Publication of WO2003105222A1 publication Critical patent/WO2003105222A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H05K1/185—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/10—Configurations of laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the invention relates to a method for contacting at least one electronic component with flat connection elements on an insulating substrate and a component module produced by this method.
  • EP 0782765 B1 already discloses a component module consisting of a connection substrate with polymer bumps molded onto the underside, on which a chip is arranged and contacted. There is also provision for the chip to be arranged in a recess on the underside of the substrate, various types of contacting being shown. In addition to contacting using flip-chip technology, contacting via bond wires is primarily provided there. While the flip-chip technology only allows a limited connection density, the connection technology with bond wires requires a high amount of tools, since each contact must be connected individually and the bond wires must then be provided with a protective covering.
  • WO 01/37338 A2 also discloses a method for integrating a chip within a printed circuit board, the chip being thinned on the back, then applied to a bottom layer of the printed circuit board and encased by a further layer of printed circuit board. In this layer, recesses for the conductor structure of the circuit board base layer and for the connection areas of the chip are then produced and provided with a corresponding conductor structure.
  • This method results in a relatively high structure of the circuit board layer structure.
  • the aim of the present invention is to provide a method for contacting components, in particular semiconductor chips, on a substrate and to create a module produced in this way, a space-saving design being associated with simple method steps and, in particular, no tools and method steps for contacting individual connection elements of the component are required.
  • a method for contacting at least one electronic component with flat connection elements on an insulating substrate has the following steps:
  • the substrate is three-dimensionally formed from a polymer material, at least one depression being formed on the top of the flat substrate in accordance with the dimensions of the component to be contacted; b) the component is arranged in the associated recess in such a way that it is provided with connecting elements
  • Connection side is directed upward and approximately aligned with the top of the substrate; c) the upper side of the substrate including the component is covered with a dielectric layer; d) external contact bumps made of polymer material are formed on the outer surface of the substrate or the dielectric layer; e) by means of laser irradiation, through holes (vias) are drilled through the dielectric layer to the connections of the component and, if appropriate, connection holes to the substrate; f) the upper side of the dielectric layer and the inner sides of the through holes and the connecting holes are provided with a metallization and g) the metallization is structured with the aid of laser radiation, external contacts on the external contact bumps as well as conductor tracks between the terminals elements of the component and the external contacts are formed on the external contact bumps.
  • the use according to the invention of the three-dimensional substrate, produced by injection molding or hot stamping, with a preformed depression for the component or the components, can be kept to a low height of the module obtained in this way, since the recessed arrangement of the component also means that the dielectric layer arranged above it has only a relatively small thickness must have.
  • connection elements and their conductive connection up to the external connections on the polymer bumps on the underside takes place via laser processes, namely structuring and drilling, which work with electronic masks, so that no tools and individual processes are required for the connection of individual contacts.
  • laser processes namely structuring and drilling, which work with electronic masks, so that no tools and individual processes are required for the connection of individual contacts.
  • the accuracy of laser lithography also allows a higher connection density than flip-chip technology.
  • the substrate can already be provided with a metallization both on the top and bottom and in through holes before the component is applied, with internal connection elements on the top side, external connection elements on the polymer bumps on the underside and connecting conductor tracks from the internal connections via the through holes to already by laser structuring the external connections.
  • contact holes to the connection elements of the component and connection holes to the internal connections are drilled, and corresponding conductor tracks are only structured on the upper side of the substrate or the dielectric layer.
  • connection holes are made from the top to the connection elements of the component as in the previous case, but in addition the connection holes are produced as through holes through the dielectric layer and the original substrate down to its underside, so that a subsequent metallization of the top and bottom of the
  • Composite body at the same time electrical connections are generated from the top through the through holes to the bottom of the substrate and to the external connections on the polymer bumps.
  • the individual conductor tracks are separated from one another by structuring the metallization on the top and on the bottom.
  • two foils with different melting points are used, a first foil with a high melting point being provided by embossing with one or more recesses for corresponding components and then being fitted with these components. Another film with a lower melting point is then applied to the component side of the first film and connected to it. Another embossing process forms polymer bumps on this second film as supports for external connections.
  • the composite body is then provided by laser drilling with contact holes to the connection elements of the components and with connection holes between the top and bottom of the composite body; By metallizing the composite body and then structuring the top and bottom, as in the previous case, conductor tracks are produced between the connection elements of the components and the external connections on the polymer bumps.
  • a component module produced by the method according to the invention accordingly has a three-dimensional substrate formed from polymer material, a dielectric layer arranged on the substrate and at least one electronic component arranged between the substrate and the dielectric layer and the following features: the substrate has at least one recess on its upper side, in which the component is positioned such that its connections point upwards in the direction of the dielectric layer, the dielectric layer in each case has through holes extending from the connections of the component to its upper side, On the underside of the substrate or on the top of the dielectric layer, external contact bumps made of polymer material are formed and provided with external contacts in the form of a metal coating, and on the upper side of the dielectric layer there is a conductor track structure which provides conductive connections to the connections of the component via the through holes and to the external contacts.
  • the external contact bumps can be arranged on the underside of the substrate; in this case, the conductive connections go from the top of the dielectric layer via through holes in the dielectric layer and in the substrate to the external contacts. Depending on the manufacturing process used, the connection can be made through a via through both layers; However, it is also possible to provide separate through holes in the dielectric layer and in the substrate, which are then connected to one another via a metallic layer on the top of the substrate.
  • the substrate and the dielectric layer can be formed by two superimposed foils, the first foil forming the substrate first being deformed in order to form depressions for one or more components, the external contact bumps being able to be formed on the underside at the same time.
  • the second film is then placed on and connected to the first, the second film then being used as the dielectric layer Through holes can be created.
  • the external contact bumps can also be embossed on the second film, in which case the first film has no bumps.
  • the second film must have a lower melting point than the first, so that the shape of the first film is not changed when the second film is embossed.
  • FIGS. 2A to 2D a second embodiment of the invention with a component module shown in multiple process stages
  • FIGS. 3A to 3D show a third embodiment of the invention with a module formed from two films in several process stages and
  • 4A to 4C show a fourth embodiment of the invention with a module formed from two films in different stages of the manufacturing process.
  • FIGS. 1A to 1D The production of a component module is shown in FIGS. 1A to 1D, wherein a substrate 1 is first produced three-dimensionally from polymer material. This can be produced, for example, by injection molding or hot stamping. Polymer bumps 2 are formed on this substrate during the shaping on the underside, while at least one recess 3 for receiving an electronic component, for example a semiconductor chip, is formed in the top. Through holes 4 are also formed between the top and bottom of the substrate.
  • the substrate 1 is provided both on the underside and on the top and in the through holes 4 with a metal layer 5, which is already structured using conventional methods, such as laser structuring and / or etching technology, so that on the bumps 2 each have external contacts 6, conductor tracks 7 on the underside of the substrate, conductor tracks 8 on the top of the substrate and in each case through conductors 9 in the through holes 4.
  • the through holes 4 are then filled with a filling material, which can be metallic or insulating.
  • a component 10 is inserted into the recess 3 in such a way that its connections 11 point upwards. These connections 11 are thus essentially aligned with the upper side of the substrate 1 or the conductor track structure 8 on this upper side.
  • the component for example a semiconductor chip, is fixed in the depression.
  • a dielectric layer is applied to the top of the substrate 1
  • This dielectric layer 13 applied. This can, for example, be laminated on in the form of a film. However, it is also possible to produce this dielectric layer 13 in a spraying process, in an injection molding process or in some other way.
  • Through holes are then produced in the dielectric layer 13 from the top by laser drilling.
  • the respective laser irradiation is indicated in FIG. IC with the arrows 14.
  • Through holes 15 and 15a are produced in each case to the connections 11 of the component 10 and at other points to internal contacts 8a of the conductor tracks 8 on the upper side of the substrate 1. These through holes are shown in Figure 1D. It is further shown that a further metallization layer 16 is deposited on the top side of the dielectric layer 13, which also covers the walls of the through holes 15 and 15a and the connections 11 of the component contacted.
  • This metal layer 16 is further structured by means of laser beams 17, so that a conductor track structure is created which produces electrical connections from the connections 11 via the through holes 15 to the conductor tracks 8 and via the through holes 15a and the through conductors 9 to the external contacts 6.
  • the conductor track structure 16 on the upper side of the dielectric layer 13 is finally covered with an insulating layer 18, so that the module produced in this way can be processed in a protected manner.
  • FIGS. 2A to 2D A modified embodiment of the invention is shown in FIGS. 2A to 2D.
  • a substrate 21 is shaped in the same way as in the previous example and provided with external contact bumps 22 on its underside and a recess 23 in its top.
  • This substrate 21 initially has no through holes as in the previous example.
  • Metallization is also not yet carried out. Rather, the depression 23 is provided with the component 10 without further coating of the substrate, which in this case also has its connections 11 towards the top.
  • FIG. 2C shows that a dielectric layer 24 is applied directly to the substrate 21 with the component 10, there being no metallization layer between the substrate 21 and the dielectric layer 24. Then, as in the previous example, through holes are generated in the dielectric layer 24 by means of laser radiation, specifically through holes 25 to the component connections 11 and through holes 26, which in this case penetrate both layers, namely the dielectric layer 24 and the substrate 21.
  • a metallization layer is then produced both on the underside of the substrate 21 and on the top side of the dielectric layer 24 and in the through holes 25 and 26 and then structured. riert, so that on the bumps 22 in each case external contacts 27 and on the top of the dielectric layer 24, on the underside of the substrate 21 and in the through holes 25 and 26, a conductor track structure 28 is generated, the electrical connections between the terminals 11 of the component and the external contacts 27 and possibly to other connections.
  • the through holes 26 are filled, as already described, and the top of the dielectric layer 24 or the conductor track structure 28 is covered with a protective insulation layer 29.
  • FIGS. 3A to 3D show how a module according to the invention can be formed by two foils.
  • a first film forms the substrate 31, while a second film forms the dielectric layer 32.
  • the substrate 31 is embossed according to FIG. 3A, with external contact bumps 33 being embossed on the underside and different flat depressions 34 and deep recesses 35 being embossed on the upper side.
  • flat components 10 are inserted and fixed with their connections 11 lying upward, as in the previous example.
  • a vertically standing component 19 is inserted into the recess 35 in such a way that one connection 19a faces the top and another connection 19b faces the bottom. In this case, as shown in FIG.
  • the component connections 11 and 19a are aligned with the upper side of the substrate 31. It would also be conceivable that the depressions 34 and 35 are less than the respective height of the component, so that the introduced ones Components protrude above the top of the substrate 31.
  • the film, which forms the dielectric layer 32 is placed on the substrate 31 and connected to it.
  • through holes are produced by means of laser beams 36, specifically through holes 37 to the component connections 11 and 19a and through holes 38, which are from the top of the dielectric layer 32 extend to the underside of the substrate 31.
  • a blind hole 39 is drilled from the underside of the substrate 31 to the connection 19b of the component 19.
  • the substrate 31 on its underside, the dielectric layer on its top and the through holes are then provided with an all-round metallization 40, which in turn is then structured by means of laser beams 41. That way then
  • FIGS. 4A to 4C show a further modified example for producing a component module from two foils.
  • a first film serves as substrate 31, on which a second film as dielectric layer 32 is placed.
  • the depressions 34 and 35 for the various components are embossed on the substrate 31, but initially no bumps 33 on the underside.
  • the depressions 34 and 35 are shown in this example according to FIG. 4A in such a way that the components are not completely accommodated in the depressions.
  • the components 10 and 19 are thus partially embossed into the dielectric layer 32.
  • bumps 43 are also embossed on the upper side of the dielectric layer.
  • additional component connections 19b can also be contacted via the blind holes 39, which are then connected via the conductor structure on the underside of the substrate 31 and the through holes 38 to the conductor structure on the top of the dielectric layer 32 and an external contact 42 ,
  • the conductor tracks can be covered and protected in the usual way by means of an insulating coating (not shown in FIG. 4C).
  • an electronic module can be created in this way, one or more components being arranged and fixed between two polymer films, preferably made of LCP. At least one of the foils is deformed by hot stamping before and / or after the union, and external contact bumps are formed on one of the foils by means of hot stamping.
  • the component connections are uncovered by means of laser radiation, and all electrical connections are created in a mass process using flat metallization and laser structuring.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention concerne la fabrication d'un module composant, selon laquelle un ou plusieurs composants (10) électroniques sont placés entre un substrat (1) et une couche diélectrique (13), dans un évidement (3) du substrat, de façon telle que les raccords (11) du composant sont orientés vers le haut en direction de la couche diélectrique. Le contact est réalisé au moyen d'un réseau de circuits imprimés (16) disposé sur la face supérieure de la couche diélectrique. Ce réseau est en contact par des orifices de passage d'une part, avec les raccords (11) du composant et d'autre part, avec des raccords extérieurs (6) sur des bosses polymère (2) lesquelles sont façonnées sur la face inférieure du substrat (1) ou sur la face supérieure de la couche diélectrique.
PCT/DE2003/001795 2002-06-07 2003-06-06 Procede pour etablir le contact par raccords de composants electroniques sur un substrat isolant et module composant fabrique selon ce procede Ceased WO2003105222A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003240426A AU2003240426A1 (en) 2002-06-07 2003-06-06 Method for contact bonding electronic components on an insulating substrate and component module produced according to said method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10225431A DE10225431A1 (de) 2002-06-07 2002-06-07 Verfahren zur Anschlußkontaktierung von elektronischen Bauelementen auf einem isolierenden Substrat und nach dem Verfahren hergestelltes Bauelement-Modul
DE10225431.1 2002-06-07

Publications (1)

Publication Number Publication Date
WO2003105222A1 true WO2003105222A1 (fr) 2003-12-18

Family

ID=29718897

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2003/001795 Ceased WO2003105222A1 (fr) 2002-06-07 2003-06-06 Procede pour etablir le contact par raccords de composants electroniques sur un substrat isolant et module composant fabrique selon ce procede

Country Status (3)

Country Link
AU (1) AU2003240426A1 (fr)
DE (1) DE10225431A1 (fr)
WO (1) WO2003105222A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102752958A (zh) * 2005-10-14 2012-10-24 揖斐电株式会社 多层印刷线路板
US8320135B2 (en) 2005-12-16 2012-11-27 Ibiden Co., Ltd. Multilayer printed circuit board
CN103096635A (zh) * 2011-10-31 2013-05-08 健鼎（无锡）电子有限公司 将磁性元件埋置基板内的方法
EP2596689A4 (fr) * 2010-07-23 2017-07-26 Tessera, Inc. Éléments microélectroniques à planarisation post-montage

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10343053A1 (de) * 2003-09-16 2005-04-07 Siemens Ag Elektronisches Bauelement und Anordnung mit einem elektronischen Bauelement
EP1622435A1 (fr) * 2004-07-28 2006-02-01 ATOTECH Deutschland GmbH Méthode de fabrication d'un dispositif par des techniques d'écriture directe
DE102004061907A1 (de) * 2004-12-22 2006-07-13 Siemens Ag Halbleitermodul mit geringer thermischer Belastung

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03297152A (ja) * 1990-04-16 1991-12-27 Hitachi Chem Co Ltd 半導体装置の製造法
EP0971405A2 (fr) * 1994-09-23 2000-01-12 Siemens S.A. Procédé pour la fabrication d'un substrat por un "stud grid array" en polymère
WO2002011201A2 (fr) * 2000-07-31 2002-02-07 Siemens Dematic Ag Procede et dispositif de production de substrats de connexion de composants electroniques
WO2002045162A2 (fr) * 2000-11-29 2002-06-06 Siemens Aktiengesellschaft Support intermediaire pour un module semi-conducteur, module semi-conducteur produit en utilisant un tel support intermediaire et procede pour la production d'un tel support intermediaire
WO2002045163A2 (fr) * 2000-11-29 2002-06-06 Siemens Dematic Ag Procede pour produire des modules semi-conducteurs et module produit selon ce procede

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5306670A (en) * 1993-02-09 1994-04-26 Texas Instruments Incorporated Multi-chip integrated circuit module and method for fabrication thereof
US5745984A (en) * 1995-07-10 1998-05-05 Martin Marietta Corporation Method for making an electronic module
JP2842378B2 (ja) * 1996-05-31 1999-01-06 日本電気株式会社 電子回路基板の高密度実装構造

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03297152A (ja) * 1990-04-16 1991-12-27 Hitachi Chem Co Ltd 半導体装置の製造法
EP0971405A2 (fr) * 1994-09-23 2000-01-12 Siemens S.A. Procédé pour la fabrication d'un substrat por un "stud grid array" en polymère
WO2002011201A2 (fr) * 2000-07-31 2002-02-07 Siemens Dematic Ag Procede et dispositif de production de substrats de connexion de composants electroniques
WO2002045162A2 (fr) * 2000-11-29 2002-06-06 Siemens Aktiengesellschaft Support intermediaire pour un module semi-conducteur, module semi-conducteur produit en utilisant un tel support intermediaire et procede pour la production d'un tel support intermediaire
WO2002045163A2 (fr) * 2000-11-29 2002-06-06 Siemens Dematic Ag Procede pour produire des modules semi-conducteurs et module produit selon ce procede

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 016, no. 138 (E - 1186) 7 April 1992 (1992-04-07) *

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102752958A (zh) * 2005-10-14 2012-10-24 揖斐电株式会社 多层印刷线路板
CN101288350B (zh) * 2005-10-14 2012-11-07 揖斐电株式会社 多层印刷线路板及其制造方法
US8692132B2 (en) 2005-10-14 2014-04-08 Ibiden Co., Ltd. Multilayered printed circuit board and method for manufacturing the same
US8912451B2 (en) 2005-10-14 2014-12-16 Ibiden Co., Ltd. Multilayered printed circuit board and method for manufacturing the same
US8973259B2 (en) 2005-10-14 2015-03-10 Ibiden Co., Ltd. Method for manufacturing a multilayered circuit board
US9027238B2 (en) 2005-10-14 2015-05-12 Ibiden Co., Ltd. Multilayered printed circuit board and method for manufacturing the same
US8320135B2 (en) 2005-12-16 2012-11-27 Ibiden Co., Ltd. Multilayer printed circuit board
US8705248B2 (en) 2005-12-16 2014-04-22 Ibiden Co., Ltd. Multilayer printed circuit board
EP2596689A4 (fr) * 2010-07-23 2017-07-26 Tessera, Inc. Éléments microélectroniques à planarisation post-montage
US10559494B2 (en) 2010-07-23 2020-02-11 Tessera, Inc. Microelectronic elements with post-assembly planarization
CN103096635A (zh) * 2011-10-31 2013-05-08 健鼎（无锡）电子有限公司 将磁性元件埋置基板内的方法

Also Published As

Publication number Publication date
AU2003240426A1 (en) 2003-12-22
DE10225431A1 (de) 2004-01-08

Similar Documents

Publication Publication Date Title
DE102006021959B4 (de) Leistungshalbleiterbauteil und Verfahren zu dessen Herstellung
DE10259221B4 (de) Elektronisches Bauteil mit einem Stapel aus Halbleiterchips und Verfahren zur Herstellung desselben
WO2000048249A1 (fr) Composant a semiconducteur comportant un porte-puce avec des ouvertures pour la metallisation
DE19650296A1 (de) Verfahren zum Herstellen eines Halbleiterbauelements
WO2005109499A2 (fr) Composant a semi-conducteur comportant un substrat de recablage et son procede de production
DE102018207955A1 (de) Leistungselektronisches Metall-Keramik-Modul und Leiterplattenmodul mit integriertem leistungselektronischen Metall-Keramik-Modul sowie Verfahren zu deren Herstellung
EP2452546A1 (fr) Procédé de fabrication d'une carte de circuits imprimés constituée d'au moins deux régions ainsi que carte de circuits imprimés
DE102004008135A1 (de) Halbleiterbauteil mit einem Stapel aus Halbleiterchips und Verfahren zur Herstellung desselben
DE102005043557B4 (de) Verfahren zur Herstellung eines Halbleiterbauteils mit Durchkontakten zwischen Oberseite und Rückseite
WO2004003991A2 (fr) Composant electronique encapsule dans un boitier
DE69509979T2 (de) BGA Gehäuse für integrierte Schaltungen und Verfahren zu ihrer Herstellung
DE69723801T2 (de) Herstellungsverfahren einer Kontaktgitter-Halbleiterpackung
WO2000079590A1 (fr) Ensemble electronique a points de contact souples
WO2008104324A1 (fr) Procédé d'intégration de puces dans des cavités de cartes à circuit imprimé
DE10059176C2 (de) Zwischenträger für ein Halbleitermodul, unter Verwendung eines derartigen Zwischenträgers hergestelltes Halbleitermodul sowie Verfahren zur Herstellung eines derartigen Halbleitermoduls
DE10059178A1 (de) Verfahren zur Herstellung von Halbleitermodulen sowie nach dem Verfahren hergestelltes Modul
WO2000011755A1 (fr) Dispositif d'etablissement de contact, en particulier pour l'etablissement de contact entre des composants electriques et des supports de circuit, ainsi que procede de fabrication dudit dispositif
WO2006012846A1 (fr) Element de base semi-conducteur comportant un support de connexions et une plaque intermediaire de connexions pour un empilement d'elements semi-conducteurs, et procede de fabrication associe
WO2003105222A1 (fr) Procede pour etablir le contact par raccords de composants electroniques sur un substrat isolant et module composant fabrique selon ce procede
DE102008058003A1 (de) Halbleitermodul und Verfahren zu dessen Herstellung
DE19945794C2 (de) Verfahren zum Herstellen einer Metall-Keramik-Leiterplatte mit DurchKontaktierungen
DE10333840B4 (de) Halbleiterbauteil mit einem Kunststoffgehäuse, das eine Umverdrahrungsstruktur aufweist und Verfahren zu deren Herstellung
DE3931551A1 (de) Verfahren zum herstellen eines mehrschichtigen, kupfer- und keramikschichten aufweisenden substrates
DE10223203B4 (de) Elektronisches Bauelement-Modul und Verfahren zu dessen Herstellung
EP4342267A1 (fr) Procédé de fabrication d'une carte de circuit imprimé et carte de circuit imprimé comportant au moins un composant électronique intégré

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NI NO NZ OM PH PL PT RO RU SC SD SE SG SK SL TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP