WO2004100253A3 - Elektronisches bauteil, sowie systemträger und nutzen zur herstellung desselben - Google Patents

Elektronisches bauteil, sowie systemträger und nutzen zur herstellung desselben Download PDF

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Publication number
WO2004100253A3
WO2004100253A3 PCT/DE2004/000934 DE2004000934W WO2004100253A3 WO 2004100253 A3 WO2004100253 A3 WO 2004100253A3 DE 2004000934 W DE2004000934 W DE 2004000934W WO 2004100253 A3 WO2004100253 A3 WO 2004100253A3
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WO
WIPO (PCT)
Prior art keywords
electronic component
production
well
panel
system support
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE2004/000934
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English (en)
French (fr)
Other versions
WO2004100253A2 (de
Inventor
Bernd Goller
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Infineon Technologies AG
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Infineon Technologies AG
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Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to EP04730953A priority Critical patent/EP1620890A2/de
Publication of WO2004100253A2 publication Critical patent/WO2004100253A2/de
Publication of WO2004100253A3 publication Critical patent/WO2004100253A3/de
Priority to US11/267,589 priority patent/US7795717B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H05K1/185—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H05K1/185—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
    • H05K1/186—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H05K1/187—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards manufactured by mounting on or connecting to patterned circuits before or during embedding the patterned circuits being prefabricated circuits, which are not yet attached to a permanent insulating substrate, e.g. on a temporary carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Die Erfindung betrifft ein elektronisches Bauteil (3), sowie Systemträger und Nutzen zur Herstellung desselben. Das elektronische Bauteil weist einen ersten Halbleiterchip (11) auf und einen zweiten Halbleiterchip (17), der auf einer Kunststoffmasse (13) angeordnet ist, in welche der erste Halbleiterchip (11) eingebettet ist. Die Halbleiterchips sind über Umverdrahtungslagen und Durchkontakte, die sich zwischen den Umverdrahtungslagen erstrecken, miteinander verbunden, wobei die Durchkontakte (6) an einem Übergang zu einer der Umverdrahtungslagen verbreitert ausgebildet sind.
PCT/DE2004/000934 2003-05-07 2004-05-04 Elektronisches bauteil, sowie systemträger und nutzen zur herstellung desselben Ceased WO2004100253A2 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP04730953A EP1620890A2 (de) 2003-05-07 2004-05-04 Elektronisches bauteil, sowie systemträger und nutzen zur herstellung desselben
US11/267,589 US7795717B2 (en) 2003-05-07 2005-11-07 Electronic component embedded within a plastic compound and including copper columns within the plastic compound extending between upper and lower rewiring layers, and system carrier and panel for producing an electronic component

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10320646A DE10320646A1 (de) 2003-05-07 2003-05-07 Elektronisches Bauteil, sowie Systemträger und Nutzen zur Herstellung desselben
DE10320646.9 2003-05-07

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/267,589 Continuation US7795717B2 (en) 2003-05-07 2005-11-07 Electronic component embedded within a plastic compound and including copper columns within the plastic compound extending between upper and lower rewiring layers, and system carrier and panel for producing an electronic component

Publications (2)

Publication Number Publication Date
WO2004100253A2 WO2004100253A2 (de) 2004-11-18
WO2004100253A3 true WO2004100253A3 (de) 2005-09-29

Family

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PCT/DE2004/000934 Ceased WO2004100253A2 (de) 2003-05-07 2004-05-04 Elektronisches bauteil, sowie systemträger und nutzen zur herstellung desselben

Country Status (4)

Country Link
US (1) US7795717B2 (de)
EP (1) EP1620890A2 (de)
DE (1) DE10320646A1 (de)
WO (1) WO2004100253A2 (de)

Families Citing this family (83)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10320646A1 (de) 2003-05-07 2004-09-16 Infineon Technologies Ag Elektronisches Bauteil, sowie Systemträger und Nutzen zur Herstellung desselben
DE10334577B3 (de) * 2003-07-28 2005-02-10 Infineon Technologies Ag Verfahren zum Aufbringen einer Umverdrahtung auf einen Nutzen unter Kompensation von Positionsfehlern und Halbleiterchips in Bauteilpositionen des Nutzens
DE102004022884B4 (de) * 2004-05-06 2007-07-19 Infineon Technologies Ag Halbleiterbauteil mit einem Umverdrahtungssubstrat und Verfahren zur Herstellung desselben
CN101053079A (zh) 2004-11-03 2007-10-10 德塞拉股份有限公司 堆叠式封装的改进
DE102005006280B4 (de) * 2005-02-10 2006-11-16 Infineon Technologies Ag Halbleiterbauteil mit einem Durchkontakt durch eine Gehäusemasse und Verfahren zur Herstellung desselben
DE102005043557B4 (de) * 2005-09-12 2007-03-01 Infineon Technologies Ag Verfahren zur Herstellung eines Halbleiterbauteils mit Durchkontakten zwischen Oberseite und Rückseite
DE102005046737B4 (de) * 2005-09-29 2009-07-02 Infineon Technologies Ag Nutzen zur Herstellung eines elektronischen Bauteils, Bauteil mit Chip-Durchkontakten und Verfahren
EP1949441A2 (de) * 2005-11-11 2008-07-30 Koninklijke Philips Electronics N.V. Chip-baugruppe und herstellungsverfahren dafür
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
DE102006001429A1 (de) * 2006-01-10 2007-03-22 Infineon Technologies Ag Nutzen und Halbleiterbauteil aus einer Verbundplatte mit Halbleiterchips und Kunststoffgehäusemasse sowie Verfahren zur Herstellung desselben
DE102006037538B4 (de) * 2006-08-10 2016-03-10 Infineon Technologies Ag Elektronisches Bauteil, elektronischer Bauteilstapel und Verfahren zu deren Herstellung sowie Verwendung einer Kügelchenplatziermaschine zur Durchführung eines Verfahrens zum Herstellen eines elektronischen Bauteils bzw. Bauteilstapels
US8174119B2 (en) * 2006-11-10 2012-05-08 Stats Chippac, Ltd. Semiconductor package with embedded die
CN101690434B (zh) * 2007-06-26 2011-08-17 株式会社村田制作所 元器件内置基板的制造方法
US8829663B2 (en) * 2007-07-02 2014-09-09 Infineon Technologies Ag Stackable semiconductor package with encapsulant and electrically conductive feed-through
US7838420B2 (en) 2007-08-29 2010-11-23 Freescale Semiconductor, Inc. Method for forming a packaged semiconductor device
US7855439B2 (en) * 2008-08-28 2010-12-21 Fairchild Semiconductor Corporation Molded ultra thin semiconductor die packages, systems using the same, and methods of making the same
US8093711B2 (en) * 2009-02-02 2012-01-10 Infineon Technologies Ag Semiconductor device
US8169070B2 (en) * 2009-05-15 2012-05-01 Infineon Technologies Ag Semiconductor device
US9922955B2 (en) * 2010-03-04 2018-03-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming package-on-package structure electrically interconnected through TSV in WLCSP
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8895440B2 (en) * 2010-08-06 2014-11-25 Stats Chippac, Ltd. Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV
KR101075241B1 (ko) 2010-11-15 2011-11-01 테세라, 인코포레이티드 유전체 부재에 단자를 구비하는 마이크로전자 패키지
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US9142502B2 (en) 2011-08-31 2015-09-22 Zhiwei Gong Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits
US8916421B2 (en) * 2011-08-31 2014-12-23 Freescale Semiconductor, Inc. Semiconductor device packaging having pre-encapsulation through via formation using lead frames with attached signal conduits
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US8597983B2 (en) 2011-11-18 2013-12-03 Freescale Semiconductor, Inc. Semiconductor device packaging having substrate with pre-encapsulation through via formation
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
KR101985236B1 (ko) 2012-07-10 2019-06-03 삼성전자주식회사 멀티-칩 패키지 및 그의 제조 방법
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
DE102012108627B4 (de) * 2012-09-14 2021-06-10 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Optoelektronische Halbleitervorrichtung und Trägerverbund
US9559039B2 (en) * 2012-09-17 2017-01-31 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using substrate having base and conductive posts to form vertical interconnect structure in embedded die package
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9870946B2 (en) 2013-12-31 2018-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and method of forming same
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9343434B2 (en) 2014-02-27 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Laser marking in packages
US9589900B2 (en) 2014-02-27 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Metal pad for laser marking
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9666522B2 (en) 2014-05-29 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment mark design for packages
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9852998B2 (en) 2014-05-30 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Ring structures in device die
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
TW201826893A (zh) * 2017-01-11 2018-07-16 思鷺科技股份有限公司 封裝結構及封裝結構的製作方法
TWI591762B (zh) * 2014-06-30 2017-07-11 恆勁科技股份有限公司 封裝裝置及其製作方法
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9530749B2 (en) 2015-04-28 2016-12-27 Invensas Corporation Coupling of side surface contacts to a circuit platform
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9831155B2 (en) * 2016-03-11 2017-11-28 Nanya Technology Corporation Chip package having tilted through silicon via
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US20190164875A1 (en) * 2017-11-27 2019-05-30 Asm Technology Singapore Pte Ltd Premolded substrate for mounting a semiconductor die and a method of fabrication thereof
US11114407B2 (en) * 2018-06-15 2021-09-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package and manufacturing method thereof
DE102020207279A1 (de) 2020-06-10 2021-12-16 Vitesco Technologies Germany Gmbh Leiterplatte mit einem eingebetteten Halbleiterbauelement, Verfahren zum Herstellen einer Leiterplatte

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6054772A (en) * 1998-04-29 2000-04-25 National Semiconductor Corporation Chip sized package
EP1154474A1 (de) * 1999-08-23 2001-11-14 Rohm Co., Ltd. Halbleiter und seine herstellung
DE10224124A1 (de) * 2002-05-29 2003-12-18 Infineon Technologies Ag Elektronisches Bauteil mit äußeren Flächenkontakten und Verfahren zu seiner Herstellung

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US6038133A (en) * 1997-11-25 2000-03-14 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method for producing the same
EP0971409A1 (de) * 1998-07-07 2000-01-12 Interuniversitair Micro-Elektronica Centrum Vzw Herstellungsverfahren von Kupfer enthaltenden Metallstützen
US6734534B1 (en) * 2000-08-16 2004-05-11 Intel Corporation Microelectronic substrate with integrated devices
JP2002158312A (ja) * 2000-11-17 2002-05-31 Oki Electric Ind Co Ltd ３次元実装用半導体パッケージ、その製造方法、および半導体装置
JP3798620B2 (ja) * 2000-12-04 2006-07-19 富士通株式会社 半導体装置の製造方法
DE10137184B4 (de) * 2001-07-31 2007-09-06 Infineon Technologies Ag Verfahren zur Herstellung eines elektronischen Bauteils mit einem Kuststoffgehäuse und elektronisches Bauteil
TW550997B (en) * 2001-10-18 2003-09-01 Matsushita Electric Industrial Co Ltd Module with built-in components and the manufacturing method thereof
TW200302685A (en) * 2002-01-23 2003-08-01 Matsushita Electric Industrial Co Ltd Circuit component built-in module and method of manufacturing the same
DE10320646A1 (de) 2003-05-07 2004-09-16 Infineon Technologies Ag Elektronisches Bauteil, sowie Systemträger und Nutzen zur Herstellung desselben

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6054772A (en) * 1998-04-29 2000-04-25 National Semiconductor Corporation Chip sized package
EP1154474A1 (de) * 1999-08-23 2001-11-14 Rohm Co., Ltd. Halbleiter und seine herstellung
DE10224124A1 (de) * 2002-05-29 2003-12-18 Infineon Technologies Ag Elektronisches Bauteil mit äußeren Flächenkontakten und Verfahren zu seiner Herstellung

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WO2004100253A2 (de) 2004-11-18
US20060087044A1 (en) 2006-04-27

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