WO2004105132A1 - Connexion electrique pour puce microelectronique et son procede de fabrication - Google Patents

Connexion electrique pour puce microelectronique et son procede de fabrication Download PDF

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Publication number
WO2004105132A1
WO2004105132A1 PCT/IB2004/001596 IB2004001596W WO2004105132A1 WO 2004105132 A1 WO2004105132 A1 WO 2004105132A1 IB 2004001596 W IB2004001596 W IB 2004001596W WO 2004105132 A1 WO2004105132 A1 WO 2004105132A1
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WO
WIPO (PCT)
Prior art keywords
layer
microelectronic chip
manufacturing
connection
additional layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2004/001596
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English (en)
Inventor
Denis Groeninck
Béatrice BONVALOT
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Axalto SA
Axalto Inc
Original Assignee
Axalto SA
Schlumberger Malco Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Axalto SA, Schlumberger Malco Inc filed Critical Axalto SA
Publication of WO2004105132A1 publication Critical patent/WO2004105132A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07511—Treating the bonding area before connecting, e.g. by applying flux or cleaning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07531—Techniques
    • H10W72/07532—Compression bonding, e.g. thermocompression bonding
    • H10W72/07533—Ultrasonic bonding, e.g. thermosonic bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5434—Dispositions of bond wires the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5525—Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/28—Configurations of stacked chips the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the invention relates to the electrical connection of microelectronic components, in particular the electrical connection of one or several microelectronic chips.
  • the Invention also relates to a method for manufacturing the electrical connection of microelectronic chip, in particular when using wire bonding process.
  • connection pads are the elements on a microelectronic chip which enable to connect the integrated circuit to other electronic components (for example other microelectronic chip) or to the microelectronic chip package (for example microelectronic module) or to the electronic boards.
  • the connection pad size has evolved as follows: - 200 x 100 ⁇ m in the 80's.
  • Figure 1 illustrates the electrical connection of the pads of a microelectronic chip to the metallic contact of the substrate by using wire bonding process (also called ball bonding process).
  • a ball 1 of metallic material is formed and thermo-sonic bonded on the connection pad 2 of the chip 3 as shown in the details view of Figure 2.A.
  • the microelectronic chip 3 is placed on the substrate 5, the active face 9 of the microelectronic chip 3 being positioned upside. The face opposite to the active face 9 is glued via a glue layer 7 on the substrate 5.
  • the chip connection pad 2 is wired to the metal area 4 on substrate 5.
  • a stitch 6 is bonded on the metal area 4.
  • the electrical connection between the chip connection pad 2 and substrate metal area 4 is made by a metal wire 8.
  • the metal wire can be made of gold, palladium, or copper, etc...
  • the standard wire bonding process requires the use of a metal wire having a diameter ranging from 15 /m to 35 ⁇ m. The wire diameter depends in particular on wire length, electrical power, wire loop height.
  • Ball bonding process requires forming first a ball which measures :
  • a wire bonding machine has a global accuracy of about +/- 5 ⁇ m (X, Y, Z axis accuracy).
  • the minimum required area to bond has to measure from 55 ⁇ m x 55 ⁇ (for 15 /vm of wire diameter), 85 ⁇ m x 85 ⁇ m (for 25 /m of wire diameter) to 115 /m x 115 ⁇ m
  • connection pad size As a consequence, with reduced connection pad size and usual wire diameter, there is no ball bonding size reduction and the ball takes a surface greater than the connection pad surface as shown in the details view of Figure 2.B.
  • the microelectronic chip circuit is generally damaged during the bonding process (for example cracks 10 are formed in the active surface as shown on Figure 2.B).
  • One goal of the invention is to continue using the standard wire bonding process in the frame of narrow connection pads with only minor modification. Another goal of the invention is to keep using the same manufacturing equipment for performing the electrical connection.
  • connection pads before the connection ball and the wire are bonded on the connection pad (yet the metallic layer).
  • the present invention relates to a method of manufacturing an electrical connection for a microelectronic chip, the microelectronic chip comprises at least one connection pad of reduced size, wherein the method of manufacturing comprises the steps of: - adding an additional layer on the at least one connection pad, - bonding a wire on the additional layer.
  • the step of bonding a wire on the additional layer comprises the further step of forming a ball of metallic material on the additional layer.
  • the invention also relates to an electrical connection for a microelectronic chip obtained with the manufacturing method of the invention.
  • the electrical connection according to the invention comprises at least one connection pad and an additional layer added on the connection pad, the additional layer having a thickness so as to protect the active face of the chip from the connection ball formed and bonded on the additional layer.
  • the wire is thermo-sonic bonded on the additional layer.
  • the additional layer comprises a first sub-layer and a second sub-layer, the first sub-layer being attached to the connection pad, at least one of the sub-layers is made of a metallic material.
  • the layers can be deposed by electro-less metal deposition process (plating) or by electrolyze metal deposition process.
  • the additional layer has a thickness so as to protect an active surface of the chip from the ball formed on the additional layer.
  • the thickness of the additional layer may vary from 5 ⁇ m to 10 ⁇ m.
  • the metallic material may be Ni, Cu, Au, Pd, Pt or Ag.
  • the first sub-layer can be made of Ni, while the second sub-layer can be made of Au, Pd, Pt or Ag.
  • the deposition of one or several metallic' layers (Nickel, Copper, Gold, Palladium%) compatible with thermo-sonic bonding process, with various layer thicknesses is easy to perform.
  • the conventional/standard wire bonding process the one used with standard pad size
  • the standard wire bonding process can be used for pad size inferior to two times the wire diameter.
  • the electro-less plating on wafers is a well known and inexpensive process.
  • Figure 1 schematically illustrates the electrical connection of the pads of a microelectronic chip to the metallic contact of the substrate by using wire bonding process according to the prior art
  • Figures 2.A and 2.B schematically illustrate in details the effect of the pad size regarding the ball connection step of the wire bonding process according to the prior art
  • Figure 3 schematically illustrates in details a modified connection pad according to a first embodiment of the invention
  • Figure 4 schematically illustrates in details a modified connection pad according to a second embodiment of the invention
  • Figures 5.A and 5.B show respectively a cross-section view and a top view of a microelectronic chip, after a first step of the method of manufacturing the connection according to the rerouting connection alternative of the invention
  • Figures 6.A and 6.B show respectively a cross-section view and a top view of a microelectronic chip, after a second step of the method of manufacturing the connection according to the rerouting connection alternative of the invention
  • Figures 7.A and 7.B show respectively a cross-section view and a top view of a microelectronic chip, after a third step of the method of manufacturing the connection according to the rerouting connection alternative of the invention
  • Figures 8.A, 8.B and 8.C show cross-section views of a microelectronic chip according to three variants of another embodiment of the invention.
  • FIGs 3 and 4 are a detailed view of a modified connection pad according to the invention. For sake of clarity, the other elements of a whole microelectronic component as shown on Figure 1 are omitted.
  • the microelectronic chip 3 comprises an active face 9 positioned upside.
  • the active face comprises the active circuit, for example memories, processor units and interconnection buses.
  • the microelectronic chip 3 also comprises a connection pad 2 for connecting the active circuits of the active face 9 to the external "world", namely other chips or other components.
  • an additional layer 11 is added on the connection pad 2.
  • the additional layer is obtained through a growth of metallic material. This growth may be perform by known electro-less or electrolyze process.
  • the additional layer 11 has a thickness H.
  • the metallic material can be Ni, Cu, Au, Pd, Pt or Ag.
  • the additional layer 11 added on the connection pad 2 comprises a first sub-layer 11 ' and a second sub-layer 11 ".
  • the first sub-layer 11 ' is attached to the connection pad 2.
  • the second sub-layer 11 " is attached to the first sub-layer 11 '.
  • the layers can be obtained through a growth of metallic material by known electro- less metal deposition process (plating) or by electrolyze metal deposition process.
  • the first sub-layer 11' and the second sub-layer 11 " have a total thickness H'.
  • the thickness H' can be made substantially identical to the additional layer thickness H.
  • the first sub-layer 11 ' can be made of Ni.
  • the first sub-layer 11 ' can have a thickness of some ⁇ m.
  • the second sub-layer 11 " can be made of Au, Pd, Pt or Ag.
  • the second sub-layer 11 " can be a thin layer acting as a protection layer with regards to oxidation. This second sub-layer 11 " enables to perform a better wire bonding.
  • a ball 1 of metallic material is formed and thermo-sonic bonded on the top surface of the layer.
  • a ball 1 is respectively bonded on the additional layer 11 of the first embodiment, and on the second sub-layer 11 " of the second embodiment.
  • the thickness H or H' is chosen so as to protect the active surface 9 of the chip from the ball formation and bonding.
  • the thickness may vary from 5 ⁇ m to 10 ⁇ m. However, higher thickness and lower thickness can be implemented as soon as the active surface does not come in contact with the ball 1.
  • Figures 5.A to 7.B schematically illustrate the method of manufacturing the electrical connection according to an alternative of the invention. This alternative consists in adding at least one additional layer on the connection pad and creating rerouting connection pad.
  • Figure 5.A is a cross-section view along line AA of Figure 5.B.
  • FIG.B is a top view of a microelectronic chip.
  • a microelectronic chip is obtained.
  • the microelectronic chip 13 comprises an active face.
  • the active face comprises the active circuit and connection pads 2A and 2B for connecting the active circuit of the active face to external components.
  • the active face is protected by a passivation layer 15 of soft or hard like organic or oxide material, while letting an opening for each connection pad.
  • Figure 6.A - left side is a cross-section view along line AA of Figure 6.B.
  • Figure 6.A - right side is a cross-section view along line BB of Figure 6.B.
  • Figure 6.B is a top view of a microelectronic chip.
  • an additional layer is added on the connection pad 2A and on some part of the passivation layer 15.
  • the additional layer constitutes a rerouting pad 11 A.
  • the rerouting pad has a first part with a width substantially equal to the initial pad 2A size and a second part which constitutes an enlarged pad.
  • Another additional layer constitutes a rerouting pad 11 B.
  • Both rerouting pads 11A and 11 B are obtained for example by known sputtering or metal evaporation process.
  • the rerouting pads 11A and 11 B define new paths and new connection pad areas which are compatible in term of surface with the wire bonding process.
  • the additional layer can be constituted of two sub-layers (not shown) as previously described.
  • a first sub-layer of some ⁇ (for example 5 ⁇ m) is covered by a thin second sub-layer (for example 0,2 ⁇ m).
  • a passivation layer can be coated on the whole surface for protecting the under-layer while letting an opening over each new pad area.
  • the passivation layer can be coated by known spin coating, sputtering or pressure enhanced chemical vapor deposition process.
  • Figure 7.A - left side is a cross-section view along line AA of Figure 7.B.
  • Figure 7.A - right side is a cross-section view along line BB of Figure 7.B.
  • Figure 7.B is a top view of a microelectronic chip.
  • a ball 1A and 1B of metallic material is formed and thermo-sonic bonded on the top surface of the rerouting pads 11 A and 11 B respectively.
  • Figures 8.A, 8.B and 8.C are cross-section views of a complex microelectronic chip according to another embodiment of the invention.
  • an additional microelectronic chip 23 or 33 is stacked onto the microelectronic chip 3.
  • Figure 8.A shows the connection to a first microelectronic chip 3.
  • Figure 8.B shows the connection to a second microelectronic chip 23.
  • Figure 8.C shows the stacking of an additional microelectronic chip 33 of smaller dimension than the first microelectronic chip 3 with a rerouting pad 2D.
  • a complex microelectronic chip may comprise a combination of connections (not shown) to a first microelectronic chip 3 and to the second microelectronic chip 23 and/or 33.
  • the microelectronic chip 3 comprises an active face 9 positioned upside.
  • the active face comprises the active circuit.
  • the microelectronic chip 3 also comprises a connection pad 2 for connecting the active circuits of the active face 9 to the external chips or external components.
  • the complex microelectronic chip comprises an additional die or wafer 23 coupled to the microelectronic chip 3 via an interface layer 21.
  • the interface layer can be for example an organic glue.
  • a cavity 22 is etched into the additional die 23 so as to open the way to the connection pad 2.
  • an additional layer 11 is added on the connection pad 2.
  • the additional layer is obtained through a growth of metallic material. This growth may be perform by known electro-less or electrolyze process.
  • the metallic material can be Ni, Cu, Au, Pd, Pt or Ag.
  • a ball 1 of metallic material is formed and thermo-sonic bonded on the top surface of the layer. After the ball formation and bonding step, the standard wire 8 bonding process continues as usual.
  • a passivation layer (not shown) may be added so as to avoid possible electrical contact between the die 23 and the connection during the growth (short circuit).
  • the first microelectronic chip 3 comprises an active face 9 positioned upside, while the second microelectronic chip 23 comprises an active face 29 positioned downside.
  • the active face of both circuits comprises the active circuit.
  • the microelectronic chip 23 comprises a connection pad 2C for connecting the active circuits of the active face 29 to the external chips or external components.
  • the first microelectronic chip 3 is coupled to the second microelectronic chip 23 via an interface layer 21.
  • the interface layer 21 is made for example of an organic glue.
  • a cavity 22 is etched into the second microelectronic chip 23 so as to open the way to the connection pad 2C.
  • connection pad 2C An additional layer 11 is added on the connection pad 2C.
  • the additional layer is obtained through a growth of metallic material (growth is made via electro-less or electrolyze process). After the layer deposition, a ball 1 of metallic material is formed and thermo-sonic bonded on the top surface of the layer. After the ball formation and bonding step, the standard wire 8 bonding process continues as usual.
  • a passivation layer (not shown) may be added so as to avoid possible electrical contact between the microelectronic chip 23 and the connection during the growth (short circuit).
  • the invention enables to make contact to deep active surface or underneath layer, in particular from the back side of the chip. Also, such complex electrical contact can be made with standard manufacturing equipment.
  • the first microelectronic chip 3 comprises an active face 9 positioned upside, while a second microelectronic chip of smaller size 33 comprises an active face 39 positioned downside.
  • the active face of both circuits comprises the active circuit.
  • the microelectronic chip 33 comprises a rerouting connection pad 2D for connecting the active circuits of the active face 39 to the external chips or external components.
  • the first microelectronic chip 3 is coupled to the second microelectronic chip 33 via an interface layer 21.
  • the interface layer 21 is made for example of an organic glue.
  • the connection pad 2D constitutes a new connection path that extends outwards of the area where the first and second microelectronic chip are coupled together.
  • the rerouting connection pad 2D defines a new connection pad area above the first microelectronic chip 3 enabling to connect the active face 39 of the second microelectronic chip of smaller size 33.
  • An additional layer 11 is added on the connection pad 2D.
  • the additional layer is obtained through a growth of metallic material (growth is made via electro-less or electrolyze process).
  • a ball 1 of metallic material is formed and thermo-sonic bonded on the top surface of the layer.
  • the standard wire 8 bonding process continues as usual.
  • a passivation layer (not shown) may be added so as to avoid possible electrical contact between the microelectronic chip 33 and the connection during the growth (short circuit).
  • the invention enables to make contact to complex chip structure while avoiding any damaging during the wire bonding connection process.
  • a complex microelectronic chip combining the connections to the active face of respectively the first microelectronic chip and the second microelectronic as described in relation with Figure 8.A, 8.B and 8.C can also be implemented.
  • the additional layer 11 can be made of two sub-layers as described in the second embodiment here above.

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Abstract

Connexion électrique pour puce microélectronique et son procédé de fabrication. Dans un procédé de fabrication d'une connexion électrique pour une puce microélectronique, cette dernière (3, 13, 23, 33) comporte au moins une plage de connexion de taille réduite (2, 2A, 2B, 2C, 2D) et le procédé comprend les étapes consistant à ajouter une couche supplémentaire (11, 11',11', 11A, 11B) à la ou aux plages de connexion et à souder un fil métallique (8) à ladite couche supplémentaire.
PCT/IB2004/001596 2003-05-20 2004-05-18 Connexion electrique pour puce microelectronique et son procede de fabrication Ceased WO2004105132A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03291188 2003-05-20
EP03291188.5 2003-05-20

Publications (1)

Publication Number Publication Date
WO2004105132A1 true WO2004105132A1 (fr) 2004-12-02

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016202539A1 (fr) * 2015-06-19 2016-12-22 Danfoss Silicon Power Gmbh Procédé de production d'une face de contact métallique à l'aide d'un corps métallique mis en forme supporté sur un côté, d'un semi-conducteur de puissance ayant la face de contact métallique et d'un écran de liaison pour produire la face de contact métallique

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0271110A2 (fr) * 1986-12-12 1988-06-15 Kabushiki Kaisha Toshiba Dispositif semi-conducteur comprenant une plage d'électrode
US4908685A (en) * 1985-05-10 1990-03-13 Asahi Kasei Kogyo Kabushiki Kaisha Magnetoelectric transducer
US6144100A (en) * 1997-06-05 2000-11-07 Texas Instruments Incorporated Integrated circuit with bonding layer over active circuitry
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EP0271110A2 (fr) * 1986-12-12 1988-06-15 Kabushiki Kaisha Toshiba Dispositif semi-conducteur comprenant une plage d'électrode
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US20030049882A1 (en) * 2001-08-29 2003-03-13 Yin Leng Nam Wire bonded microelectronic device assemblies and methods of manufacturing same

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