WO2005013318A3 - Procede d’obtention d’une couche mince de qualite accrue par co-implantation et recuit thermique - Google Patents
Procede d’obtention d’une couche mince de qualite accrue par co-implantation et recuit thermique Download PDFInfo
- Publication number
- WO2005013318A3 WO2005013318A3 PCT/FR2004/002038 FR2004002038W WO2005013318A3 WO 2005013318 A3 WO2005013318 A3 WO 2005013318A3 FR 2004002038 W FR2004002038 W FR 2004002038W WO 2005013318 A3 WO2005013318 A3 WO 2005013318A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- donor substrate
- order
- substrate
- thermal annealing
- implantation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
- H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P54/00—Cutting or separating of wafers, substrates or parts of devices
- H10P54/50—Cutting or separating of wafers, substrates or parts of devices by scoring, breaking or cleaving
- H10P54/52—Cutting or separating of wafers, substrates or parts of devices by scoring, breaking or cleaving by cleaving
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10P95/90—Thermal treatments, e.g. annealing or sintering
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
- Recrystallisation Techniques (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP04786008A EP1652230A2 (fr) | 2003-07-29 | 2004-07-29 | Procede d' obtention d' une couche mince de qualite accrue par co-implantation et recuit thermique |
| JP2006521623A JP2007500435A (ja) | 2003-07-29 | 2004-07-29 | 共注入と熱アニールによって特性の改善された薄層を得るための方法 |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR03/09304 | 2003-07-29 | ||
| FR0309304A FR2858462B1 (fr) | 2003-07-29 | 2003-07-29 | Procede d'obtention d'une couche mince de qualite accrue par co-implantation et recuit thermique |
| US10/691,403 US7081399B2 (en) | 2003-07-29 | 2003-10-21 | Method for producing a high quality useful layer on a substrate utilizing helium and hydrogen implantations |
| US10/691,403 | 2003-10-21 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| WO2005013318A2 WO2005013318A2 (fr) | 2005-02-10 |
| WO2005013318A3 true WO2005013318A3 (fr) | 2005-03-24 |
| WO2005013318B1 WO2005013318B1 (fr) | 2005-05-19 |
Family
ID=34117569
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/FR2004/002038 Ceased WO2005013318A2 (fr) | 2003-07-29 | 2004-07-29 | Procede d’obtention d’une couche mince de qualite accrue par co-implantation et recuit thermique |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US20060223283A1 (fr) |
| EP (1) | EP1652230A2 (fr) |
| JP (1) | JP2007500435A (fr) |
| KR (1) | KR20060030911A (fr) |
| WO (1) | WO2005013318A2 (fr) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2773261B1 (fr) | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
| DE602004022882D1 (de) | 2004-12-28 | 2009-10-08 | Soitec Silicon On Insulator | Ner geringen dichte von löchern |
| FR2880988B1 (fr) * | 2005-01-19 | 2007-03-30 | Soitec Silicon On Insulator | TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE |
| FR2889887B1 (fr) | 2005-08-16 | 2007-11-09 | Commissariat Energie Atomique | Procede de report d'une couche mince sur un support |
| FR2891281B1 (fr) | 2005-09-28 | 2007-12-28 | Commissariat Energie Atomique | Procede de fabrication d'un element en couches minces. |
| FR2895563B1 (fr) | 2005-12-22 | 2008-04-04 | Soitec Silicon On Insulator | Procede de simplification d'une sequence de finition et structure obtenue par le procede |
| FR2910179B1 (fr) | 2006-12-19 | 2009-03-13 | Commissariat Energie Atomique | PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART |
| FR2914495B1 (fr) * | 2007-03-29 | 2009-10-02 | Soitec Silicon On Insulator | Amelioration de la qualite d'une couche mince par recuit thermique haute temperature. |
| EP2161741B1 (fr) * | 2008-09-03 | 2014-06-11 | Soitec | Procédé de fabrication d'un semi-conducteur sur un substrat isolant doté d'une densité réduite de défauts SECCO |
| US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
| FR2947098A1 (fr) | 2009-06-18 | 2010-12-24 | Commissariat Energie Atomique | Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince |
| FR2949606B1 (fr) | 2009-08-26 | 2011-10-28 | Commissariat Energie Atomique | Procede de detachement par fracture d'un film mince de silicium mettant en oeuvre une triple implantation |
| FR2953640B1 (fr) * | 2009-12-04 | 2012-02-10 | S O I Tec Silicon On Insulator Tech | Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante |
| JP5703920B2 (ja) * | 2011-04-13 | 2015-04-22 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
| JP2013143407A (ja) | 2012-01-06 | 2013-07-22 | Shin Etsu Handotai Co Ltd | 貼り合わせsoiウェーハの製造方法 |
| JP6056516B2 (ja) | 2013-02-01 | 2017-01-11 | 信越半導体株式会社 | Soiウェーハの製造方法及びsoiウェーハ |
| JP6086031B2 (ja) | 2013-05-29 | 2017-03-01 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
| CN114334792B (zh) * | 2021-10-29 | 2025-01-24 | 上海新昇半导体科技有限公司 | Soi结构的半导体硅晶圆及其制备方法 |
| CN114050123A (zh) * | 2021-10-29 | 2022-02-15 | 上海新昇半导体科技有限公司 | 一种soi晶圆及其最终处理方法 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0954014A1 (fr) * | 1998-04-23 | 1999-11-03 | Shin-Etsu Handotai Company Limited | Procédé de fabrication d'une pastille SOI par délamination utilisant des ions d'hydrogène et la pastille SOI fabriqué par ce procédé |
| FR2797713A1 (fr) * | 1999-08-20 | 2001-02-23 | Soitec Silicon On Insulator | Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede |
| US20020025604A1 (en) * | 2000-08-30 | 2002-02-28 | Sandip Tiwari | Low temperature semiconductor layering and three-dimensional electronic circuits using the layering |
| US6593212B1 (en) * | 2001-10-29 | 2003-07-15 | The United States Of America As Represented By The Secretary Of The Navy | Method for making electro-optical devices using a hydrogenion splitting technique |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3412470B2 (ja) * | 1997-09-04 | 2003-06-03 | 三菱住友シリコン株式会社 | Soi基板の製造方法 |
| FR2774510B1 (fr) * | 1998-02-02 | 2001-10-26 | Soitec Silicon On Insulator | Procede de traitement de substrats, notamment semi-conducteurs |
| CN1155074C (zh) * | 1998-09-02 | 2004-06-23 | Memc电子材料有限公司 | 从低缺陷密度的单晶硅上制备硅-绝缘体结构 |
| JP2000124092A (ja) * | 1998-10-16 | 2000-04-28 | Shin Etsu Handotai Co Ltd | 水素イオン注入剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ |
| EP1158581B1 (fr) * | 1999-10-14 | 2016-04-27 | Shin-Etsu Handotai Co., Ltd. | Procede de fabrication d'une tranche de soi, et tranche de soi |
| JP3943782B2 (ja) * | 1999-11-29 | 2007-07-11 | 信越半導体株式会社 | 剥離ウエーハの再生処理方法及び再生処理された剥離ウエーハ |
| TW452866B (en) * | 2000-02-25 | 2001-09-01 | Lee Tien Hsi | Manufacturing method of thin film on a substrate |
| JP2001274368A (ja) * | 2000-03-27 | 2001-10-05 | Shin Etsu Handotai Co Ltd | 貼り合わせウエーハの製造方法およびこの方法で製造された貼り合わせウエーハ |
| FR2809867B1 (fr) * | 2000-05-30 | 2003-10-24 | Commissariat Energie Atomique | Substrat fragilise et procede de fabrication d'un tel substrat |
| JP2003017723A (ja) * | 2001-06-29 | 2003-01-17 | Shin Etsu Handotai Co Ltd | 半導体薄膜の製造方法及び太陽電池の製造方法 |
| FR2827078B1 (fr) * | 2001-07-04 | 2005-02-04 | Soitec Silicon On Insulator | Procede de diminution de rugosite de surface |
| FR2855910B1 (fr) * | 2003-06-06 | 2005-07-15 | Commissariat Energie Atomique | Procede d'obtention d'une couche tres mince par amincissement par auto-portage provoque |
| US7772087B2 (en) * | 2003-12-19 | 2010-08-10 | Commissariat A L'energie Atomique | Method of catastrophic transfer of a thin film after co-implantation |
| FR2867307B1 (fr) * | 2004-03-05 | 2006-05-26 | Soitec Silicon On Insulator | Traitement thermique apres detachement smart-cut |
| FR2925221B1 (fr) * | 2007-12-17 | 2010-02-19 | Commissariat Energie Atomique | Procede de transfert d'une couche mince |
-
2004
- 2004-07-29 JP JP2006521623A patent/JP2007500435A/ja active Pending
- 2004-07-29 WO PCT/FR2004/002038 patent/WO2005013318A2/fr not_active Ceased
- 2004-07-29 EP EP04786008A patent/EP1652230A2/fr not_active Withdrawn
- 2004-07-29 KR KR1020067001760A patent/KR20060030911A/ko not_active Ceased
-
2006
- 2006-06-05 US US11/446,357 patent/US20060223283A1/en not_active Abandoned
-
2015
- 2015-02-18 US US14/625,407 patent/US20150221545A1/en not_active Abandoned
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0954014A1 (fr) * | 1998-04-23 | 1999-11-03 | Shin-Etsu Handotai Company Limited | Procédé de fabrication d'une pastille SOI par délamination utilisant des ions d'hydrogène et la pastille SOI fabriqué par ce procédé |
| FR2797713A1 (fr) * | 1999-08-20 | 2001-02-23 | Soitec Silicon On Insulator | Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede |
| US20020025604A1 (en) * | 2000-08-30 | 2002-02-28 | Sandip Tiwari | Low temperature semiconductor layering and three-dimensional electronic circuits using the layering |
| US6593212B1 (en) * | 2001-10-29 | 2003-07-15 | The United States Of America As Represented By The Secretary Of The Navy | Method for making electro-optical devices using a hydrogenion splitting technique |
Non-Patent Citations (1)
| Title |
|---|
| AGARWAL A ET AL: "EFFICIENT PRODUCTION OF SILICON-ON-INSULATOR FILMS BY CO- IMPLANTATION OF HE+ WITH H+", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 72, no. 9, 2 March 1998 (1998-03-02), pages 1086 - 1088, XP000742819, ISSN: 0003-6951 * |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2007500435A (ja) | 2007-01-11 |
| US20060223283A1 (en) | 2006-10-05 |
| WO2005013318B1 (fr) | 2005-05-19 |
| EP1652230A2 (fr) | 2006-05-03 |
| KR20060030911A (ko) | 2006-04-11 |
| US20150221545A1 (en) | 2015-08-06 |
| WO2005013318A2 (fr) | 2005-02-10 |
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