WO2006019603A2 - Depot de couche mince de siliciure de tungstene et integration metallique de grille - Google Patents

Depot de couche mince de siliciure de tungstene et integration metallique de grille Download PDF

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Publication number
WO2006019603A2
WO2006019603A2 PCT/US2005/024163 US2005024163W WO2006019603A2 WO 2006019603 A2 WO2006019603 A2 WO 2006019603A2 US 2005024163 W US2005024163 W US 2005024163W WO 2006019603 A2 WO2006019603 A2 WO 2006019603A2
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layer
tungsten
depositing
substrate
polysilicon
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WO2006019603A3 (fr
Inventor
Ming Li
Shulin Wang
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Applied Materials Inc
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Applied Materials Inc
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Publication of WO2006019603A2 publication Critical patent/WO2006019603A2/fr
Publication of WO2006019603A3 publication Critical patent/WO2006019603A3/fr
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/01312—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional layer comprising a metal or metal silicide formed by deposition, i.e. without a silicidation reaction, e.g. sputter deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/664—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a barrier layer between the layer of silicon and an upper metal or metal silicide layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/412—Deposition of metallic or metal-silicide materials
    • H10P14/414—Deposition of metallic or metal-silicide materials of metal-silicide materials

Definitions

  • Embodiments of the present invention generally relate to methods of depositing layers of a gate electrode.
  • Integrated circuits are composed of many, e.g., millions, of devices such as transistors, capacitors, and resistors.
  • Transistors such as field effect transistors, typically include a source, a drain, and a gate stack.
  • the gate stack typically includes a substrate, such as a silicon substrate, a gate dielectric, such as silicon dioxide (SiOa) on the substrate, and a gate electrode on the gate dielectric.
  • Materials that have been used for gate electrodes include metals, such as aluminum (Al), and polysilicon.
  • Doped polysilicon has become a preferred material for gate electrodes, as doped polysilicon has a lower threshold voltage than aluminum.
  • the threshold voltage is the amount of voltage that is required for formation of the channel under the gate that connects the source and drain of a transistor.
  • a lower threshold voltage is preferred as it reduces the amount of power required by the transistor and increases the speed of the transistor.
  • Gate electrodes including a stack of a tungsten (W) or tungsten nitride (WN)/tungsten layer on a polysilicon layer have also been developed. Gate electrodes including a stack of a tungsten or tungsten nitride/tungsten layer on a polysilicon layer can be formed such that the gate electrodes have a low resistance, which is becoming increasingly important with the development of 90 nm and smaller transistors. However, it has been found that the treatment of such gate electrodes with subsequent processing steps, such as annealing, can result in undesirable interactions between the tungsten or tungsten nitride layer and the polysilicon layer.
  • a non-uniform silicon nitride (SiN) or tungsten suicide (WSi x ) layer may be formed between the polysilicon and tungsten or tungsten nitride layers when the layers are annealed. Reactions between the polysilicon and tungsten or tungsten nitride layers can also affect the resistance of the gate electrode and device reliability.
  • Embodiments of the present invention generally provide a method of depositing layers of a gate electrode on a substrate, comprising depositing a polysilicon layer on a substrate, depositing a tungsten suicide layer having a thickness of between about 20 A and about 80 A on the polysilicon layer, and depositing a metal layer on the tungsten suicide layer to form the layers of the gate electrode.
  • the polysilicon layer is a doped polysilicon layer, and a polysilicon-rich layer is deposited on the doped polysilicon layer.
  • Embodiments of the invention also provide a method of depositing layers of a gate electrode on a substrate, comprising depositing a polysilicon layer on a substrate, depositing a tungsten suicide layer having a thickness of between about 20 A and about 80 ⁇ on the polysilicon layer, wherein depositing the tungsten suicide layer comprises exposing the polysilicon layer to silane, reacting a gas mixture comprising dichlorosilane and tungsten hexafluoride to deposit the tungsten suicide layer, and exposing the tungsten suicide layer to silane, and then depositing a metal layer on the tungsten suicide layer to form the layers of the gate electrode.
  • exposing the polysilicon layer to silane comprises depositing a thin silicon layer on the polysilcion layer
  • exposing the tungsten suicide layer to silane comprises depositing a thin silicon layer on the tungsten suicide layer.
  • a method of processing a substrate comprising depositing a polysilicon layer on the substrate in a first chamber of an integrated processing system and depositing a tungsten suicide layer having a thickness of between about 20 A and about 80 A on the polysilicon layer in a second chamber of the integrated processing system, wherein the substrate is not exposed to an atmosphere external to the integrated processing system after depositing the polysilicon layer and before depositing the tungsten suicide layer, is provided.
  • a method of depositing layers of a gate electrode on a substrate comprising depositing a polysilicon layer on the substrate, depositing a layer having a thickness of between about 20 A and about 80 A on the polysilicon layer under conditions sufficient to provide a sheet resistance of the layer of about 2500 ⁇ /cm 2 or greater, and depositing a metal layer on the layer is provided.
  • Figure 1 is a graph showing the phosphorus concentration profile of a doped polysilicon layer and a polysilicon-rich layer deposited thereon according to an embodiment of the invention.
  • Figure 2 is a top schematic view of an integrated processing system.
  • Figure 3 is a cross-sectional view of a structure that includes multiple layers that comprise a gate electrode according to an embodiment.
  • Figure 4 is a flow chart depicting one embodiment of the invention.
  • Figure 5 is a cross-sectional view of a device that includes a gate electrode formed according to one embodiment.
  • Figure 6 is a graph showing the oxygen concentration at the interface between polysilicon layers and tungsten suicide layers deposited according to different embodiments.
  • Embodiments of the invention relate to a method for depositing layers of a gate electrode on a substrate.
  • Embodiments of the invention provide a method of depositing a thin layer between a polysilicon layer and a metal layer wherein the thin layer has a sheet resistance of about 2500 ⁇ /cm 2 or greater.
  • the layers include a polysilicon layer, a tungsten suicide (WSi x ) layer, and a metal layer.
  • the layers provide a gate electrode stack having a desirable sheet resistance and good adhesion between the layers of the stack.
  • the tungsten suicide layer is a thin adhesion or glue layer that enhances the adhesion between the metal layer and the polysilicon layer and prevents undesirable reactions between the metal layer and the polysilicon layer. Since the tungsten suicide layer is very thin, i.e., about 20 A to about 80 A thick, the tungsten suicide layer does not significantly increase the resistance of the gate electrode stack. Tungsten suicide layers having a sheet resistance of at least about 2500 ⁇ /cm 2 as measured on an undoped silicon substrate were obtained according to embodiments of the invention.
  • a polysilicon layer is deposited on a substrate.
  • the substrate may be a silicon or silicon-containing substrate.
  • a silicon substrate includes single layer silicon substrates, such as silicon wafers, or structures that include a silicon layer on top of one or more other layers.
  • the substrate has a thin gate oxide layer formed thereon.
  • the gate oxide layer may be a silicon oxide layer formed by exposing the substrate to an atmosphere comprising oxygen to oxidize the top surface of the substrate.
  • the polysilicon layer may be about 500 A to about 2000 A thick.
  • the polysilicon layer is a doped polysilicon layer, such as a phosphorus doped polysilicon layer.
  • the polysilicon layer may be deposited by reacting a gas mixture comprising a silicon source, such as silane (SiH 4 ) or disilane (Si 2 H 6 ), and a dopant source, such as phosphine (PH 3 ), in a thermal chemical vapor deposition process.
  • the thermal chemical vapor deposition process may be performed in a POLYgenTM chamber of a Polycide Centura ® system.
  • the gas mixture may further comprise a carrier gas, such as nitrogen or an inert gas, such as argon or helium.
  • Exemplary deposition conditions for the polysilicon layer include a silicon source flow rate of between about 30 seem and about 200 seem into a processing chamber, a chamber pressure of between about 50 Torr and about 300 Torr, and a substrate support temperature of between about 570°C and about 750 0 C. Typically, the temperature of the substrate is about 30°C less than the temperature of the substrate support. It is to be noted that the processing conditions provided above and throughout the application are processing conditions for a 300 mm substrate, and that the processing conditions may be adjusted accordingly for other sizes of substrates.
  • a doped polysilicon layer may be formed by depositing an undoped polysilicon layer and then exposing the undoped polysilicon layer to a dopant source.
  • a polysilicon-rich layer may be deposited on the doped polysilicon layer.
  • a polysilicon-rich layer is a polysilicon layer containing a lower concentration of the dopant of the doped polysilicon layer or an undoped polysilicon layer.
  • the doped polysilicon layer may have a dopant concentration of about 1x10 20 to about 1x10 21 atoms/cm 3 and the polysilicon-rich layer may have a dopant concentration of about 1x10 19 atoms/cm 3 at its upper surface such that the polysilicon-rich layer has a lower dopant concentration than the polysilicon layer.
  • the polysilicon-rich layer may be deposited in the same chamber used to deposit the doped polysilicon chamber such that the deposition of the doped polysilicon layer and the polysilicon-rich layer are performed in situ, i.e., in the same chamber without exposing the substrate to an atmosphere external to the chamber between the deposition of the two layers.
  • the polysilicon-rich layer may be deposited by terminating the flow of the dopant source into the chamber and continuing the flow of the silicon source in the chamber.
  • the flows of the dopant source and the silicon source into the chamber are terminated and the chamber is purged, such as with a flow of a carrier gas, before the flow of the silicon source into the chamber is resumed to deposit the polysilicon-rich layer.
  • the polysilicon-rich layer may be deposited in a different chamber than the chamber used to deposit the polysilicon layer.
  • the chamber used to deposit the polysilicon layer and the chamber used to deposit the polysilicon-rich layer may be part of an integrated processing system such that both layers may be deposited without breaking vacuum and exposing the substrate to an atmosphere external to the integrated processing system between the deposition of the two layers.
  • the polysilicon-rich layer may have a concentration gradient of the dopant, with the concentration of the dopant decreasing during the deposition of the polysilicon-rich layer as the remaining dopant source is removed from the chamber, as shown in Figure 1.
  • Figure 1 shows the phosphorus concentration profile of a doped polysilicon layer having a polysilicon-rich layer deposited thereon.
  • the surface of the polysilicon-rich layer has a phosphorus concentration of about 3x10 19 atoms/cm 3 .
  • the phosphorus concentration of the polysilicon-rich layer increases with the depth of the polysilicon-rich layer until it is substantially the same as the phosphorus concentration of the doped polysilicon layer (about 2x10 20 atoms/cm 3 ).
  • a tungsten suicide layer is deposited thereon.
  • the tungsten suicide layer may be deposited by reacting a gas mixture comprising a silicon source, such as dichlorosilane (SiH 2 CI 2 ) or silane (SiH 4 ), and a tungsten source, such as tungsten hexafluoride (WF 6 ) in a thermal chemical vapor deposition process.
  • the gas mixture may further comprise a carrier gas, such as nitrogen or an inert gas.
  • Exemplary deposition conditions for the tungsten suicide layer include a silicon source flow rate of between about 30 seem and about 100 seem into a deposition chamber, a tungsten source flow rate of between about 1 seem and about 3 seem into the deposition chamber, a chamber pressure of between about 0.8 Torr and about 2 Torr, and a substrate support temperature of between about 400°C and about 650 0 C.
  • the substrate support temperature may vary according to the silicon source used. For example, a substrate support temperature of between about 500 0 C and 650 0 C is preferred when dichlorosilane is used as the silicon source, and a substrate support temperature of between about 400 0 C and about 500 0 C is preferred when silane is used as the silicon source.
  • the tungsten suicide layer may have a thickness of between about 20 A and about 80 A and a silicon to tungsten ratio of between about 2.1 :1 and about 3.0:1.
  • the silicon to tungsten ratio is tunable, such as by adjusting the ratio of the silicon source and tungsten source flow rates.
  • depositing the tungsten suicide layer comprises exposing the polysilicon layer, i.e., either a doped polysilicon layer or a polysilicon-rich layer on top of a doped polysilicon layer as described above, to a silicon source, such as silane, before reacting the gas mixture comprising a silicon source and a tungsten source to deposit the tungsten suicide layer on the polysilicon layer.
  • a silicon source such as silane
  • the polysilicon layer may be exposed to the silicon source in the same chamber used to deposit the tungsten suicide layer.
  • a carrier gas may be introduced into the chamber before the silicon source.
  • the silicon source may be introduced into the chamber at a flow rate of between about 300 seem and about 1200 seem, such as about 700 seem, with a chamber pressure of between about 5 Torr and about 10 Torr and a substrate support member in the chamber heated to a temperature of between about 400 0 C and about 650 0 C, such as about 550 0 C.
  • the silicon source may be flowed into the chamber for a period of time sufficient to deposit a thin layer of silicon, such as several atomic layers of silicon, e.g., 1-2 atomic layers having a thickness between about 5 A and about 10 A on the polysilicon layer.
  • the silicon source may be flowed into the chamber at a rate of about 300 seem to about 1200 seem for about 20 seconds to about 50 seconds.
  • a tungsten suicide layer deposited on a polysilicon layer according to an embodiment of the invention had a silicon/tungsten ratio of about 2.4:1 , as measured by X-ray photoelectron spectroscopy (XPS).
  • a tungsten suicide layer having a silicon/tungsten ratio of 2 or greater is desired as it has been observed that tungsten suicide layers having lower silicon/tungsten ratios can provide excess tungsten radicals that react with the underlying polysilicon layer during subsequent substrate processing steps, such as annealing, and form an interface having physical and resistivity non-uniformities between the polysilicon layer and the tungsten suicide layer.
  • a tungsten suicide layer having a silicon/tungsten ratio of 2 or greater is also desired as it has been found that tungsten suicide layers having a lower silicon/tungsten ratio have a tendency to be delaminated.
  • dichlorosilane is introduced into the chamber.
  • a stable flow rate of the dichlorosilane is established in the chamber.
  • a dichlorosilane flow rate of between about 30 seem and about 100 seem, such as about 60 seem, and a chamber pressure of about 1 to about 1.2 Torr may be used.
  • tungsten hexafluoride is introduced into the chamber, such as with a flow rate of between about 1 seem and about 3 seem, such as about 2 seem and a chamber pressure of about 0.8 Torr to about 2 Torr, such as about 1 to about 1.2 Torr.
  • the dichlorosilane and tungsten hexafluoride are reacted within the chamber to deposit a tungsten suicide layer.
  • the substrate support member in the chamber may be heated to a temperature of between about 400 0 C and about 650°C, such as about 550°C, during the deposition of the tungsten suicide layer. As discussed above, the temperature may be varied depending on the source gases used.
  • a flow of dichlorosilane is maintained with a flow of carrier gas to purge the chamber after the deposition of the tungsten suicide layer.
  • the tungsten suicide layer may be exposed to a flow of a silicon source, such as silane.
  • a carrier gas may also be used.
  • the silane may be flowed into the chamber at a rate between about 100 seem and about 700 seem at a substrate support member temperature of between about 500°C and about 600°C and a chamber pressure of between about 0.8 Torr to about 2 Torr, such as about 1 to about 1.2 Torr.
  • Exposing the tungsten suicide layer to the silane flow enables the removal of unwanted fluorine atoms that may be associated with the tungsten silicide layer as a residue from a fluorine- containing precursor, such as WF 6 , used to deposit the layer.
  • the silane decomposes and combines with the fluorine atoms to form HF and SiF 4 which can be pumped out of the chamber. Exposing the tungsten silicide layer to the silane may also form a silicon-rich cap on the tungsten silicide which can be oxidized to form a silicon oxide cap that protects the underlying layers.
  • the exposure of the polysilicon layer to a silicon source, deposition of the tungsten silicide layer, and exposure of the tungsten silicide layer to a silicon source may be performed in different chambers within an integrated processing system such that the substrate is not exposed to an atmosphere external to the integrated processing system from the exposure of the polysilicon layer to a silicon source through the exposure of the tungsten silicide layer to a silicon source.
  • a flow of ammonia may be introduced into the chamber to form tungsten-nitrogen bonds on the surface of the tungsten silicide layer and enhance the deposition of a tungsten nitride layer thereon.
  • a metal layer is deposited on the tungsten silicide layer.
  • the metal layer may be a tungsten layer, tungsten nitride layer, or a combination thereof, such as a tungsten nitride layer followed by a tungsten layer.
  • the tungsten and tungsten nitride layers may be deposited by CVD, physical vapor deposition (PVD), or atomic layer deposition (ALD), for example.
  • Exemplary processing conditions for depositing the tungsten and tungsten nitride layers are disclosed in commonly assigned U.S. Patent Application Serial No. 10/084,767, entitled "Cyclical Deposition of Tungsten Nitride for Metal Oxide Gate Electrode,” filed on February 26, 2002, which is incorporated herein by reference to the extent not inconsistent with the disclosure and claimed aspects of the invention described herein.
  • an integrated method of depositing layers of a gate electrode, the layers comprising a polysilicon layer and a tungsten suicide layer having a thickness of between about 20 A and about 80 A, on a substrate within an integrated processing system is provided.
  • An example of an integrated processing system 100 that may be used is the Polycide Centura ® system, available from Applied Materials, Inc. of Santa Clara, CA, which is shown schematically in Figure 2.
  • the integrated processing system 100 may include a central transfer chamber 102, transfer robot 103, load locks 104, 106, and processing chambers 110, 114, 116, and 118. Processing chambers 110, 114, 116, and 118 are thermal chemical vapor deposition chambers.
  • processing chambers 110 and 116 are POLYgenTM chambers, and processing chambers 114 and 118 are DCS (dichlorosilane) xZ 300 chambers, both of which are available from Applied Materials, Inc.
  • POLYgenTM chambers are low pressure chemical vapor deposition (LPCVD) chambers that may be used to deposit the doped and polysilicon-rich layers of embodiments of the invention.
  • DCS xZ 300 chambers are chemical vapor deposition chambers that may be used to deposit tungsten suicide layers according to embodiments of the invention.
  • a Polycide Centura ® system having only two processing chambers, wherein one processing chamber is a POLYgenTM chamber and the other processing chamber is a DCS xZ 300 chamber, may be used.
  • FIG. 3 is a cross-sectional view of a structure 200 that includes layers of a gate electrode.
  • Figure 4 is a flow chart summarizing a processing sequence of the embodiment.
  • a substrate 202 is introduced into the integrated processing system 100, as shown in step 302 ( Figure 4).
  • the substrate 202 includes a gate oxide layer 204 thereon.
  • the substrate 202 is introduced into the integrated processing system 100 through the load lock 104 or 106.
  • the substrate 202 is transferred to processing chamber 110 by the transfer robot 103.
  • a doped polysilicon layer 206 is deposited on the gate oxide layer 204 in processing chamber 110, as shown in step 304.
  • a polysilicon-rich layer 208 is then deposited on the doped polysilicon layer 206 in the processing chamber 110, as shown in step 306.
  • the substrate 202 is transferred to processing chamber 118 by the transfer robot 103, as shown in step 308.
  • the substrate 202 and the layers thereon are exposed to silane in processing chamber 118, as shown in step 310.
  • the substrate 202 and the layers thereon may be exposed to the silane for a period of time sufficient to deposit a thin layer of silicon 210 thereon.
  • a tungsten suicide layer 212 is then deposited in processing chamber 118, as shown in step 312.
  • the substrate 202 and the layers thereon are exposed to silane in processing chamber 114, as shown in step 314.
  • the substrate 202 and the layers thereon may be exposed to the silane for a period of time sufficient to form a silicon-rich cap 214.
  • the substrate 202 is then removed from the integrated processing system 100, as shown in step 316.
  • a metal layer 216 is deposited on top of the layers deposited on the substrate, as shown in step 318.
  • the metal layer may be a tungsten layer, tungsten nitride layer, or a combination thereof.
  • a polysilicon layer is deposited on a substrate and then a tungsten suicide layer is deposited on the polysilicon layer without exposing the substrate to atmosphere, in other embodiments, the substrate may be exposed to atmosphere after the deposition of the polysilicon layer and before the deposition of the tungsten suicide layer.
  • the substrate may be cleaned by exposing the substrate to hydrofluoric acid (HF), e.g., by rinsing the substrate with HF, after the deposition of the polysilicon layer and before the deposition of the tungsten suicide layer.
  • HF hydrofluoric acid
  • Figure 5 depicts a NMOS transistor 500 comprising a substrate 502 having source 504 and drain 506 regions.
  • the substrate has a gate oxide layer 508 formed thereon between the source 504 and drain 506 regions.
  • Gate electrode 510 includes gate electrode layers (not shown) formed according to any of the embodiments of the invention. Spacers 512 surround the gate oxide layer 508 and the gate electrode 510.
  • a 300 mm substrate having an oxide layer formed thereon was introduced into a Polycide Centura ® system comprising a POLYgenTM chamber and a DCS xZ 300 chamber.
  • a doped polysilicon layer was deposited on the substrate in a POLYgenTM chamber using a thermal chemical vapor deposition process from a gas mixture comprising silane and 1% phosphine diluted with hydrogen.
  • the doped polysilicon layer was deposited at a pressure of 150 Torr with a phosphine flow rate of 99 seem and a disilane flow rate of 50 seem for about 55 seconds at a substrate support temperature of 600 0 C and a substrate temperature of approximately 558°C.
  • Nitrogen was flowed into the chamber prior to the deposition and was continued during and after the deposition.
  • An undoped polysilicon layer was then deposited on the doped polysilicon layer using a disilane flow rate of 80 seem for about 25 seconds, a pressure of 150 Torr, and a substrate support temperature of 600 0 C and a substrate temperature of approximately 558°C.
  • the substrate was then transferred to a DCS xZ 300 chamber.
  • Argon was introduced through a dichlorosilane source port in the chamber at 1000 seem and was also introduced through a tungsten hexafluoride source port in the chamber at 1000 seem and maintained through the deposition of the tungsten suicide layer.
  • the substrate was then exposed to silane for 35 seconds at a flow rate of 300 seem.
  • Dichlorosilane was then introduced into the chamber at a flow rate of 60 seem for 10 seconds before tungsten hexafluoride was introduced into the chamber at a flow rate of 2 seem and the flow of dichlorosilane was maintained with the flow of tungsten hexafluoride for 20 seconds to deposit a 50 A tungsten suicide layer.
  • the tungsten suicide layer was deposited at a substrate support temperature of 550°C and a substrate temperature of approximately 443°C at a pressure of 1.2 Torr.
  • the flow of tungsten hexafluoride was terminated, and the flow of dichlorosilane was maintained for 10 seconds.
  • the substrate was then exposed to silane at a flow rate of 100 seem for 10 seconds at a substrate support temperature of 550 0 C and a substrate temperature of approximately 443°C at a pressure of 2 Torr.
  • the transfer chamber is typically maintained with a nitrogen atmosphere such that exposure of the substrate to oxygen is minimized while the substrate is within the integrated processing system.
  • the transfer chamber may have a pressure of about 2.5 to about 5 Torr, such as about 3 Torr.
  • a polysilicon layer and a tungsten suicide layer can be deposited within an integrated processing system (in situ integration line in Figure 6) such that the oxygen concentration at the interface between the polysilicon layer and the tungsten suicide layer is less than the oxygen concentration at the interface between a polysilicon layer and a tungsten suicide layer, wherein the polysilicon layer is deposited in a first processing chamber and the tungsten suicide layer is exposed to the external atmosphere and deposited three hours later in a second processing chamber (idle time 3 hours line in Figure 6).
  • oxygen concentration at the interface between a polysilicon layer and a tungsten suicide layer of a substrate exposed to the external atmosphere can be reduced by rinsing the substrate with hydrofluoric acid (HF), it is preferred to deposit the polysilicon layer and the tungsten suicide layer within an integrated processing system.
  • HF hydrofluoric acid

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Abstract

L'invention concerne un procédé de dépôt de couches d'une électrode grille. Le procédé comprend le dépôt d'une couche de silicium polycristallin dopé, d'une couche mince de siliciure de tungstène et d'une couche métallique. Dans un procédé selon l'invention, la couche de silicium polycristallin et la couche mince de siliciure de tungstène sont déposées à l'intérieur d'un système de traitement intégré. Dans un autre procédé selon l'invention, le dépôt de couche mince de siliciure de tungstène inclut l'exposition d'une couche de silicium polycristallin à une source de silicium, le dépôt d'une couche de siliciure de tungstène, et l'exposition de la couche de siliciure de tungstène à une source de silicium.
PCT/US2005/024163 2004-07-30 2005-07-07 Depot de couche mince de siliciure de tungstene et integration metallique de grille Ceased WO2006019603A2 (fr)

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JP2008508721A (ja) 2008-03-21
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KR100871006B1 (ko) 2008-11-27
KR20070037645A (ko) 2007-04-05
US20060024959A1 (en) 2006-02-02

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