WO2006038201A2 - Dispositifs a semi-conducteur de puissance - Google Patents

Dispositifs a semi-conducteur de puissance Download PDF

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Publication number
WO2006038201A2
WO2006038201A2 PCT/IB2005/053289 IB2005053289W WO2006038201A2 WO 2006038201 A2 WO2006038201 A2 WO 2006038201A2 IB 2005053289 W IB2005053289 W IB 2005053289W WO 2006038201 A2 WO2006038201 A2 WO 2006038201A2
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WO
WIPO (PCT)
Prior art keywords
gate
region
channel
drain
major surface
Prior art date
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Ceased
Application number
PCT/IB2005/053289
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English (en)
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WO2006038201A3 (fr
Inventor
Steven T. Peake
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Koninklijke Philips NV
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Koninklijke Philips Electronics NV
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Publication of WO2006038201A2 publication Critical patent/WO2006038201A2/fr
Publication of WO2006038201A3 publication Critical patent/WO2006038201A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/611—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates

Definitions

  • the present invention relates to power semiconductor devices and to circuit arrangements including such devices.
  • Vertical insulated gate field effect power transistor semiconductor devices which comprise a semiconductor body having an active area with a plurality of electrically parallel transistor cells. Each transistor cell has a source region and a drain region of a first conductivity type, which are separated by a channel- accommodating body region of a second, opposite, conductivity type which extends adjacent to an insulated gate structure.
  • a desirable property for power transistors is to have good switching performance, that is fast switching and low switching losses when the device is turned on and off. This is particularly important where the power transistor is to be used in the output stage of the power supply, for example a voltage regulation module (VRM) for a PC motherboard, where it is continuously turned on and off at very high frequency.
  • VRM voltage regulation module
  • WO-A-2004/032243 discloses a vertical insulated gate field effect power transistor in which the gate structure comprises first and second gates isolated from each other so as to be independently operable. The first gate is a trench-gate, and the second gate is a planar gate. Simultaneous operation of the first and second gates forms a conduction channel between source and drain regions of the device.
  • the present invention provides a semiconductor device including: a semiconductor body defining opposed first and second major surfaces; a drain region of a first conductivity type comprising a drain drift region and a drain contact region, with the drain drift region extending to part of the first major surface, and the drain contact region being more highly doped than the drain drift region and extending to the second major surface; a source region of the first conductivity type extending from the first major surface; a channel-accommodating region of a second, opposite conductivity type extending from the first major surface and separating the source and drain regions and defining junctions with the source and drain drift regions at the first major surface; first and second gates extending laterally over the first major surface which are isolated from each other so as to be independently operable, the first gate extending part way across the channel- accommodating region from over said source region junction towards said drain drift region junction, and the second gate extending over the channel-accommodating region from adjacent to the first gate to over said drain drift region junction, such that the first and second gates are operable to form a conduction
  • a modulating potential is applied to the first gate, and a fixed potential is applied to the second gate.
  • the device is therefore turned on by application of a sufficient bias potential to the first gate, in combination with a sufficient fixed potential at the second gate. If no bias potential is applied to the first gate, the net current flow through the conduction channel of the device will be zero.
  • the controlling first gate is spaced from the drain drift region by the associated insulating layer and also a portion of the channel-accommodating region.
  • the gate-drain capacitance of the device is therefore negligible, providing a substantial reduction in switching losses.
  • the device structure of the present invention is more cost effective to manufacture than that of WO-A-2004/032243. Its fabrication may only require one more photolithographic stage than the manufacture of a known planar VDMOS (vertical double-diffused metal oxide semiconductor) device.
  • the second gate extends between two adjacent transistor cells, and extends over the junction of the first major surface between the drain drift region and the channel-accommodating region in each of the two adjacent cells.
  • one of the first and second gates extends part way over the other gate. This serves to minimise the gap between the gates where there will be reduced field effect. If both gates are formed in the same layer and defined in the same photolithographic step, the minimum gap would typically be about 0.5 micron (or at least the same as the minimum etched dimension for a particular toolset). Overlapping the gates reduces this gap to the thickness of the intervening insulating layer (typically about 50 nm).
  • Overlapping the gates may also give greater flexibility in cell design, more readily facilitating the fabrication of square or hexagonal arrays, as well as stripe cell geometries.
  • the source and channel-accommodating regions are contacted by a source electrode at the surface of a trench which extends into the semiconductor body from the first major surface. This reduces the area required to achieve these contacts, making the structure more compact.
  • the first and second gates may be connected to first and second gate terminals for connection to respective control potentials.
  • the first gate terminal may be connected to a gate driver circuit for applying a modulating potential, and the second gate terminal connected in use to a fixed, bias potential.
  • the invention further provides a circuit arrangement including a device as described herein, wherein the device is a power transistor connected in series with a second power transistor for supplying a regulated voltage to an output via a switch node connection between the power transistors, the gate driver circuit being included in a control circuit for alternately switching the power transistors on and off.
  • the present invention also provides a circuit arrangement including a device as described herein, wherein the device is a switch for supplying current to a load connected to one of a source electrode and a drain electrode of the device.
  • the second gate terminal of the device is connected to a supply voltage rail of the circuit.
  • Figure 1 shows a cross-sectional side view of the active area of a semiconductor body of a prior art device
  • Figure 2 shows a cross-sectional side view of the active area of the semiconductor body of a semiconductor device according to an embodiment of the present invention
  • Figures 3 and 4 are graphs showing plots of switching energy loss during turn-on and turn-off, respectively, against time, generated by simulation of a prior art device and a device embodying the invention
  • Figure 5 is a graph showing plots of on-resistance and switching energy loss per cycle at turn-on and turn-off generated by simulation of a device embodying the invention
  • Figure 6 is a graph showing plots of switching energy figure of merit per cycle at turn-on and turn-off generated by a simulation of the device embodying the invention
  • Figure 7 is a graph showing plots of drain current against drain voltage generated by simulation of a prior art device and a device embodying the present invention
  • Figure 8 shows a voltage regulation module circuit arrangement including a device embodying the invention connected as a high side power transistor in series with a low side power transistor via a switch node;
  • Figure 9 shows a circuit arrangement including a device embodying the invention connected as a low side switch for supplying current to a load and including a protection circuit.
  • Figure 1 illustrates a device of the form disclosed in WO-A-2004/032243. It comprises a monocrystaline silicon semiconductor body 10 having a top major surface 10a opposed to a bottom major surface 10b.
  • the semiconductor body 10 comprises a relatively highly doped substrate
  • a p-type channel- accommodating region 15 extends between the top surface 10a and the drain drift region 14.
  • the source region 13 is contacted by a source electrode 23 at the top major surface 10a of the device body.
  • the drain contact region 14a is contacted at the bottom major surface 10b of the semiconductor body by a drain electrode 24.
  • the gate structure of the device shown in Figure 1 comprises first and second gates 17 and 19 respectively, which are isolated from each other so as to be independently operable.
  • the second gate 19 is provided in a trench which extends from the top major surface 10a, through the channel-accommodating region 15, to the drain drift region 14.
  • the first gate 17 is a planar gate formed over and extending to the side of the second gate.
  • the first gate enables a first, lateral channel portion to be formed in the channel-accommodating region when a gate potential is applied to the first gate.
  • the second gate 19 enables a second, vertical channel portion to be formed in the channel-accommodating region when a gate potential is applied thereto.
  • a modulating gate potential is connected to the first gate, and a fixed gate potential is connected to the second gate.
  • a modulating gate potential is connected to the first gate, and a fixed gate potential is connected to the second gate.
  • Near zero Cgd and Qgd values result from the second gate 19 shielding the first gate 17 from the drain drift region, reducing the gate-drain periphery of the second gate to zero.
  • FIG. 2 illustrates an exemplary embodiment of a power semiconductor device according to the invention.
  • the drain drift region 14 extends to part of the first major surface 10a.
  • Channel-accommodating region 15 extends from the first major surface 10a and separates the source and drain regions, 31 and 14, 14a respectively. It defines a junction 15a with the source region and a junction 15b with the drain drift region adjacent to the first major surface 10a.
  • a first gate 33 in the form of a planar gate, extends laterally over the first major surface 10a and extends from over the source region, across the junction 15a between the source region and the channel-accommodating region, and part way across the channel-accommodating region 15 towards the junction 15b.
  • the second gate 35 extends from a location adjacent to the first gate, over the channel- accommodating region 15, and over the junction 15b between the channel- accommodating region and the drain drift region 14.
  • a portion 35a of the second gate 35 extends partway over the first gate 33.
  • the first and second gates are insulated from the semiconductor body by an insulating layer 37.
  • the thickness of the insulating layer 37 under the second gate 35 may be greater than that under the first gate 33.
  • An insulating layer 39 is provided over the first gate 33, isolating it from the second gate.
  • This layer is typically 20-60 nm thick and may be formed of silicon dioxide or silicon nitride, for example.
  • a further insulating layer 41 is formed over the second gate 35.
  • the source region is contacted by a source electrode 43.
  • This electrode 43 is provided in a trench 47 which extends through source region 31 and into the channel-accommodating region 15.
  • the source electrode extends to the sidewall of the trench 47a, and the channel accommodating region extends to its base 47b.
  • the device of Figure 2 is operable in a similar manner to that of Figure 1.
  • a fixed gate potential is applied to the second gate 35, and a modulating gate potential applied to the first gate 33.
  • Cgd and Qgd of the device shown in Figure 2 are essentially zero, with the first gate being shielded from the drain drift region, and having zero gate-drain periphery.
  • devices embodying the present invention may be manufactured using techniques well known to those skilled in the art.
  • the device may be manufactured using processes associated with DMOS or VDMOS technology.
  • a short oxidation or deposition process may be carried out to form the insulating layer 39 between the first and second gates.
  • the second gate may then be formed by depositing a layer of polysilicon and using photolithography to pattern this layer to form the second gate 35 and its bond pad. Further oxidation (or deposition) may then be performed to form the insulating layer 41 over the second gate 35.
  • No plan view of the cellular geometry is shown in the drawings, as the device according to the invention may be fabricated using quite different, known cell geometries.
  • the cells may have a square geometry as illustrated in Figure 14 of US-A-5378655, or they may have a close-packed hexagonal geometry, or an elongate stripe geometry.
  • the second gate 35 extends around the boundary of each cell.
  • Figure 2 shows half of each of two adjacent cells A and B, which meet at a boundary having a lateral location indicated by numeral 45 in Figure 2. It will be appreciated that typically a device will comprise many hundreds of parallel cells between the electrodes 43 and 24.
  • the active cellular area of the device may be bounded around the periphery of the body 10 by various known peripheral termination schemes (also not shown).
  • Such schemes normally show the formation of a thick field-oxide layer at the peripheral area of the first major surface 10a, before the transistor cell fabrication steps.
  • various known circuits such as gate control circuits
  • the circuit elements may be fabricated with their own layout in this circuit area using some of the same masking and doping steps as are used for the transistor cells.
  • the applicants have simulated a device embodying the present invention, to demonstrate its improved performance relative to a simulation of a known device having a typical three terminal trench-gate configuration.
  • the device embodying the invention had the following characteristics:
  • Figures 3 and 4 show plots of switching energy loss against time at turn-on and turn-off, respectively, for one cycle.
  • plots 51 and 51' (plotted using square data points)
  • a constant bias of 5 volts was applied to second gate 35
  • plots 53 and 53' (plotted using triangular data points)
  • a constant bias of 10 volts was applied to second gate 35.
  • Plots 55 and 55' (circular data points) show the performance of the simulated known trench-gate device.
  • Figure 5 shows simulated measurements of on-resistance (Ron) at a first gate voltage of 10 V (plot 61 with square data points); and switching energy loss per cycle at turn-on (plot 63, triangular data points) and turn-off (plot 65, circular data points) for a device having an active area of 10 mm 2 , whilst the bias applied to the second gate is varied from 5 V to 10 V.
  • Ron on-resistance
  • Figure 6 shows plots of the simulated turn-on, turn-off and "total switching energy figure of merit" (plots 71, 73 and 75 respectively).
  • This figure of merit is the switching energy per cycle (mJ) multiplied by the Ron (mOhm) of the device at a first gate voltage of 10 V.
  • the plots are over a range of second gate bias voltages from 5 V to 10 V.
  • Figure 6 suggests that a preferred value for the voltage power supply to the second gate is around 6 V or less.
  • the total switching energy figure of merit for the simulated device embodying the invention was found to be around 60% lower than that for the simulated known trench-gate structure.
  • Figure 7 shows the reverse characteristics of the device embodying the invention (plot 81) and the known trench-gate device (plot 83).
  • a bias voltage of 5 V was applied to the second gate. It can be seen that the device embodying the invention supports a significantly greater reverse voltage than the known device using the same drain drift region doping concentration.
  • FIG 8 shows a voltage regulation module (VRM) circuit arrangement 150 including a power transistor 113 embodying the present invention connected as a high side power transistor in series with a low side power transistor 116 for supplying a regulated voltage to an output 151 via a switch node connection 152 between the transistors 113 and 116.
  • VRM voltage regulation module
  • the circuit 150 may be, for example, a synchronous DC-DC buck converter used to convert an input voltage supply (e.g. 12 V) to a lower output voltage supply (e.g. 5 V).
  • the input voltage is applied between an input line voltage terminal 153 and a ground terminal 154.
  • the high side transistor 113 is next to the input terminal 153 and is known as the control FET.
  • the low side transistor 116 is connected to the ground terminal 154 and is known as the synchronous FET (syncFET).
  • the switch node connection 152 feeds through an inductor 155 and across a capacitor 156 to the output line voltage terminal 151.
  • a control circuit 157 has a control portion 171 with one input on a control terminal 158 and another input fed from the output 151 via a feedback path 159.
  • the controller portion 171 supplies control signals to a gate driver circuit 173 for the high side transistor 113 and to a gate driver circuit 176 for the low side transistor 116. These control signals are alternating signals which cause the control and sync FETs 113, 116 to conduct alternately.
  • the mark-space ratio that is the ratio of the time for which the control FET 113 conducts to the time the sync FET 116 conducts is varied to achieve the desired voltage on the ouput 151.
  • the second gates 35 of the cells of the transistor 113 are connected to a second gate terminal 111 which is connected to terminal means Vcc for connecting a supply to a fixed gate potential to the second gate terminal 111.
  • the terminal Vcc to which the gate terminal 111 is connected is the terminal which supplies a 12 V line voltage to the gate driver circuit 173.
  • the gate terminal 111 could be connected to the 12 V input line voltage terminal 153 or to the 5 V output line voltage terminal 151.
  • the first gates 33 of the cells of the transistor 113 are connected to a first gate terminal 121 which is connected to the gate drive circuit 173 for applying a modulating potential to the gate terminal 121.
  • the power transistor of the invention described herein is particularly advantageous for use as the high side control FET because low switching losses are a primary consideration for this transistor. Low switching losses are less important for the low side syncFET 116 for which a low on-state resistance is important. A trench gate MOSFET power transistor may therefore be preferable for use as the syncFET 116.
  • Figure 9 shows a circuit arrangement 160 including a power transistor embodying the present invention connected as a low side power transistor in series with a load L between a voltage supply line terminal 163 and a ground terminal 164.
  • the power transistor 113 acts as a switch for supplying current to the load L when its drain electrode is connected to the load L via the terminal 162 of the circuit 160.
  • a control circuit 167 has a control portion 171 connected to a control input terminal 168.
  • the control portion 171 supplies control signals to a gate driver circuit 173 for the transistor 113.
  • the second gates 35 of the cells of the transistor 113 are connected to a second gate terminal 111 which is connected to terminal means VF for connecting a supplied fixed gate potential to the gate terminal 111.
  • the first gates 33 of the cells of the transistor 113 are connected to a first gate terminal 121 which is connected to the gate driver circuit 173 for applying a modulating potential to the gate terminal 121 .
  • the control circuit 167 includes protection circuit means 174 for the power transistor switch 113.
  • the protection circuit means 174 is not shown connected in Figure 9, since its connections to the other circuit elements shown within the circuit arrangement 160 depend on whether it is adapted and arranged for one or more of the functions of voltage overload protection, current overload protection, and temperature overload protection.
  • the embodiment shown in Figure 2 is a MOSFET device. However, it will be appreciated that the drain contact region 14a may be of opposite conductivity type to region 14 to provide a vertical IGBT.
  • the particular example described in relation to Figure 2 is an n-channel device.
  • a p-channel device By using opposite conductivity type dopants to those shown in Figure 2, a p-channel device can be provided.
  • the regions 31, 14 and 14a are of p-type conductivity
  • the region 15 is of n-type
  • a hole inversion channel is induced in the region 15 by the first and second gates 33 and 35.
  • the region 14a may be a doped buried layer between a device substrate and the epitaxial low-doped drain drift region 14.
  • This buried layer 14a may be contacted by an electrode 24 at the front of the major surface 10a, via a doped peripheral contact region which extends from the surface 10a to the depth of the buried layer.

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteur de puissance comprenant une région (15) contenant un canal s'étendant à partir d'une première surface principale (10a) de son corps semi-conducteur et séparant les régions source et drain. La région contenant le canal définit des jonctions (15a, 15b) avec des régions source et de dérive drain à la première surface principale. Une première et une seconde grilles (33, 35) s'étendent latéralement sur la première surface principale (10a) et sont isolées l'une de l'autre de manière à fonctionner indépendamment. La première grille (33) s'étend en partie à travers la région du canal (15), à partir de ladite jonction de région source (15a) vers ladite jonction de région de dérive drain (15b), et la seconde grille (35) s'étend à travers la région du canal (15) à partir de la zone adjacente à la première grille (33), vers ladite jonction de la région de dérive drain (15b), de façon que la première et la seconde grilles fonctionnement pour former un canal de conduction dans la région du canal, entre les régions source et drain. Lorsque le dispositif est utilisé, un potentiel de modulation est appliqué à la première grille (33), et un potentiel fixe est appliqué à la seconde grille (35). Le dispositif est donc mis sous tension par application d'un potentiel de polarisation suffisant à la première grille, en combinaison avec un potentiel fixe suffisant à la seconde grille. La première grille de réglage est séparée de la région de dérive drain (14) par la couche isolante associée, ainsi que par une portion de la région du canal (15). La capacité grille-drain du dispositif est donc négligeable, ce qui entraîne une réduction substantielle des pertes de commutation.
PCT/IB2005/053289 2004-10-09 2005-10-06 Dispositifs a semi-conducteur de puissance Ceased WO2006038201A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0422476.2A GB0422476D0 (en) 2004-10-09 2004-10-09 Power semiconductor devices
GB0422476.2 2004-10-09

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WO2006038201A2 true WO2006038201A2 (fr) 2006-04-13
WO2006038201A3 WO2006038201A3 (fr) 2006-09-14

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3089216A4 (fr) * 2013-12-23 2017-10-11 Zhongshan Hkg Technologies Limited Transistor à effet de champ à semiconducteurs à puissance de porte double
CN109817708A (zh) * 2019-01-28 2019-05-28 江苏矽导集成科技有限公司 一种快速开关igbt结构

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8204855A (nl) * 1982-12-16 1984-07-16 Philips Nv Veldeffekttransistor met geisoleerde stuurelektrode en werkwijze ter vervaardiging daarvan.
JPH0834311B2 (ja) * 1987-06-10 1996-03-29 日本電装株式会社 半導体装置の製造方法
JP2006501666A (ja) * 2002-10-04 2006-01-12 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ パワー半導体デバイス

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3089216A4 (fr) * 2013-12-23 2017-10-11 Zhongshan Hkg Technologies Limited Transistor à effet de champ à semiconducteurs à puissance de porte double
CN109817708A (zh) * 2019-01-28 2019-05-28 江苏矽导集成科技有限公司 一种快速开关igbt结构
CN109817708B (zh) * 2019-01-28 2023-10-31 江苏矽导集成科技有限公司 一种快速开关igbt结构

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GB0422476D0 (en) 2004-11-10
WO2006038201A3 (fr) 2006-09-14

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