WO2006100950A1 - Appareil d'affichage et circuit et procede de commande - Google Patents

Appareil d'affichage et circuit et procede de commande Download PDF

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Publication number
WO2006100950A1
WO2006100950A1 PCT/JP2006/304896 JP2006304896W WO2006100950A1 WO 2006100950 A1 WO2006100950 A1 WO 2006100950A1 JP 2006304896 W JP2006304896 W JP 2006304896W WO 2006100950 A1 WO2006100950 A1 WO 2006100950A1
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WIPO (PCT)
Prior art keywords
pixel
sub
image
data signal
signal line
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Ceased
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PCT/JP2006/304896
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English (en)
Japanese (ja)
Inventor
Hidetaka Mizumaki
Yasuhiro Hirayama
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Sharp Corp
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Sharp Corp
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1323—Arrangements for providing a switchable viewing angle
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
    • G09G3/003—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to produce spatial visual effects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns

Definitions

  • the present invention relates to a display device for displaying different images for at least two viewpoints and a drive circuit thereof, for example, a binocular parallax is generated for one user and a stereoscopic image is generated.
  • the present invention relates to a liquid crystal display device that performs typical display and a liquid crystal display device that displays different images to two users.
  • liquid crystal display devices that provide stereoscopic display by causing binocular parallax to a user have been provided.
  • a parallax barrier is provided on the liquid crystal panel to display different images for two viewpoints corresponding to the left and right eyes.
  • DV liquid crystal display device a liquid crystal display device that displays different images for two users.
  • the display image seen from the right side and the display image seen from the left side can be made different. Therefore, this DV liquid crystal display device is installed in a car, for example, to display different images for the driver and passengers in the passenger seat, or installed at a bank counter to display different images for customers and staff. Can be done.
  • FIG. 16 (A) is a plan view schematically showing the arrangement of the pixel forming portions (hereinafter referred to as “pixel arrangement”) for forming the pixels of the image to be displayed in the DV liquid crystal display device.
  • Figure 16 (C) is a plan view and a cross-sectional view schematically showing a configuration for dual view display based on the pixel arrangement ( Figure 16 (C) is a cross-sectional view of YY in Figure 16 (B). (It is a sectional view in the line)
  • each pixel constituting an image to be displayed is composed of an R (red) subpixel, a G (green) subpixel, and a B (blue) subpixel.
  • an R (red) pixel formation portion also referred to as an “R subpixel”
  • a G (green) pixel formation are formed.
  • a B (blue) pixel formation portion also referred to as “B subpixel”.
  • the pixel array having a large number of pixel forming portions arranged in a matrix has columns of R subpixels, columns of G subpixels, and An image to be displayed (displayed on a DV liquid crystal display device) by three subpixels consisting of an R subpixel, a G subpixel, and a B subpixel arranged in every other column. There are two images to be formed, and one pixel in one image) is formed.
  • the light emitted from each subpixel 90 is selectively blocked by disposing the parallax barrier 84b as shown in FIGS. 16 (B) and 16 (C).
  • the light exiting from the DV liquid crystal display device is only the light passing through the slit 84s formed in the parallax barrier layer. That is, light is emitted only in the ranges indicated by ⁇ b and ⁇ g in FIG.
  • FIG. 16 (C) the user located in the left DL in front of the display surface of the DV liquid crystal display device is notified to the third B subpixel from the left among the four subpixels shown in the figure.
  • the power to see the pixel The second G subpixel from the left is not visible.
  • the user who is located on the right side DR in front of the display surface of the DV liquid crystal display device can see the second G sub-pixel from the left of the four sub-pixels shown in the figure.
  • the third B subpixel is not visible. Therefore, among the sub-pixels arranged in a matrix in the DV liquid crystal display device, the first sub-pixel group consisting of sub-pixels selected every other column is for the user (viewpoint) located in the left DL.
  • the second pixel group consisting of sub-pixels other than the first sub-pixel group (this is also the sub-pixel force selected every other column) is used on the right DR.
  • An image to be displayed to the person (viewpoint) is formed. That is, in the DV liquid crystal display device, the display image when viewed from the left DL is different from the display image when the right DR force is also viewed.
  • Patent Document 1 Japanese Unexamined Patent Publication No. 2004-206089
  • Patent Document 2 Japanese Unexamined Patent Publication No. 2004-287406
  • the left side force of the DV liquid crystal display device when the left side force of the DV liquid crystal display device is viewed and when the right side force is viewed, it is possible to display different images well, that is, it should be visible only from one of the left and right sides. If the image can be seen when the other force is seen, whether or not the phenomenon (hereinafter “reflection of left and right images” t) can be sufficiently prevented is sensitive to the positional relationship between the parallax barrier 84b and the sub-pixel 90. In order to prevent the right and left images from being reflected, the distance (gap) d2 between the parallax barrier 84b and the sub-pixel 90 must be narrowed.
  • the sub-pixel 70 is arranged so that the horizontal direction (row direction) is the longitudinal direction, and each pixel constituting the color image is arranged in the vertical direction (column direction).
  • a configuration (hereinafter referred to as “horizontal pixel arrangement configuration”) in which three subpixels 70, which are adjacent to each other in the direction (R), G subpixel, and B subpixel, are also proposed (for example, FIG. (See 7 (b)).
  • the parallax barrier 54b, the sub-pixel 70, and the sub-pixel 70 are compared to the conventional configuration in which the sub-pixels are arranged so that the vertical direction is the longitudinal direction (hereinafter referred to as “vertically long pixel arrangement configuration”). Since the interval dl can be made relatively large, it is possible to prevent the right and left images from being reflected without requiring high processing accuracy.
  • the number of scanning signal lines required to obtain the same resolution is increased as compared with the vertically long pixel arrangement configuration.
  • the aperture ratio in the liquid crystal panel is lowered, and the circuit scale of the scanning signal line driving circuit is increased.
  • the present invention is a display device such as a DV liquid crystal display device or a 3D liquid crystal display device that displays different images for a plurality of viewpoints, and suppresses a decrease in aperture ratio and does not require high processing accuracy. It is an object to provide a display device that can prevent reflection of left and right images.
  • the first aspect of the present invention is:
  • a plurality of data signal lines extending in the column direction
  • a plurality of scanning signal lines that intersect the plurality of data signal lines and extend in the row direction; and a plurality of sub signal lines arranged in a matrix corresponding to the intersections of the plurality of data signal lines and the plurality of scanning signal lines, respectively.
  • a pixel forming portion A scanning signal line driving circuit for driving the plurality of scanning signal lines so that the plurality of scanning signal lines are sequentially selected;
  • a data signal line driving circuit for applying a plurality of data signals representing an image to be displayed to the plurality of data signal lines;
  • Each sub-pixel forming unit captures a signal on a corresponding data signal line when a scanning signal line passing through a corresponding intersection is selected
  • Each pixel of the image to be displayed is formed by a predetermined number of sub-pixel forming units that are adjacent to each other in the column direction and connected to the same data signal line.
  • the data signal line driving circuit includes:
  • the same pixel signal group consisting of signals corresponding to the data signals to be taken in by the predetermined number of sub-pixel forming portions, and the same pixel scanning signal line group also including scanning signal power passing through the intersection corresponding to the predetermined number of sub-pixel forming portions.
  • a holding circuit that holds and outputs while either is selected;
  • a second aspect of the present invention is the first aspect of the present invention
  • the apparatus further includes a parallax generation unit that generates parallax for the image formed by the sub-pixel forming unit.
  • a third aspect of the present invention is the second aspect of the present invention.
  • the plurality of sub-pixel forming portions are composed of a first sub-pixel forming group for forming the first image and a second sub-pixel forming group for forming the second image,
  • the parallax generation unit is allowed to display an image formed by the first sub-pixel formation group with respect to the first predetermined area and to be suppressed with respect to the second predetermined area.
  • the plurality of images are displayed so that display of an image formed by the second subpixel formation group is suppressed with respect to the first predetermined area and allowed with respect to the second predetermined area.
  • Each of the plurality of subpixel forming portions is arranged so that a longitudinal direction thereof is substantially perpendicular to a direction in which the slit extends.
  • a fourth aspect of the present invention is the third aspect of the present invention.
  • the first column that only has the power of the sub-pixel forming portion belonging to the first sub-pixel forming portion group and the sub-pixel belonging to the second sub-pixel forming portion group are alternately arranged in the row direction, and the slits extend in the column direction along the portion where the first column and the second column are adjacent to each other. It is characterized by that.
  • a fifth aspect of the present invention provides any one of the first to fourth aspects of the present invention.
  • the predetermined number of sub-pixel forming portions that should form each pixel of the image to be displayed are sub-pixel forming portions of the first, second, and third colors corresponding to the three primary colors for displaying a color image. It is characterized by comprising.
  • a sixth aspect of the present invention is the fifth aspect of the present invention.
  • the sub-pixel forming portions adjacent to each other in the row direction are sub-pixel forming portions of the same color.
  • a seventh aspect of the present invention provides a plurality of data signal lines extending in the column direction, a plurality of scanning signal lines intersecting with the plurality of data signal lines and extending in the row direction, and the plurality of scanning signal lines. Are arranged in a matrix corresponding to the intersections of the plurality of data signal lines and the plurality of scanning signal lines, respectively.
  • a plurality of subpixel forming sections each subpixel forming section capturing a signal on a corresponding data signal line when a scanning signal line passing through a corresponding intersection is selected, and each pixel of an image to be displayed
  • a display device formed by a predetermined number of sub-pixel forming units that are adjacent to each other in the column direction and connected to the same data signal line, a plurality of data signals representing the image to be displayed are supplied to the plurality of data signal lines.
  • the same pixel scanning signal line consisting of a scanning signal passing through an intersection corresponding to the predetermined number of sub-pixel forming portions, and the same pixel signal group consisting of signals corresponding to data signals to be taken in by the predetermined number of sub-pixel forming portions.
  • a holding circuit for holding and outputting while one of the groups is selected;
  • a plurality of data signal lines extending in the column direction, a plurality of scanning signal lines intersecting with the plurality of data signal lines and extending in the row direction, and the plurality of scanning signal lines are sequentially selected.
  • Each sub-pixel forming section, each sub-pixel forming section captures a signal on the corresponding data signal line when a scanning signal line passing through the corresponding intersection is selected, and each pixel of the image to be displayed is aligned in the column direction.
  • the same pixel scanning signal line consisting of a scanning signal passing through an intersection corresponding to the predetermined number of sub-pixel forming portions, and the same pixel signal group consisting of signals corresponding to data signals to be taken in by the predetermined number of sub-pixel forming portions.
  • a holding step for holding and outputting while one of the groups is selected;
  • the data signal to be applied to the same data signal line which is a data signal line passing through an intersection corresponding to the predetermined number of sub-pixel forming portions, is selected by the selection step.
  • the predetermined number of sub-pixel forming portions for forming each pixel of the image to be displayed are adjacent to each other in the column direction and connected to the same data signal line.
  • Data signals to be taken in by each of the predetermined number of sub-pixel forming units are applied to the same data signal lines in a time-division manner in conjunction with the sequential selection of the same pixel scanning signal line group. Therefore, in order to obtain the same resolution as compared with the conventional pixel arrangement configuration in which a predetermined number of sub-pixel forming portions for forming each pixel of the image to be displayed are adjacent in the row direction, the scanning signal line Although the number increases, the number of data signal lines decreases, so it is possible to suppress the decrease in aperture ratio.
  • the aperture ratio is ensured while ensuring the same resolution as compared with the conventional pixel arrangement configuration. Can be suppressed.
  • each sub-pixel forming portion for performing dual view display or stereoscopic display has a longitudinal direction substantially perpendicular to the direction in which the slits in the barrier layer extend. Therefore, the right and left images can be prevented from being reflected without requiring high processing accuracy.
  • the aperture ratio is maintained while ensuring the same resolution. Can be suppressed.
  • the first column which only has a subpixel formation part belonging to the first subpixel formation part group, and the subpixel formation belonging to the second subpixel formation part group
  • the second column which also has a force only in the portion, is alternately arranged in the row direction, and the slits in the barrier layer extend in the column direction along the portion where the first column and the second column are adjacent to each other, It is possible to realize a dual view display device that can prevent the left and right images from being reflected without requiring high processing accuracy.
  • the predetermined number of sub-pixel forming portions that should form the pixels of the image to be displayed are the first and second corresponding to the three primary colors for color image display.
  • the third color sub-pixel forming part force the reduction in aperture ratio is suppressed and high processing accuracy is achieved.
  • the sub-pixel forming portions adjacent to each other in the row direction are sub-pixel forming portions of the same color, it is easy to manufacture a color filter. As a result, it is possible to realize a dual-view color display device that can suppress the reduction of the aperture ratio and prevent the reflection of left and right images and the like without requiring high processing accuracy at a low cost.
  • FIG. 1 is a block diagram showing an overall configuration of a liquid crystal display device according to a first embodiment of the present invention.
  • FIG. 2 is a circuit diagram showing an equivalent circuit of one sub-pixel forming unit in the first embodiment.
  • FIG. 3 is a cross-sectional view for explaining the structure of the liquid crystal panel in the first embodiment.
  • FIG. 4 is a plan view (A) and a cross-sectional view (B) schematically showing a configuration for realizing dual view display in the first embodiment.
  • FIG. 5 is a diagram (A, B) showing a format of input data represented by an image signal to be supplied to the data driver in the first embodiment.
  • FIG. 6 is a block diagram showing a configuration example of a data driver in the first embodiment.
  • FIG. 7A is a diagram showing a truth table showing the operation of the input-side selector in the data driver according to the above configuration example
  • FIG. 7B is a diagram showing a truth table showing the operation of the output-side selector.
  • FIG. 8 is a timing chart (A to C) for explaining the operation of the input side selector in the data driver according to the above configuration example.
  • FIG. 9 is a timing chart (A to F) for explaining the operation of the output side selector for time division output in the data driver according to the above configuration example.
  • FIG. 10 is a timing chart (A to G) for explaining the operation (mainly on the input side) of the data driver according to the above configuration example in the two-system simultaneous input mode.
  • FIG. 11 is a timing chart (A to I) for explaining the operation (mainly on the output side) of the data driver according to the above configuration example in the two-system simultaneous input mode.
  • FIG. 12 is a timing chart (A to F) for explaining the operation (mainly on the input side) in the display mapping input mode of the data driver according to the above configuration example.
  • FIG. 13 is a block diagram showing a first modification of the data driver in the first embodiment.
  • FIG. 14 is a block diagram showing a second modification of the data driver in the first embodiment.
  • FIG. 16 is a diagram (A to C) showing a pixel arrangement of a conventional dual view liquid crystal display device. Explanation of symbols
  • TFT Thin film transistor
  • FIG. 1 is a block diagram showing the configuration of the liquid crystal display device according to the first embodiment of the present invention.
  • This liquid crystal display device can display different images with respect to two regions where viewpoints can be arranged, that is, a predetermined angular force tilted to the left or right as it is directed toward the display screen.
  • a DV (dual view) liquid crystal display device capable of displaying different images sometimes, a display control circuit 200, a data driver 300 as a data signal line driving circuit, and a gate driver as a scanning signal line driving circuit 400 and an active matrix type liquid crystal panel 600.
  • a display control circuit 200 a data driver 300 as a data signal line driving circuit
  • a gate driver as a scanning signal line driving circuit 400 and an active matrix type liquid crystal panel 600.
  • a liquid crystal panel 600 as a display unit in the liquid crystal display device includes image data Dvl for displaying a left image and image data for displaying a right image from a predetermined external video source (CPU or the like). Dv2 and a control signal TS for controlling the operation timing are received. Note that the original image for displaying the left image and the right image on the liquid crystal panel 600 is displayed in the horizontal direction so that it is displayed correctly by being displayed only in the odd or even columns in the display column of the liquid crystal panel 600. It is assumed that it has been compressed (halved) in the (display line direction). For example, when the display screen is composed of 640 columns and 480 rows, the original image for displaying the left image and the right image is composed of 320 columns and 480 rows.
  • the liquid crystal panel 600 includes three (3m) scanning signal lines Lg that are three times the number of horizontal scanning lines m in the image represented by the image data Dvl and Dv2, and the 3m scanning signal lines Lg. 2n data signal lines Ls intersecting with each other, and 3m x 2n subpixels formed corresponding to the intersections of these 3m scanning signal lines Lg and 2n data signal lines Ls, respectively Part Ps (l, l) to Ps (3m, 2n). Further, the liquid crystal panel 600 is provided in common to the pixel electrodes included in the sub-pixel forming portions Ps (l, l) to Ps (3m, 2n), and is opposed to the pixel electrodes with the liquid crystal layer interposed therebetween. Are provided with a common electrode.
  • 3m x 2n sub-pixel forming portions Ps (l, l) to Ps (3m, 2n) in the liquid crystal panel 600 are adjacent to the extending direction of the data signal line Ls, that is, the column direction, as shown in FIG.
  • the R subpixel, the G subpixel, and the B subpixel are arranged in a matrix in units of three subpixel formation portions, and the color image to be displayed on the liquid crystal panel 600 by the three subpixel formation portions.
  • Pixels that is, each pixel of the left image represented by the image data Dvl and the right image represented by the image data Dv2 (hereinafter, three sub-pixel forming portions corresponding to one pixel of the image to be displayed are Pixel forming portion “t ⁇ , indicated by a symbol“ Pix ”). Therefore, three scanning signal lines correspond to one display row.
  • the symbols “R”, “G”, and “B” attached to each sub-pixel forming portion Ps (i, j) are displayed by the sub-pixel forming portion Ps (i, j).
  • the display control circuit 200 receives the image data Dvl, Dv2 and the timing control signal TS sent from the outside, and converts the image signals corresponding to the image data Dvl, Dv2 respectively to the digital image signal DV1, DV1.
  • Data start pulse signal DSP, data clock signal DCK, latch strobe signal LS, gate start pulse signal GS P, and gate to output as DV2 and control the timing of displaying images on LCD panel 600 Outputs various signals including clock signal GCK.
  • the digital image signals DV1, DV2, the data start pulse signal DSP, the data clock signal DCK, and the latch strobe signal LS are data
  • the gate start pulse signal GSP and the gate clock signal GCK are supplied to the driver 300, and are supplied to the gate dryer OO.
  • the display control circuit 200 generates a polarity switching control signal for AC drive of the liquid crystal panel 600 based on the clock signal and the like, and this is used as the data driver 300 and a common electrode drive circuit (not shown). Supply. Since the polarity switching signal and the AC driving based on the polarity switching signal are not directly related to the present invention, the description thereof will be omitted below.
  • the data driver 300 Based on the digital image signals DV1 and DV2, the data clock signal DCK, the data start pulse signal DSP, the latch strobe signal LS, and the like, the data driver 300 sets the analog voltage for driving the liquid crystal panel 600 as data. Signals D (l), D (2),..., D (2n) are generated and applied to 2n data signal lines Ls in the liquid crystal panel 600, respectively.
  • the gate dry 400 is applied to each scanning signal line to sequentially select the scanning signal lines in the liquid crystal panel 600 by 1Z3 horizontal scanning period.
  • the application to the line is repeated with one vertical scanning period as the cycle.
  • the data signals D (1) to D (2n) based on the digital image signals DV1 and DV2 are applied to the data signal line Ls, and the scanning signals G (1) to G (3m) is applied to the scanning signal line Lg.
  • a common voltage signal is applied to the common electrode by a common electrode drive circuit (not shown).
  • the liquid crystal panel 600 is added to the liquid crystal layer.
  • the light transmittance is changed, and the left and right images represented by the image data Dvl and Dv2 received from the external video source are displayed. Depending on the viewing angle of the display screen, one of these images appears clearly bright and the other appears dark or completely invisible.
  • the liquid crystal panel 600 includes 2n data signal lines Ls connected to the data driver 300 and 3m scanning signal lines Lg connected to the gate driver 400, and the 2n data signal lines Ls and 3m
  • the scanning signal lines Lg are arranged in a grid pattern so that each data signal line Ls and each scanning signal line Lg intersect each other. Then, 3m ⁇ 2n sub-pixel forming portions Ps (1, l) to Ps (3m, 2n) are provided corresponding to the intersections of the 2n data signal lines and the 3m scanning signal lines Lg, respectively. ing.
  • each pixel of the color image to be displayed by the liquid crystal panel 600 is in the column direction (extension of the data signal line).
  • 3m x 2n sub-pixel forming parts Ps (l in the liquid crystal panel 600 are formed by a pixel forming part Pix consisting of three sub-pixel forming parts of R sub-pixel, G sub-pixel and B sub-pixel adjacent to each other in the direction).
  • , l) to Ps (3m, 2n) are arranged in a matrix with these three subpixel formation units as units (see Fig. 1).
  • each sub-pixel forming portion Ps (i, j) has a source terminal connected to the data signal line Ls passing through the corresponding intersection and a scanning signal passing through the corresponding intersection.
  • a thin film transistor (hereinafter abbreviated as “TFT”) 10 having a gate terminal connected to the line Lg, a pixel electrode Ep connected to the drain terminal of the TFT 10, and the above 3 m ⁇ 2n sub-pixels
  • Common electrodes (also referred to as “counter electrodes”) Ec provided in common in the formation portions Ps (l, l) to Ps (3m, 2n) and the 3m ⁇ 2n sub-pixel formation portions Ps (l, l) to Ps (3m, 2 ⁇ ), and a liquid crystal layer sandwiched between the pixel electrode ⁇ and the common electrode Ec.
  • the substrate is called a TFT substrate! /
  • the common electrode Ec and the substrate not shown, and a color filter and various optical compensation films (polarizing plates, etc.) are called CF substrates.
  • the liquid crystal capacitance Clc formed by the pixel electrode Ep, the common electrode Ec, and the liquid crystal layer sandwiched between them constitutes a pixel capacitance for holding a voltage corresponding to sub-pixel data.
  • an auxiliary capacitor is provided in parallel with the liquid crystal capacitor Clc, which should surely hold the voltage in the pixel capacitor.
  • the auxiliary capacitor is not directly related to the present invention, its description and illustration are omitted.
  • the scanning signal G (i) applied to the scanning signal line Lg which is V or shifted, becomes active, the scanning signal line Lg is selected, and the scanning signal line Lg is selected.
  • the TFT 10 connected to Lg (of each sub-pixel forming portion Ps (i, j)) becomes conductive, and the data signal D (j) passes through the data signal line Ls to the pixel electrode Ep connected to the TFT 10.
  • Applied (j l to 2n).
  • the voltage of the applied data signal D (j) (voltage based on the potential of the common electrode Ec) is transferred to the subpixel formation portion Ps (i, j) including the pixel electrode Ep.
  • FIG. 3 is a cross-sectional view schematically showing the structure of the liquid crystal panel 600 as described above.
  • the liquid crystal panel 600 includes a pair of transparent insulating substrates, a TFT substrate 66 and a CF substrate 56, and a liquid crystal layer 60 sandwiched between the TFT substrate 66 and the CF substrate 56.
  • the viewpoint (eyepoint) should be placed in front ( Display the image represented by the above image data Dvl and Dv2
  • Polarizing plates 68 and 55 are attached to the outer surfaces of the TFT substrate 66 and the CF substrate 56 in the liquid crystal panel 600 (main surfaces opposite to the side where the liquid crystal layer 60 is disposed).
  • the data signal lines Ls and the scanning signal lines Lg and the sub-pixel forming portions Ps (l, l) to Ps ( 3m, 2n) TFT circuit 64 including pixel electrode Ep and pixel electrode Ep are formed, and the inner surface of CF substrate 56 corresponds to the arrangement of R subpixel, G subpixel, and B subpixel shown in FIG.
  • the color filter 58 configured as described above is formed, and a transparent common electrode 59 is formed so as to cover the color filter 58.
  • a transparent parallax barrier substrate 52 is formed outside the CF substrate 56.
  • the parallax barrier layer 54 including the parallax barrier 54b is formed on the inner surface of the parallax barrier substrate 52 with a light-shielding metal or a resin.
  • the parallax barrier layer 54 has a slit 54s, and selectively blocks light that passes through the TFT substrate 66, the liquid crystal layer 60, the CF substrate 56, and the like from the knock light and moves forward.
  • a parallax is generated for an image formed by the sub-pixel forming portions Ps (l, l) to Ps (3 m, 2n) realized by the liquid crystal layer 60, the color filter 58, and the like. That is, the parallax barrier layer 54 has a parallax on the image formed by the sub-pixel forming portions Ps (l, l) to Ps (3m, 2n) so that different images are displayed for at least two viewpoints. It functions as a parallax generator that generates
  • FIG. 4 schematically shows a configuration of the liquid crystal panel 600 as described above, and FIG. 4A shows a configuration for a dual-view display (hereinafter abbreviated as “DV display”).
  • FIG. 4B is a cross-sectional view showing a configuration for DV display, and corresponds to a cross-sectional view taken along line XX in FIG. 4A.
  • FIG. 4 (A) and FIG. 4 (B) the configuration and operation for realizing DV display in the present embodiment will be described.
  • Ps (l, l) to Ps (3m, 2n) realized by the TFT circuit portion 64, the liquid crystal layer 60, the color filter 58, etc. without distinction.
  • each subpixel 70 is any of the R subpixel, the G subpixel, and the B subpixel.
  • the subpixel 70 with “R1” is an R subpixel for forming the left image
  • the subpixel 70 with “Gr” is the G subpixel for forming the right image. It is.
  • the sub-pixel 70 labeled “Xy” is referred to as “Xy sub-pixel”.
  • each sub-pixel 70 is arranged such that its longitudinal direction is the row direction (direction in which the scanning signal line Lg extends),
  • the sub-pixels 70 constituting each column are only sub-pixels for forming one of the left image and the right image. Consists of. Then, a column consisting only of sub-pixels for forming the left image and a column consisting of only the sub-pixels for forming the right image are exchanged. They are arranged with each other.
  • the parallax barrier layer 54 has slits 54 s extending in the direction perpendicular to the longitudinal direction of each sub-pixel 70, that is, the column direction (direction in which the data signal line Ls extends), and one slit 54 s for every two columns of the sub-pixel 70.
  • the distance dl between the parallax barrier 54b and the sub-pixel 70 corresponds to the distance between the color filter 58 and the parallax barrier 54b shown in FIG.
  • each subpixel 70 is arranged so that its longitudinal direction is the row direction (horizontal pixel arrangement configuration), and the slit 54s in the parallax barrier layer 54 is perpendicular to the longitudinal direction of each subpixel.
  • the slits 84s extend parallel to the longitudinal direction of each sub-pixel 90 even if the distance dl between the parallax nolia 54b and the sub-pixel 70 is increased, the left and right images are projected. It is hard to produce. Therefore, according to the above configuration, it is possible to prevent the left and right images from being reflected without requiring high processing accuracy.
  • the distance d2 between the viewing barrier 84b and the sub-pixel 90 is about 50 ⁇
  • the thickness of the glass as the CF substrate 56 is about 700.
  • special processing such as polishing of the glass substrate is required when manufacturing a conventional DV liquid crystal panel.
  • Such a special work is unnecessary or reduced, so that the manufacturing cost can be reduced.
  • the number of scanning signal lines Lg is three times that of the conventional vertical pixel arrangement (Fig. 16).
  • the number of data signal lines Ls is 1Z3 in the case of the conventional vertically long pixel arrangement configuration. It can be.
  • the data driver 300 in this embodiment needs to generate data signals D (1) to D (2n) so as to enable DV display (dual view display) according to the configuration of the liquid crystal panel 600. .
  • DV display dual view display
  • FIGS. 5A and 5B show the format of the input data represented by the digital image signal to be supplied to the data driver 300.
  • the left image data DaL and the right image data DaR are simultaneously supplied to the display control circuit 200 as image data Dvl and Dv2, and the image data
  • the digital image signal DV1 which is the signal of the left image represented by Dv 1 and the digital image signal DV2 which is the signal of the right image represented by image data Dv2 are simultaneously input to the data driver 300 (hereinafter this input format is referred to as “ DV2 simultaneous input format ”).
  • this input format is referred to as “ DV2 simultaneous input format ”).
  • image data in a format in which the left image data DaL and the right image data DaR are arranged in the row direction (horizontal direction) (hereinafter referred to as “combined image data” t, ), And an image signal represented by the combined image data may be input to the data driver 300 (hereinafter, this input format is referred to as “DV display mapping input format”).
  • This combined image data is image data consisting of 2 ⁇ 3 ⁇ m ⁇ n subpixel data arranged in a matrix of m rows ⁇ 2 ⁇ 3n columns, and the first half of each row is a subpixel representing the left image. The second half consists of sub-pixel data representing the right image.
  • the DV display mapping input type such 2 ⁇ 3 ⁇ m ⁇ n sub-pixel data are sequentially input to the data driver 300 as one digital image signal DV. If the left image data DaL and the right image data DaR have the same contents, Regardless of whether the input format is DV2 simultaneous input format or DV display mapping input format, normal display that is not DV display is performed (the same image is displayed for any viewpoint in front of the display screen). .
  • FIG. 6 is a block diagram showing a configuration example of the data driver 300 that can support both the DV2 simultaneous input format and the DV display mapping input format.
  • the data driver 300 includes an input side selector 302 as a first connection switching circuit, and six line memories functioning as a series-parallel converter, that is, a left image red line memory.
  • a latch circuit 306 as a holding means for holding a signal indicating pixel data
  • an output side selector 308 as a second connection switching circuit
  • a DZA conversion circuit 310 a DZA conversion circuit 310
  • an output buffer 312 are provided.
  • the digital image signal DV1 representing the left image is the red input signal R—Lin for the left image, the green input signal G—Lin, and the blue input signal B—Lin.
  • the red input signal R—Rin, the green input signal G—Rin, and the blue input signal B—Rin for the right image are input from the display control circuit 200 to the input side selector 302, respectively.
  • the input side selection control signal Sa is supplied from the display control circuit 200 to the input side selector 302 as a control signal for selecting the input format, and the output side selection control is performed as a control signal for switching the output signal in a time division manner.
  • Signals Sb and Sc are supplied from the display control circuit 200 to the output side selector 308.
  • the latch strobe signal LS is supplied from the display control circuit 200 to the latch circuit 306, and a plurality of reference voltages are supplied to the DZA conversion circuit 310 as well as a reference voltage generating circuit power (not shown).
  • the input side selection control signal Sa is also given to the line memories U304R1, 304G1, 304B1, 304Rr, 304Gr, and 304Br, and also serves as an enable signal for these line memories.
  • the input-side selector 302 is a first input terminal group for inputting the input signals R—Lin, G—Lin, and B—Lin that constitute the digital image signal DV1 representing the left image.
  • a second input terminal group Dl, El, F for inputting Al, Bl, C1 and input signals R Rin, G Rin, B Rin constituting the digital image signal DV2 representing the right image, respectively 1 and the first output terminal group 1Y1, 1Y2, 1Y3 for outputting image signals to the line memories 304R1, 304G1, 304B1 for the left image and the line memories 304Rr, 30 4Gr, 304Br for the right image, respectively.
  • a second output terminal group 1Y4, 1Y5, 1Y6 for outputting image signals is provided.
  • FIG. 7A shows a truth table showing the operation of the input side selector 302. This figure 7
  • the input side selector 302 uses the first and second input terminal groups A1 to F1 as the first image signals as they are. And output from the second output terminal group 1Y1 to 1Y6.
  • the input-side selector 302 sends the image signals given to the first input terminal groups A1 to C1 to the second output terminal groups 1Y4 to: The second input terminal group D1 to F1 is not used.
  • "X" indicates that the output signal is indefinite or invalid.
  • the input-side selector 302 receives a signal representing the left image and the right image in the DV2 system simultaneous input format (hereinafter, the operation mode at this time is referred to as “two systems simultaneous input mode”).
  • the input side selection control signal Sa as shown in Fig. 8 (B) is given and signals representing the left image and the right image are received in the DV display mapping format (hereinafter, the operation mode at this time is displayed as ⁇ Display In the “mapping input mode”, an input side selection control signal Sa as shown in FIG.
  • the input-side selector 302 operates in the two-system simultaneous input mode, and therefore, the input-side selection control signal Sa as shown in FIG. Given by.
  • the output-side selector 308 also has 2n block power (2n is the number of data signal lines Ls), and each block receives digital signals A2, B2, and C2 corresponding to three sub-pixel data. According to the truth table shown in (B), select one of those signals A2, B2, and C2 and output it as a digital signal Y. Therefore, when the output-side selector 308 receives the output-side selection control signals Sb and Sc as shown in FIG. 9B, the digital image signal input from the latch circuit 306 is shown in FIG. 9C. In this way, the output side selection control signals Sb and Sc are output in a time-sharing manner according to switching.
  • the switching order of the output side selection control signals Sb and Sc for the time division output corresponds to the horizontally long pixel arrangement configuration shown in FIGS. Also this The output side selection control signals Sb and Sc are switched every 1Z3 period of each horizontal scanning period, and the timing of the switching is the gate dryer O as shown in FIGS. 9 (D) to 9 (F). It is synchronized with the selection of the scanning signal line Lg by 0.
  • the input-side selector 302 is supplied with the input-side selection control signal Sa shown in FIG. 10 (A) and two digital image signals DV1, DV2 representing the left image and the right image.
  • the input side selector 302 receives the digital image signal R—Lin, G—Lin, B—Lin, R—Rin, G as shown in FIG.
  • FIGS. 10C and 10D show the input when the digital image signal corresponding to the second line of the image to be displayed (the left image and the right image) is input to the input side selector 302.
  • the line memo U304R1, 304G1, 304B1, 304Rr, 304Gr, 304Br holds the digital image signal corresponding to the first line of the image to be displayed. .
  • the line memos U304R1, 304G1, 304B1, 304Rr, 304Gr, and 304Br are digital image signals R-Lin, G-Lin, B_Lin, R- Rin, G—Rin, B—Rin are output in parallel for each line of the image to be displayed. That is, the three line memories 304R1, 304G1, and 304B1 function as a first serial / parallel converter that serially inputs a digital image signal representing the left image in units of pixels and outputs the left image in parallel for each row.
  • the other three line memories 304Rr, 304Gr, and 304 Br input the digital image signal representing the right image serially in pixel units and output the right image in parallel for each row of the right image. Function as.
  • the latch circuit 306 receives the digital image signal for one line output from the line memories 304R1, 304 Gl, 304B1, 304Rr, 304Gr, and 304Br to the normal output, and the latch shown in FIG. Latching based on the strobe signal LS, the digital image signal for one row is output as shown in Fig. 10 (F) and Fig. 10 (G) (Fig. 10 (F) and Fig. 10 (G) are output) This shows the digital image signal output to each of the blocks I and II of the side selector 308).
  • the latch circuit 306 is connected to three sub-pixel forming portions (R sub-pixel, G sub-pixel, and B sub-pixel) for forming one pixel of an image to be displayed during one horizontal scanning period.
  • R sub-pixel, G sub-pixel, and B sub-pixel sub-pixel forming portions
  • the output side selector 308 receives a digital image signal for one row from the latch circuit 306 as described above (FIGS. 11D and 11E), and the output side shown in FIG. 11C. Selection Control signals Sb and Sc are given.
  • the values of the output side selection control signals Sb, Sc (a combination of the value of the signal Sb and the value of the signal Sc) are switched every 1Z3 horizontal scanning period in each horizontal scanning period.
  • the output-side selector 308 should capture the three sub-pixel forming portions (R sub-pixel, G sub-pixel and B sub-pixel) that form each pixel in one row of the image to be displayed (left image and right image).
  • Fig. 11 (G) shows the digital image signals output from blocks I and II of the output selector 308, respectively. The order in this time-division output corresponds to the horizontally long pixel arrangement configuration shown in FIGS.
  • the output side selection control signals Sb and Sc are switched in synchronization with the selection of the scanning signal line Lg by the gate driver 400. Therefore, the output-side selector 308 switches the output signal between the same pixel signal groups in conjunction with the sequential selection of the scanning signal line Lg in the liquid crystal panel 600.
  • the eight conversion circuit 310 converts the digital image signal Y output from the output-side selector 308 (each block thereof) into an analog voltage signal based on a plurality of reference voltages supplied from a reference voltage generation circuit (not shown). Convert.
  • the analog voltage signal thus obtained is output from the data driver 300 as data signals D (1) to D (2n) for one row via an output buffer 312 configured by a voltage hollow or the like as impedance conversion means. It is output as shown in Fig. 11 (H) and Fig. 11 (1).
  • the DZA conversion circuit 310 and the output buffer 312 constitute a signal generation output circuit that generates and outputs a data signal D (j) based on the digital image signal Y from the output side selector 308.
  • the same pixel signal group xRy—L, xGy_L, xBy is connected to the data signal line Ls connected to the sub-pixel forming portion where each pixel of the left image is to be formed in the liquid crystal non-channel 600.
  • Data signal is applied in time division to L, and the same pixel signal group xRy—R, xGy_R, xBy—R is connected to the data signal line Ls connected to the sub-pixel formation part that should form each pixel of the right image.
  • the TFT 10 becomes conductive, and the data passes through the intersection corresponding to the sub-pixel formation portion P s (i, j).
  • the data signal D (j) of the signal line Ls is taken in as subpixel data, and a voltage corresponding to the subpixel data is held in the pixel capacitor Clc.
  • the light transmittance of the liquid crystal layer is controlled based on the subpixel data taken into each subpixel formation portion Ps (i, j), and this is combined with the action of the parallax barrier layer 54 as the parallax generation portion.
  • dual view display is realized.
  • the input-side selector 302 is supplied with the input-side selection control signal Sa shown in FIG. 12 (A), and the left image data DaL and the right image data as shown in FIG. 5 (B). DaR aligned in the row direction
  • a digital image signal DV corresponding to the combined image data of the equation is converted into serial image in units of ij pixels from the input terminal group Al, Bl, C1 as digital image signals R_Lin, G_Lin, B_Lin shown in Fig. 12 (B). Entered.
  • the input-side selector 302 in the first half of each horizontal scanning period, the digital image signal xR y_L, xGy_L, xBy— L is output from the first output terminal group 1Y1 ⁇ : LY3 is supplied to the line memories 304R1, 304G1, 304B1, respectively, and in the second half of each horizontal scanning period, digital image signals representing the right image xRy—R, xGy_R, xBy—R are output from the second output terminal group 1 Y4 ⁇ : LY6, respectively, and supplied to the line memories 304Rr, 304Gr, 304Br.
  • the line memories 304R1, 304G1, 304B1 capture and hold the digital image signal supplied from the input side selector 302 in the first half of each horizontal scanning period
  • the line memories 304Rr, 304Gr, 304Br In the second half of the scanning period, the digital image signal supplied from the input side selector 302 is captured and held.
  • FIGS. 12B and 12C show the signals on the input side and the output side when the digital image signal corresponding to the second line of the image to be displayed is input to the input side selector 302.
  • the line memos U304R1, 304G1, 304B1, 304Rr, 304Gr, and 304Br hold the digital image signal corresponding to the first line of the image to be displayed.
  • “X” indicates an invalid or indefinite signal value.
  • the digital image signals xRy—L, xGy_L, and xBy—L representing the left image are represented by line memories 304R1, 304G1, 304B1, and the right image, each of which is manually acquired in ij pixels.
  • Digital image signals xRy— R, xGy_R, xBy— R are serially input in units of subpixels, and line memories 304Rr, 304Gr, 304Br output these image signals in parallel for each row of the image to be displayed. To do. That is, as in the two-line simultaneous input mode described above, the three line memories 304R1, 304G1, and 304B1 display the left image.
  • the latch circuit 306 receives one line of digital image signals output from the line memory 304R1, 304G1, 304B1, 304Rr, 304Gr, 304Br force to the NORENORE. Based on the latch strobe signal LS shown in 12 (D), the digital image signal for one row is output as shown in FIGS. 12 (E) and 12 (F).
  • the output side selector 308, the DZ A conversion circuit 310, and the output buffer 312 operate in the same manner as in the two-system simultaneous input mode described above (see FIG. 11), and the same data signal D (1) to D (2n) is output from the data driver 300.
  • the data signal line Ls connected to the sub-pixel forming portion where each pixel of the left image is to be formed is time-divided into the same pixel signal group xRy—L, xGy_L, xBy—L.
  • the data signal is applied to the data signal line Ls connected to the sub-pixel forming part where each pixel of the right image is to be formed, and the data signal is applied to the same pixel signal group xRy—R, xGy_R, xBy—R in a time division manner.
  • a horizontal pixel arrangement configuration that is higher than the conventional vertical pixel arrangement configuration and that can prevent left and right images from appearing without requiring processing accuracy is employed.
  • the number of scanning signal lines is three times as many as the number of display rows.
  • 3 lines compared to the conventional vertical pixel arrangement (Fig. 16) are required.
  • Double the number of scanning signal lines Lg is provided in the liquid crystal panel 600.
  • the three sub-pixel forming portions are connected to the same data signal line Ls (FIG. 1).
  • the same pixel signal group xRy—L, xGy_L is connected to the data signal line Ls connected to the sub-pixel forming unit that should form each pixel of the left image.
  • a data signal is applied to xBy—L in a time-sharing manner, and the same pixel signal group xRy—R, xGy_R, xBy—is connected to the data signal line Ls connected to the sub-pixel forming portion that should form each pixel of the right image.
  • the input data format is the DV2 system simultaneous input format (FIG. 5 (A)) and the DV display.
  • the DV display LCD panel 600 (with a horizontal pixel arrangement with a reduced number of data signal lines to suppress a decrease in aperture ratio) Data signal line Ls) can be driven.
  • the output-side selector 308 for time-division output for the same pixel signal group is arranged in front of the DZA conversion circuit 310.
  • the output-side selector The 308b may be constituted by an analog switch or the like, and may be arranged at the subsequent stage of the DZA conversion circuit 310 as shown in FIG.
  • the configuration in which the output side selector 308 is arranged in front of the DZA conversion circuit 310 has the advantage that the scale of the DZA conversion circuit 310 can be reduced.
  • each block in the output-side selector 308 has one terminal that outputs a signal Y selected from the same pixel signal group A2, B2, and C2.
  • each block in the output-side selector 308 may output three signals Yl, Y2, Y3 from three output terminals. .
  • the output buffer 312 outputs three signals Rj, Bj, Gj as shown in FIG. 15 (H) and FIG.
  • the three output terminals of the data driver 300 are connected to one data signal line of the liquid crystal panel 600.
  • the three signals Rj, Gj, and Bj as the data signal D (j) are substantially the same signal. Therefore, the three output terminals from which the signals Rj, Gj, and Bj are output are connected to one data signal line (jth data signal line) Ls in the liquid crystal panel 600.
  • a configuration in which the parallax barrier layer 54 as the parallax generation unit is arranged on the front side of the liquid crystal panel 600, that is, a front parallax barrier method is adopted (FIG. 3).
  • a rear parallax barrier method (see, for example, FIG. 4 of Patent Document 1) may be employed.
  • the liquid crystal display device is, for example, a so-called driver (full) monolithic type or partial driver monolithic type in which all or part of various drive circuits and the like are integrally formed on a glass substrate together with a pixel circuit. It may be a liquid crystal display device. Further, in the above embodiment, the liquid crystal panel in which the pixel electrode and the counter electrode are formed on different substrates has been described as an example. However, these electrode structures are not limited to, for example, the IPS On Plane Switching) method, The pixel electrode and the counter electrode may be formed on the same substrate. Furthermore, the present invention is not limited to the liquid crystal display device, but can be applied to an active matrix type DV display device other than the liquid crystal display device.
  • a DV display device that displays different images for two users is taken as an example, but binocular parallax is given to one user based on the same principle.
  • the present invention is also applicable to a display device that generates a three-dimensional display by generating the above.
  • a display device other than a DV display device when a pixel of a color image is formed by an R subpixel, a G subpixel, and a B subpixel which are in a horizontally long pixel arrangement configuration and are adjacent in the column direction. If so, the present invention can be applied.
  • the present invention is applied to a display device for displaying different images for at least two viewpoints and a drive circuit thereof, and generates binocular parallax for one user. It is suitable for a liquid crystal display device that displays three-dimensional images and a liquid crystal display device that displays different images for two users.

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Abstract

La présente invention a pour objet de supprimer la réduction du rapport d'ouverture et d'éviter les réflexions des images dissymétriques ou semblables sans avoir besoin d'une forte précision de finition dans un appareil d'affichage qui affiche des images différentes sur une pluralité de points de vue. Dans un panneau d'affichage à cristaux liquides avec un large placement de pixels capable de réaliser un double affichage, trois sous-pixels (sous-pixel R, sous-pixel V, sous-pixel B) formant chaque pixel d'une image couleur à afficher sont placés l'un près de l'autre en colonne, tout en étant reliés à la même ligne de signal de données. Un pilote de données fait appel à un sélecteur côté sortie (308) pour commuter les signaux de données qui doivent être appliqués aux lignes de signaux de données dans ce panneau à cristaux liquides, parmi les signaux correspondant aux données devant être traitées par les trois sous-pixels, chaque tiers à chaque intervalle de balayage horizontal. L'invention s'applique à un appareil d'affichage à cristaux liquides ou similaire capable de réaliser un double affichage ou un affichage en trois dimensions.
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WO2007110993A1 (fr) * 2006-03-24 2007-10-04 Sharp Kabushiki Kaisha Convertisseur de format de signal et procédé de conversion de format de signal destinés à une utilisation avec un appareil d'affichage matriciel
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US9171520B2 (en) 2011-11-21 2015-10-27 Boe Technology Group Co., Ltd. Array substrate, method for controlling the same and display panel including the array substrate
CN106133812A (zh) * 2014-03-31 2016-11-16 索尼公司 显示设备、显示模块和显示构件
CN113097371A (zh) * 2021-03-31 2021-07-09 厦门天马微电子有限公司 一种显示面板及其制备方法、显示装置
CN116034418A (zh) * 2021-07-02 2023-04-28 京东方科技集团股份有限公司 显示面板、显示装置及显示装置的驱动方法

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WO2007110993A1 (fr) * 2006-03-24 2007-10-04 Sharp Kabushiki Kaisha Convertisseur de format de signal et procédé de conversion de format de signal destinés à une utilisation avec un appareil d'affichage matriciel
JP2009169330A (ja) * 2008-01-21 2009-07-30 Seiko Epson Corp 電気光学装置、電気光学装置の製造方法及び電子機器
CN102654701A (zh) * 2011-11-21 2012-09-05 京东方科技集团股份有限公司 阵列基板、显示面板及显示设备
WO2013075558A1 (fr) * 2011-11-21 2013-05-30 京东方科技集团股份有限公司 Substrat de réseau, procédé de commande associé et panneau d'affichage contenant ledit substrat
CN102654701B (zh) * 2011-11-21 2014-06-11 京东方科技集团股份有限公司 阵列基板、显示面板及显示设备
US9171520B2 (en) 2011-11-21 2015-10-27 Boe Technology Group Co., Ltd. Array substrate, method for controlling the same and display panel including the array substrate
CN106133812A (zh) * 2014-03-31 2016-11-16 索尼公司 显示设备、显示模块和显示构件
CN113097371A (zh) * 2021-03-31 2021-07-09 厦门天马微电子有限公司 一种显示面板及其制备方法、显示装置
US11843081B2 (en) 2021-03-31 2023-12-12 Xiamen Tianma Micro-Electronics Co., Ltd. Display panel and fabrication method, and display device for displaying multiple images at different viewing angles
CN116034418A (zh) * 2021-07-02 2023-04-28 京东方科技集团股份有限公司 显示面板、显示装置及显示装置的驱动方法
EP4339934A4 (fr) * 2021-07-02 2024-05-22 BOE Technology Group Co., Ltd. Panneau d'affichage, dispositif d'affichage, et procédé d'attaque du dispositif d'affichage
US12217638B2 (en) 2021-07-02 2025-02-04 Boe Technology Group Co., Ltd. Display panel, display device, and method for driving display device
CN116034418B (zh) * 2021-07-02 2025-03-25 京东方科技集团股份有限公司 显示面板、显示装置及显示装置的驱动方法

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