WO2007120304A2 - Correction de proximite optique sur des plateformes materielles ou logicielles avec des unites de traitement graphique - Google Patents

Correction de proximite optique sur des plateformes materielles ou logicielles avec des unites de traitement graphique Download PDF

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Publication number
WO2007120304A2
WO2007120304A2 PCT/US2006/061518 US2006061518W WO2007120304A2 WO 2007120304 A2 WO2007120304 A2 WO 2007120304A2 US 2006061518 W US2006061518 W US 2006061518W WO 2007120304 A2 WO2007120304 A2 WO 2007120304A2
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Prior art keywords
processing unit
procedures
graphics processing
optical proximity
proximity correction
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WO2007120304A3 (fr
Inventor
Ilhami H. Torunoglu
Ahmet Karakas
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Gauda Inc
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Gauda Inc
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes

Definitions

  • the present invention relates to the field of electronic design automation and, in particular, to improved techniques for performing optical proximity correction.
  • the manufacture of integrated circuits strives to place ever smaller features onto a given area of the integrated circuit chip.
  • One challenge encountered in this effort to fabricate smaller features is the diffraction of the light used in photolithography. That is, the quality and fidelity of the micro lithography stage of very large scale integrated (VLSI) circuit chip production depends on the wavelength of the light source and the size of the features to be printed.
  • VLSI very large scale integrated
  • Recent sub-wavelength lithography approaches aim to use wavelengths that are larger than the minimum feature size to generate the images, (e.g., light with a wavelength of 193 nanometers is being used to generate features with dimensions of 90, 65, or 45 nanometers).
  • This approach requires methods for the correction of degradations and distortions in the final pattern caused by light diffraction. That is, the photolithography mask used to generate the desired circuit pattern includes structures that anticipate and, at least partially correct for, the imperfections arising from striving to fabricate small features.
  • OPC optical proximity correction
  • the present invention relates generally to the field of manufacturing integrated circuits and, more particularly, to using optical proximity correction (OPC) to improve the masks used for the printing of microelectronic circuit designs.
  • OPC optical proximity correction
  • the present invention relates to the execution of OPC techniques on hardware or software platforms, or a combination of these, utilizing specialized processing units.
  • the present invention relates to systems and methods for the execution of OPC algorithms on hardware or software platforms, or combination, with specialized processing units.
  • spatial domain OPC computations are executed on a hardware or software system, or combination, comprising one or more specialized processing units.
  • the specialized processing units include central processing units (CPUs), graphical processing units (GPUs), physics processors, cell processors, digital signal processors (DSPs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and the like.
  • Portions of the OPC computational task may be transformed into the form of mathematical manipulations on matrices and vectors.
  • GPUs may be particularly well suited to performing such operations on matrix and vector data.
  • the GPU or GPUs may operate on the data until the result converges on the target model within a predetermined error limit.
  • the operations may include changing the shapes of mask features and may include a detailed model of the illumination and optics systems used for exposing the pattern in the photoresist layer.
  • the final data may be transformed back to the original data format and exported for generation of the mask used to print the pattern on the semiconductor device.
  • GPUs will be used as an example of a specialized processor, but this is not intended to limit the scope of the teaching of the present invention to GPUs.
  • the present invention may utilize any of the specialized processors mentioned previously, and other substantially similar processors as understood by those having ordinary skills in the art and as similar or related processors may be developed later.
  • the invention is includes: a computing system having at least one central processing unit and at least one graphics processing unit; a user interface for interacting with the computer system; a computer readable medium including data describing the size and placement of features to be formed on a photolithography exposure mask used to manufacture semiconductor devices; a computer readable medium including optical proximity correction calculation procedures for acting upon the data, where at least a portion of the optical proximity correction calculation procedures are executed using the graphics processing unit; and output devices for displaying the results of applying the optical proximity correction calculation procedures executed using the graphics processing unit upon the data.
  • the invention is a method including: providing a system having at least one central processing unit and at least one graphics processing unit; separating an optical proximity correction process into tasks depending on a type of computation required; allocating the tasks of the optical proximity correction process to the central processing unit or the graphics processing unit; and delivering output of the central processing unit and the graphics processing unit as a result of the optical proximity corrections process.
  • the invention is includes: a computing system including a number of nodes, where each node includes at least one of at least one central processing unit or at least one graphics processing unit; an interface to couple the nodes together; a user interface for interacting with the computer system; a computer readable medium including data describing the size and placement of features to be formed on a photolithography exposure mask used to manufacture semiconductor devices; and a computer readable medium including optical proximity correction calculation procedures for acting upon the data, where at least a portion of the optical proximity correction calculation procedures are executed using the graphics processing unit in one of the nodes.
  • the interface may be at least on of a PCI Express bus, AGP bus, front side bus, Ethernet, the Internet, or other interface that facilitates the transfer of data in any form including serial or parallel.
  • the computer readable medium having data describing the size and placement of features to be formed on a photolithography exposure mask used to manufacture semiconductor devices may be directly connected to one of the nodes and a portion of the data are passed through the interface to at least one other node.
  • the direct connection may be by way of a different interface than how the nodes are connected.
  • the direct connection may be by an IDE, SATA, or USB interface.
  • the computer readable medium having optical proximity correction calculation procedures for acting upon the data is directly connected to one of the plurality of nodes, and at least a portion of the optical proximity correction calculation procedures are executed using the graphics processing unit on a different node from which the optical proximity correction calculation procedures are directly connected.
  • the computer readable medium having optical proximity correction calculation procedures for acting upon the data is directly connected to one of the nodes, and at least a portion of the optical proximity correction calculation procedures are executed using the graphics processing unit of the node to which the optical proximity correction calculation procedures are directly connected.
  • the system may include a computer readable medium having optical proximity correction calculation procedures to split given layout information into two-dimensional subregions, where these subregion overlap with each other. There may be a computer readable medium having optical proximity correction calculation procedures to transfer the given layout information split-up into two-dimensional subregions to two or more nodes of the system. A computer readable medium having optical proximity correction calculation procedures executing on the two or more nodes may operate on the given layout information split-up into two- dimensional subregions.
  • a computer readable medium having optical proximity correction calculation procedures to combine results from a first node and a second node on the given layout information split-up into two-dimensional subregions.
  • the optical proximity correction calculation procedures may combine results by stitching together the results by removing the overlapping regions.
  • Figure IA is a schematic representation of a typical pattern printed on a typical mask.
  • Figure IB shows the resulting pattern developed in the photoresist without OPC.
  • Figure 2A is a schematic representation of a typical OPC-corrected pattern printed on a typical mask.
  • Figure 2B shows the resulting pattern developed in the photoresist.
  • Figure 3 is a schematic representation of a typical implementation for some OPC procedures on a typical commercial GPU.
  • Figure 4 depicts an illustrative computer system pertaining to various embodiments of the present invention.
  • Figure 5 shows partitioning of layout data and where each partition has overlapping regions from adjacent partitions.
  • the invention can be readily utilized in the improvement of OPC methods used in the manufacture of semiconductor devices.
  • Structures arising in the manufacture of microelectronic devices are typically formed by creating a pattern of the desired structure in a layer of photoresist deposited over the material in which the desired structure is to be formed.
  • the pattern in the photoresist is created by exposing the photoresist to light through a patterned exposure mask.
  • the exposed photoresist serves as a physical mask during subsequent etch step or steps where the pattern in the photoresist is transferred to the underlying material.
  • Distortions and degradations in the final structure arise from a combination of factors including light source variations, optical proximity effects, development process nonuniformities, and etch process nonuniformities, among others.
  • the total amount of energy deposited in a given volume of photoresist during the exposure or printing step will determine if that volume remains or is removed during the subsequent development process.
  • the image features being printed on current microelectronic devices may be much smaller than the wavelengths of light being used to print the features, (e.g., light with a wavelength of 193 nanometers is being used to generate features with dimensions of 90, 65, or 45 nanometers and below).
  • the distortions may cause errors such as line thinning, end shortening, line thickening, clipping, and the like.
  • Figures IA and IB illustrate a typical example where the feature on the exposure mask is formed with the same size and shape as the desired structure on the chip (figure IA). Due to the distortions described previously, the resulting pattern may not faithfully reproduce the pattern in the exposure mask as illustrated in figure IB. The distortions in this particular example have caused the final pattern to be shorter, thinner, and poorly controlled.
  • Various methods of OPC may be used to improve the fidelity of the final pattern transferred to the target material.
  • the pattern that is formed on the exposure mask may be altered to compensate for various systematic distortions.
  • One such method involves the use of serifs to augment the pattern in areas where the distortions cause feature shortening, thinning, and the like.
  • a serif is understood to be a small feature that may be placed at a corner or vertex of a main feature. The serif may be "positive" in that it adds area to the main feature or it may be
  • Figures 2A and 2B illustrate a typical example of the use of both positive and negative serifs (figure 2A) on the exposure mask to alter the feature.
  • Figure 2B illustrates the resulting structure realized on the chip as a result of the successful use of this OPC technique.
  • the goal of the OPC process is to calculate, improve, and ideally to optimize every feature on the exposure mask so that the resulting structure realized on the chip meets the design and performance requirements of the circuit.
  • the chip has billions of transistors, each with many fine structures, the computational requirements for OPC can be very large.
  • the frequency domain (FD) OPC computations use Fourier transform techniques to calculate the deformation of the features on the exposure mask to realize the desired structure on the chip. There are typically several steps to this method:
  • FD-I FD-I .
  • the layout is pixilated (e.g., digitized as a pattern of pixels) and transformed into the 2-dimensional frequency domain.
  • FD-4 A 2-dimensional inverse filtering is applied to transform the results of these calculations back from the frequency domain into the spatial domain.
  • the accuracy of the frequency domain OPC calculations increases as the number of points used increases. Many points must be used to include all of the local structures that may impact the distortion of the feature being optimized. However, each of these neighboring local structures must also be optimized. The ideal situation is to consider the entire chip within a single calculation. However, this also dramatically increases the computational requirement.
  • the spatial domain (SD) OPC calculations are based on the spatial properties of the features.
  • the edges and vertices of the features on the exposure mask, such as polygons or rectangles, are modified in an effort to minimize the difference between the actual structure realized using the corrected exposure mask and the desired structure. There are several steps to this method.
  • the candidate control points, or evaluation points, on the edges and vertices are determined based on current design rules.
  • An example of a flow is:
  • EPE edge placement error
  • an edge fragment may be "pushed" or
  • the spatial domain OPC methods enjoy several benefits over the frequency domain methods.
  • the light effects are generally localized to the features in the immediate vicinity of the feature under consideration. Therefore, the size of a specific calculation may be smaller.
  • An alternative hardware configuration includes a cooperative collection of specialized processing units where each processing unit may be well suited for a specific type of computation.
  • This hardware configuration will be defined here as a "heterogeneous configuration" meaning that the various computational tasks are executed by different, typically specialized, processors.
  • GPUs are designed specifically for high throughput on specialized types of problems found in graphics processing that require a large number of arithmetic calculations with a relatively small number of memory access steps.
  • Other specialized processors may be designed to handle other types of data or computational problems. Allocating the various portions of the OPC computations to specialized processors may improve the throughput, increase the efficiency, lower the cost, and improve the results of the computation.
  • GPUs may be designed for fast graphics processing.
  • the data may be organized into a stream where a stream is an ordered set of data of the same data type.
  • Operations, procedures, methods, algorithms, and the like that may be applied to entire streams of data are typically called kernels. Kernels are very efficient because they depend only on their input. Internal computations within the kernel are independent of other elements of the stream. Therefore, GPUs may be designed for parallel processing, memory efficiency, and high throughput for specific problems.
  • GPUs typically have hardware blocks that may be specifically designed for certain types of problems (e.g., specific kernels may be implemented in hardware). As an example, hardware blocks may be designed to implement various types of vector or matrix computations, or both. As an example, graphics data is typically four-dimensional referring to the channel value of the red, green, and blue pixels (referred to as RGB) and the opacity value (typically referred as alpha or A). Therefore, GPUs have been designed to process four-dimensional (RGBA) data very quickly and very efficiently.
  • RGB channel value of the red, green, and blue pixels
  • alpha or A alpha
  • CPU-based approaches to improve the OPC procedures typically employ multi-CPU systems as mentioned previously. Such approaches typically have attempted to increase the computational efficiency by dividing the computation into parallel parts at the task level. However, they are not able to exploit additional parallelism at the instruction level due to their general purpose design.
  • OPC calculations are inherently graphics problems.
  • graphics data in the form of rectangles or polygons may be sent by one or more CPUs to one or more GPUs.
  • the GPUs may be designed to efficiently implement one or more kernels for the efficient execution of the steps of the OPC method described previously.
  • the following functions may be implemented with task level parallelism:
  • step SD-I Cost functions
  • step SD-2 Allocation of fragment tests such as depth tests for area query and tagging of edges and edge fragments (step SD-2).
  • fragment tests such as depth tests for area query and tagging of edges and edge fragments (step SD-2).
  • Other common fragment tests include scissor tests, alpha tests, stencil tests, blending tests, dithering tests, logical operations, and the like.
  • vertex shaders or vertex processors are a programmable unit that operates on incoming vertex values and their associated data. Rasterization is the conversion of both geometric and pixel data into fragments. Pixel shaders or fragment processors are programmable units that operate on fragment values and their associated data. Depth tests are, for each pixel, the depth buffer keeps track of the distance from the viewpoint and the object occupying that pixel. Then, if the specified depth test passes, the incoming depth value replaces the value already in the depth buffer.
  • Texture maps or image maps are rectangular arrays of data (e.g., color data, luminance data, color and alpha data, and the like). Texture interpolation is mathematical interpolation between texture map or image map data. [69] Typically, the following special hardware functions may be implemented for searching and region query:
  • MIMD Multiple-input multiple-data
  • a depth processor is a programmable unit that operates on incoming fragment or pixel values and their associated data.
  • Video processor is a processor that performs video decoding or encoding operations on video data.
  • the processor may be of a single-instruction multiple-data
  • SIMD SIMD
  • MIMD multiple-instruction multiple-data
  • FIG. 3 is a schematic representation of typical procedures for performing a typical OPC method on commercial GPU.
  • the specific case illustrated uses an Nvidia GeForce® GPU processor, but the present invention may generally apply to any commercial GPU or similar device.
  • Various operations of an OPC flow are executed using a graphics processor 300. Some steps of an OPC flow include a geometric operation 309, rectangle fragmentation 310, intensity calculation 311, area search 312, and placement error or edge placement error (EPE) calculation
  • Geometric operations are. Rectangle fragmentation operations are. Intensity calculations are. Area search are. Placement error or EPE calculations are.
  • the graphics processor may be a single integrated circuit or multiple integrated circuits.
  • 306, 307, and 308 may reside on a single integrated circuit. Or any combination of components may reside on one integrated circuit and other components reside on one or more other integrated circuits. Also a single integrated circuit may include one or more graphics processor cores.
  • a graphics processor 300 there are one or more vertex processors 301, which are connected to a triangle setup block 302.
  • a vertex processor is responsible for running the vertex shaders.
  • the input for a vertex shader is the vertex data, namely its position, color, normals, an so forth.
  • a vertex shader one can write code for tasks such as: vertex position transformation using the model view and projection matrices; normal transformation, and if required its normalization; texture coordinate generation and transformation; lighting per vertex or computing values for lighting per pixel; and color computation.
  • the triangle set up block does.
  • the triangle set-up block is connected to a shader instruction dispatch 303.
  • the shader instruction dispatch does.
  • the shader instruction dispatch is connected to one or more fragment processors 304.
  • the fragment processor is where the fragment shaders run. This unit is responsible for operations like: computing colors, and texture coordinates per pixel; texture application; fog computation; and computing normals if one wants lighting per pixel.
  • the inputs for a fragment processor this unit are typically the interpolated values computed in the previous stage of the pipeline such as vertex positions, colors, normals, and so forth.
  • the fragment processor is connected to a fragment crossbar 305.
  • the fragment crossbar does.
  • the fragment crossbar is connected to a stencil buffer 306.
  • the stencil does.
  • the stencil is connected to one or more memory partitions 307.
  • the graphics processor may have one or more video processors 308.
  • the video processor does.
  • the video processor is connected to. Any combination of the components shown in graphics processor 300 may included one integrated circuit.
  • a graphics processing unit integrated circuit may include a vertex processor unit and a fragment processor unit.
  • the graphics processing unit integrated circuit may include a vertex shader unit and a stencil buffer unit.
  • step SD-I the geometric operations and rectangle fragmentation
  • step SD-2 through SD-4 may map to the fragment processor and depth filter hardware blocks of the GPU.
  • EPE calculation may simply be referred to as placement error calculations, especially in embodiments of the invention where edges are not used.
  • Geometric operations may be performed in the CPU (outside the GPU), vertex processor, or fragment processor. Fragmentation operations may be performed in the CPU, vertex processor, or fragment processor. Intensity calculations may be performed in the fragment processor. Area search may be performed in the fragment processor or stencil. EPE calculations may be performed in the fragment processor or video processor. In OPC procedure, any combination of these operations may be performed with each other.
  • the fragment processor may perform the geometric operations, fragmentation operations, intensity calculations, area search, and EPE calculations.
  • the geometric operations and fragmentation operations may be performed by the CPU and the intensity calculations, area search, and EPE calculations may be performed in the GPU.
  • the geometric operations and fragmentation operations may be performed by the vertex processor of the GPU and the intensity calculations, area search, and EPE calculations may be performed by the fragment processor of the GPU.
  • the area search may be performed in the stencil buffer of the GPU.
  • the EPE calculation may be performed using the video processor.
  • Positions of geometries of the layout may be represented in the four-dimensional space (RGBA) format provided in the GPU.
  • RGBA four-dimensional space
  • a two-dimensional trapezoidal shape of the data is represented as four-channel data in the graphics processing unit.
  • the trapezoid may be a rectangle or square.
  • two opposite corners of a two-dimensional trapezoidal shape of the data is represented in a RGBA color space format in the graphics processing unit. For example, Xl will be R, Yl will be G, X2 will be B, and Y2 will be A.
  • the GPU will operate on the data stored in such a four-dimensional format.
  • X and Y coordinates for a corner, a width, and a height of a two- dimensional trapezoidal shape of the data is represented in a RGBA color space format in the graphics processing unit.
  • Xl will be R
  • Yl will be G
  • W will be B
  • H will be
  • the GPU will operate on the data stored in such a four-dimensional format.
  • X and Y coordinates for a corner, a change in X, and a change in Y of a two-dimensional trapezoidal shape of the data is represented in a RGBA color space format in the graphics processing unit.
  • Xl will be R
  • Yl will be G
  • delta X will be
  • the GPU will operate on the data stored in such a four-dimensional format.
  • X and Y coordinates for a corner, an angle, and a scalar of a two- dimensional trapezoidal shape of the data is represented in a RGBA color space format in the graphics processing unit.
  • Xl will be R
  • Yl will be G
  • theta will be B
  • r will be A.
  • the GPU will operate on the data stored in such a four-dimensional format.
  • There representations of OPC data in a GPU are merely examples of some representations that may be used. In other embodiments of the invention, other representation schemes may be used.
  • a system of the invention includes: a computing system having at least one central processing unit and at least one graphics processing unit; a user interface for interacting with the computer system; a computer readable medium including data describing the size and placement of features to be formed on a photolithography exposure mask used to manufacture semiconductor devices; a computer readable medium including optical proximity correction calculation procedures for acting upon the data, where at least a portion of the optical proximity correction calculation procedures are executed using the graphics processing unit; and output devices for displaying the results of applying the optical proximity correction calculation procedures executed using the graphics processing unit upon the data.
  • the graphics processing unit may include a vertex processor unit and a fragment processor unit.
  • the graphics processing unit may include a vertex shader unit and a stencil buffer unit.
  • a system of the invention may include multiple nodes which are connected with high speed interface or connections between them. This interface may include, for example, a PCI Express bus, AGP bus, front side bus, Ethernet, or the Internet, or a combination of these. Each node has one or multiple CPUs or one or more GPUs, or any combination of CPU and GPUs. Each node may or may not be equipped with a secondary storage area such as hard disk floppy, CD writer, or other. OPC software of the invention may be run on any of the machines. [93] For example, there may be a master program that runs on any subset of the nodes of the system. The master program may be executed on only one of the nodes.
  • the master program may direct other nodes of the system to perform OPC calculations.
  • the master program may coordinate operations of the computing system.
  • the OPC procedures or data, or both, may be transferred from one node to any other node of the system. Results may then be passed back to the master program, where individual results are combined.
  • the graphics processing units and the optical proximity correction calculation procedures may include at least one of:
  • a procedure splits the given layout information into two-dimensional subregions, where these regions overlaps with each other. There may be multiple such procedures running on separate nodes of a system. This information, as well as whole or partial layout information, is sent to each node where the nodes perform OPC-related calculation. The results of the calculations are collected (such as at a single node) where the information is stitched together by removing the overlapping regions. Stitching may be performed using a single node or multiple nodes in parallel.
  • a procedure includes splitting a layout into a number of nonrectangular two-dimensional overlapping regions.
  • the method splits the layout into overlapping two-dimensional rectilinear or polygonal spaces, sending whole or portions of the region or regions to each node.
  • the method may perform OPC corrections (or reticle corrections) without sending or sharing any information between nodes. Portions or complete regional information may be provided to each node for parallel computation.
  • FIG. 5 shows partitioning of layout data and where each partition has overlapping regions from adjacent partitions.
  • the layout is divided or partitioned into a number of subregions.
  • each subregion is two dimensional.
  • a technique partitions a layout 503 into a number of regions or subregions.
  • each region is shown as been rectangular in this figure, each partition may have any shape such as square, trapezoid, any polygonal, or other.
  • the data in each two-dimensional subregion is operated on by one or more computing nodes of the system.
  • each node may include CPUs or GPUs, or both.
  • each node has a GPU which performs OPC calculations on a specific subregion of the layout. Calculations may be performed on a number of subregions in parallel, which will speed up the calculations. Generally, the greater the number of nodes, the faster the calculations may be performed since more calculations will be performed in parallel.
  • the output results are transferred back to a calling node (such as the node where a master program is running) or to another specific location. Then, one or more computing nodes will assembly the output results for the individual partitions together to provide the OPC calculation output for the complete layout data.
  • each subregion is sent to a node including some overlapping region data from adjacent partitions.
  • a subregion (see subregions 505 and 509) sent to a node will include overlap information from two adjacent sides.
  • subregion 507 sent to a node will include overlap information from three adjacent regions.
  • subregion 511 will include overlap information from four adjacent regions.
  • each node will be simply the output data for the subregion itself, without any overlap regions. Therefore, in this case, each node with have the overlap region as the input data, but not in the output data. This approach leads to more accurate results in the OPC calculations.
  • the computation of the lithography process simulation for OPC and RET purposes which includes the mask preparation related calculations, EAPSM and AAPSM related calculations such as electromagnetic field computation to take into account the thick mask effects, the chemical processes happening during lithography processes including the exposure process, the postbake process, the chemical amplification process, the development process all or partially computed in pixel shaders or in combination of pixel and vertex shaders.
  • Figure 4 depicts an illustrative computer system pertaining to various embodiments of the present invention.
  • the computer system includes a server 401, display 402, one or more input interfaces 403, and one or more output interfaces 404, all conventionally coupled by one or more buses 405. Examples of suitable buses include PCI-Express®, AGP, PCI, ISA, and the like.
  • the computer system may include any number of graphics processors.
  • the graphics processor may reside on the motherboard such as being integrated with the motherboard chipset.
  • One or more graphics processors may reside on external boards connected to the system through a bus such as an ISA bus, PCI bus, AGP port, PCI Express, or other system buses.
  • Graphics processors may on separate boards, each connected to a bus such as the PCI Express bus to each other and to the rest of the system. Further, there may be a separate bus or connection (e.g., Nvidia SLI or ATI CrossFire connection) by which the graphics processors may communicate with each other. This separate bus or connection may be used in addition to or in substitution for system bus.
  • the server 401 includes one or more CPUs 406, one or more GPUs 407, and one or more memory modules 412. Each CPU and GPU may be a single core or multiple core unit. Examples of suitable CPUs include Intel Pentium®, Intel CoreTM 2 Duo, AMD Athlon 64, AMD Opteron®, and the like. Examples of suitable GPUs include Nvidia GeForce®, ATI Radeon®, and the like.
  • the input interfaces 403 may include a keyboard 408 and a mouse 409.
  • the output interface 404 may include a printer 410.
  • the communications interface 411 is a network interface that allows the computer system to communicate via a wireless or hardwired network.
  • the communications interface 411 may be coupled to a transmission medium (not shown), such as a network transmission line, for example, twisted pair, coaxial cable, fiber optic cable, and the like.
  • the communications interface 411 provides a wireless interface, that is, the communication interface 411 uses a wireless transmission medium. Examples of other devices that may be used to access the computer system via communications interface 411 include cell phones, PDAs, personal computers, and the like (not shown).
  • the memory modules 412 generally include different modalities, illustratively semiconductor memory, such as random access memory (RAM), and disk drives as well as others.
  • the memory modules 412 store an operating system 413, data structures 414, instructions 415, applications 416, and procedures 417.
  • Storage devices may include mass disk drives, floppy disks, magnetic disks, optical disks, magneto-optical disks, fixed disks, hard disks, CD-ROMs, recordable CDs, DVDs, recordable DVDs (e.g., DVD-R, DVD+R, DVD-RW, DVD+RW, HD-DVD, or Blu-ray Disc), flash and other nonvolatile solid-state storage (e.g., USB flash drive), battery-backed-up volatile memory, tape storage, reader, and other similar media, and combinations of these.
  • mass disk drives floppy disks, magnetic disks, optical disks, magneto-optical disks, fixed disks, hard disks, CD-ROMs, recordable CDs, DVDs, recordable DVDs (e.g., DVD-R, DVD+R, DVD-RW, DVD+RW, HD-DVD, or Blu-ray Disc), flash and other nonvolatile solid-state storage (e.g., USB flash drive), battery-backed-up volatile memory, tape storage
  • the specific software instructions, data structures, and data that implement various embodiments of the present invention are typically incorporated in the server, 401.
  • an embodiment of the present invention is tangibly embodied using a computer readable medium, for example, the memory, and includes of instructions, applications, and procedures which, when executed by the processor, causes the computer system to utilize the present invention, for example, the collection and analysis of data, pixelating structures, determining edge placement errors, moving edge fragments, optimizing edge fragment placements, and the like.
  • the memory may store the software instructions, data structures, and data for any of the operating system, the data collection application, the data aggregation application, the data analysis procedures, and the like in semiconductor memory, in disk memory, or a combination of these.
  • a computer-implemented or computer-executable version of the invention may be embodied using, stored on, or associated with computer-readable medium.
  • a computer-readable medium may include any medium that participates in providing instructions to one or more processors for execution. Such a medium may take many forms including, but not limited to, nonvolatile, volatile, and transmission media.
  • Nonvolatile media includes, for example, flash memory, or optical or magnetic disks.
  • Volatile media includes static or dynamic memory, such as cache memory or RAM.
  • Transmission media includes coaxial cables, copper wire, fiber optic lines, and wires arranged in a bus. Transmission media can also take the form of electromagnetic, radio frequency, acoustic, or light waves, such as those generated during radio wave and infrared data communications.
  • a binary, machine-executable version, of the software of the present invention may be stored or reside in RAM or cache memory, or on a mass storage device.
  • the source code of the software of the present invention may also be stored or reside on mass storage device (e.g., hard disk, magnetic disk, tape, or CD-ROM).
  • code of the invention may be transmitted via wires, radio waves, or through a network such as the Internet.
  • the operating system may be implemented by any conventional operating system comprising Windows® (registered trademark of Microsoft Corporation), Unix® (registered trademark of the Open Group in the United States and other countries), Mac OS ® (registered trademark of Apple Computer, Inc.), Linux® (registered trademark of Linus Torvalds), as well as others not explicitly listed here.
  • Windows® registered trademark of Microsoft Corporation
  • Unix® registered trademark of the Open Group in the United States and other countries
  • Mac OS ® registered trademark of Apple Computer, Inc.
  • Linux® registered trademark of Linus Torvalds
  • the present invention may be implemented as a method, system, or article of manufacture using standard programming or engineering techniques, or both, to produce software, firmware, hardware, or any combination thereof.
  • article of manufacture (or alternatively, "computer program product”) as used in this application is intended to encompass a computer program accessible from any computer readable device, carrier or media.
  • the software in which various embodiments are implemented may be accessible through the transmission medium, for example, from a server over the network.
  • the article of manufacture in which the code is implemented also encompasses transmission media, such as the network transmission line and wireless transmission media.
  • the article of manufacture also includes the medium in which the code is embedded.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Image Processing (AREA)
  • Electron Beam Exposure (AREA)

Abstract

La présente invention concerne des techniques de correction de proximité optique réalisées sur une ou plusieurs unités de traitement graphique et permettant d'améliorer les masques servant à l'impression de conceptions de circuit microélectronique. L'exécution de telles techniques s'effectue sur des plateformes matérielles ou logicielles utilisant des unités de traitement graphique. Ces unités peuvent répartir la charge de calcul avec les unités centrales des systèmes pour une exécution optimale des étapes du procédé de correction de proximité optique.
PCT/US2006/061518 2005-12-02 2006-12-01 Correction de proximite optique sur des plateformes materielles ou logicielles avec des unites de traitement graphique Ceased WO2007120304A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US74168705P 2005-12-02 2005-12-02
US60/741,687 2005-12-02

Publications (2)

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WO2007120304A2 true WO2007120304A2 (fr) 2007-10-25
WO2007120304A3 WO2007120304A3 (fr) 2007-12-21

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TW (1) TWI322953B (fr)
WO (1) WO2007120304A2 (fr)

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TWI448916B (zh) * 2009-07-30 2014-08-11 United Microelectronics Corp 修正佈局圖案的方法
CN119783605A (zh) * 2024-12-31 2025-04-08 西安电子科技大学 一种强磁场脉冲环境数字集成电路电源网络的评估方法

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US8578313B2 (en) * 2008-04-24 2013-11-05 Synopsys, Inc. Pattern-clip-based hotspot database system for layout verification
TWI498698B (zh) * 2014-03-27 2015-09-01 Genesis Technology Inc 使用者介面以及電腦程式產品
US9772849B2 (en) 2014-11-14 2017-09-26 Intel Corporation Four-dimensional morton coordinate conversion processors, methods, systems, and instructions
US9772848B2 (en) 2014-11-14 2017-09-26 Intel Corporation Three-dimensional morton coordinate conversion processors, methods, systems, and instructions
US9772850B2 (en) 2014-11-14 2017-09-26 Intel Corporation Morton coordinate adjustment processors, methods, systems, and instructions

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US5682323A (en) * 1995-03-06 1997-10-28 Lsi Logic Corporation System and method for performing optical proximity correction on macrocell libraries
US5553273A (en) * 1995-04-17 1996-09-03 International Business Machines Corporation Vertex minimization in a smart optical proximity correction system
US5723233A (en) * 1996-02-27 1998-03-03 Lsi Logic Corporation Optical proximity correction method and apparatus
US6467076B1 (en) * 1999-04-30 2002-10-15 Nicolas Bailey Cobb Method and apparatus for submicron IC design
US7069534B2 (en) * 2003-12-17 2006-06-27 Sahouria Emile Y Mask creation with hierarchy management using cover cells
US20060242618A1 (en) * 2005-02-14 2006-10-26 Yao-Ting Wang Lithographic simulations using graphical processing units

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI448916B (zh) * 2009-07-30 2014-08-11 United Microelectronics Corp 修正佈局圖案的方法
CN119783605A (zh) * 2024-12-31 2025-04-08 西安电子科技大学 一种强磁场脉冲环境数字集成电路电源网络的评估方法
CN119783605B (zh) * 2024-12-31 2025-10-17 西安电子科技大学 一种强磁场脉冲环境数字集成电路电源网络的评估方法

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TW200739377A (en) 2007-10-16
TWI322953B (en) 2010-04-01
WO2007120304A3 (fr) 2007-12-21

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