WO2008018478A1 - Structure de jonction de dispositif - Google Patents

Structure de jonction de dispositif Download PDF

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Publication number
WO2008018478A1
WO2008018478A1 PCT/JP2007/065477 JP2007065477W WO2008018478A1 WO 2008018478 A1 WO2008018478 A1 WO 2008018478A1 JP 2007065477 W JP2007065477 W JP 2007065477W WO 2008018478 A1 WO2008018478 A1 WO 2008018478A1
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Prior art keywords
semiconductor layer
nitrogen
layer
forming
based alloy
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Ceased
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PCT/JP2007/065477
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English (en)
Japanese (ja)
Inventor
Hironari Urabe
Yoshinori Matsuura
Takashi Kubota
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Mitsui Kinzoku Co Ltd
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Mitsui Mining and Smelting Co Ltd
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Priority to JP2007541229A priority Critical patent/JPWO2008018478A1/ja
Publication of WO2008018478A1 publication Critical patent/WO2008018478A1/fr
Anticipated expiration legal-status Critical
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/44—Physical vapour deposition [PVD]

Definitions

  • the present invention relates to a bonding structure of elements constituting a display device such as a liquid crystal display, and more particularly to a manufacturing technology of an element using an A1 based alloy as a wiring circuit material.
  • A1 aluminum (which may be simply referred to as A1 hereinafter) -based alloy is widely used as a constituent material for a display device such as a flat-screen television represented by a liquid crystal display.
  • A1 alloy wiring material has a characteristic that the wiring processing can be easily performed to lower the specific resistance value.
  • a thin film transistor (hereinafter referred to as TFT) as a switching element is an ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).
  • the element is constituted of a transparent electrode (hereinafter sometimes referred to as a transparent electrode layer) and a wiring circuit (hereinafter referred to as an A1 series alloy layer) formed of an A1 series alloy.
  • a transparent electrode hereinafter sometimes referred to as a transparent electrode layer
  • a wiring circuit hereinafter referred to as an A1 series alloy layer formed of an A1 series alloy.
  • molybdenum (Mo) or titanium between the A1 based alloy layer and the transparent electrode layer
  • a refractory metal material such as Ti
  • the semiconductor layer and the A1 alloy layer can be prevented from interdiffusion of A1 and Si due to the thermal process in the manufacturing process.
  • a refractory metal material such as molybdenum (Mo) or titanium (Ti), which is the same as the cap layer described above, is interposed between them.
  • FIG. 1 shows a schematic cross-sectional view of an a-Si type TFT related to a liquid crystal display.
  • the A1 alloy wiring material constituting the gate electrode portion G is used on the glass substrate 1.
  • An electrode wiring circuit layer 2 and a cap layer 3 made of Mo, Mo--W or the like are formed on the glass substrate 1.
  • the gate electrode portion G is provided with a gate insulating film 4 of SiNx as its protection. Further, on the gate insulating film 4, the a-Si semiconductor layer 5, the channel protective film layer 6, the n + -Si semiconductor layer 7, the cap layer 3, the electrode wiring circuit layer 2 and the cap layer 3 are sequentially deposited.
  • the drain electrode portion D and the source electrode portion S are provided by appropriately forming a pattern.
  • the drain electrode portion D and the source electrode portion S are covered with an insulating film 4 ′ for surface planarization of the element or SiNx.
  • a contact hole CH is provided in the insulating layer 4 ′, and a transparent electrode layer 7 ′ of ITO or IZO is formed in that portion.
  • the cap layer 3 is interposed between the layer 2 and the layer 2.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2003-273109
  • Patent Document 2 Japanese Patent Application Laid-Open No. 2005-123576
  • Patent Document 1 since the resistance of the nitrided part of the A1 based alloy is high, when the semiconductor layer and the A1 based alloy layer are directly joined, the atomic property tends not to be satisfied. Become. Further, as in Patent Document 2, when the entire wiring layer of the A1 alloy is nitrided, the resistance value of the wiring layer itself becomes too large, and satisfactory device characteristics can not be satisfied.
  • the present invention has been made against the background described above, and in the case where a semiconductor layer such as n + -Si and an A1 alloy layer are directly bonded, mutual diffusion of A1 and Si is prevented. Yes, The present invention provides a junction structure of a device capable of maintaining the same characteristics and securing the low resistance characteristics of the A1 based alloy layer itself. More specifically, even if a thermal history of 250 ° C. or more is applied, the interfacial reaction of the interface directly bonded between the semiconductor layer and the A1 based alloy layer is suppressed, and the ceramic characteristics are maintained. The purpose is to provide a bonding technology for devices that can reduce the resistance to 10 ⁇ 'cm or less.
  • the inventors of the present invention which solves the above-mentioned problems, have studied Si forming a semiconductor layer to realize direct bonding between the semiconductor layer and the A1 based alloy layer. It has been found that good direct bonding can be realized when it is contained.
  • the semiconductor layer directly joined to the A1 based alloy layer contains nitrogen. It is assumed to be contained Si.
  • the nitrogen content of Si which forms the semiconductor layer in the present invention is 1 ⁇ 10 18 atoms / cm to 5 ⁇ 10 atoms / cm (The strength, preferred, 1 ⁇ 10 atoms / cm. More preferred to be ⁇ 1 x 10 2 atoms / cm 3 ! /.
  • the semiconductor layer in the junction structure of the device according to the present invention can be made of Si containing nitrogen with a depth of 100 A or more from the surface side directly joined to the A1 based alloy layer.
  • the semiconductor layer in the present invention is preferably made of amorphous n + ⁇ S and p + ⁇ Si! / ,.
  • n is a semiconductor layer in which electrons are dominant as carrier one
  • p is a semiconductor layer in which holes are dominant as carrier one
  • + is Si. It means that the doping element to be added is highly doped.
  • the semiconductor layer in the present invention preferably contains 5 ⁇ 10 17 atoms / cm 3 to 5 ⁇ 10 2 ⁇ toms / cm 3 of a dopant selected from phosphorus, boron and antimony! /.
  • the Al-based alloy in the present invention preferably contains 0.5 at% to Ni; 10. Oat%. In addition, it is more preferable to contain boron by 0.2 to lat% to 0.8 at%. In the case of forming the junction structure of the element according to the present invention, it is preferable to form the A1 based alloy layer by a sputtering method. The sputtering target at that time is 0.5 at% to Ni 10.0. It is preferable to use an Al-based alloy containing at%.
  • Al-based alloy sputtering target which contains 0. lat% to 0.8 at% of boron in addition to Ni.
  • the present invention relates to a thin film transistor formed from an element provided with the above-described element junction structure.
  • N is used as a film forming atmosphere when forming Si to be a semiconductor layer by a chemical vapor deposition method.
  • a gas containing N is introduced to form a semiconductor layer to form Si.
  • the nitrogen partial pressure ratio When forming a film, it can be formed by setting the nitrogen partial pressure ratio to 0.010% to 20%, or by adjusting the nitrogen partial pressure ratio to 0.010% to 20% during film formation. .
  • the device structure according to the present invention can also be formed by performing heat treatment at 200 ° C. to 500 ° C. in a nitrogen atmosphere after forming Si to be a semiconductor layer.
  • FIG. 1 is a schematic cross-sectional view of a TFT.
  • FIG. 2 Schematic diagram of the ceramic characterization evaluation.
  • FIG. 5 Conceptual graph showing nitrogen analysis results in the semiconductor layer by the secondary ion mass spectrometer
  • FIG. 6 A schematic plan view showing the wiring structure of the TFT element.
  • the element in the present invention includes a semiconductor layer and an A1 based alloy layer directly bonded to the semiconductor layer, and the semiconductor layer directly bonded to the A1 based alloy layer contains nitrogen. It is Si.
  • the nitrogen content is preferably 1 ⁇ 10 atoms / cm to 5 ⁇ 10 ′ atoms / cm and the force S is preferably 1 ⁇ 10 18 atoms / cm 3 to 1 ⁇ 10 2 ° atoms / cm 3. Preferred Yes.
  • the whole of the semiconductor layer is made of Si having the above-mentioned nitrogen content, but a part of the semiconductor layer is made of Si having the above-mentioned nitrogen content
  • the depth of 100 A or more from the surface of the semiconductor layer directly bonded to the Al-based alloy layer is made of Si containing nitrogen. The point is that if the semiconductor layer in the portion to be joined directly to the A1 alloy layer has Si with the above-mentioned nitrogen content, it is possible to prevent the interdiffusion of A1 and Si, and to maintain the ceramic characteristics. .
  • SiH diluted with argon is used in forming a semiconductor layer by chemical vapor deposition, V, or chemical vapor deposition (CVD).
  • V chemical vapor deposition
  • CVD chemical vapor deposition
  • the introduced gas such as, PH, N gas, NH gas, NO gas
  • a method of performing heat treatment in a nitrogen atmosphere after forming a semiconductor layer For example, when nitrogen is contained in a semiconductor layer in a TFT manufacturing process of a liquid crystal display, either the whole semiconductor layer or a part of the surface of the semiconductor layer may be used. In view of the degree of difficulty, it is preferable to adopt a method that can easily cope with the current manufacturing process.
  • the semiconductor layer is adjusted by adjusting the nitrogen partial pressure ratio to 0.010% to 20% during film formation. It is possible to make nitrogen contained in Si.
  • the nitrogen partial pressure ratio is the partial pressure ratio when nitrogen gas is introduced into the atmosphere for forming the Si film, and if it is less than 0.01%, even if other film forming conditions in CVD are varied, This is because the nitrogen content (1 ⁇ 10 18 atoms / cm 3 ) that can ensure heat resistance can not be achieved. On the other hand, if it exceeds 20%, the resistance of the semiconductor layer tends to be high, and the transistor characteristics tend to deteriorate.
  • the nitrogen partial pressure ratio is obtained from the actual flow rate according to the compaction factor.
  • nitrogen can be contained in the entire semiconductor layer, or nitrogen can be contained in part of the semiconductor layer. Instead of this nitrogen gas, use ammonia (NH
  • nitrogen can be contained in Si of the semiconductor layer by performing heat treatment at 200 ° C. to 500 ° C. in a nitrogen atmosphere.
  • the semiconductor layer has a nitrogen content continuously decreasing in the depth direction from the surface of the semiconductor layer.
  • the nitrogen atmosphere in the present invention is a gas containing nitrogen as its main component, for example, N gas, NH gas
  • gas species such as NO gas to indicate a purposefully controlled environment, preferably nitrogen
  • the partial pressure is 90% or more, more preferably 99% or more.
  • Si containing nitrogen is preferably a so-called doped one, that is, n + ⁇ Si or p + ⁇ Si, and its crystal form is monomonorefus.
  • a semi-conductor layer, phosphorus, boron, a dopant selected from antimony, 5 X 10 17 atom s / cm 3 ⁇ 5 X 10 21 atoms / cm 3 is preferably contained. This is because Si that is highly doped with phosphorus, boron, and antimony can ensure the atomic property in direct bonding with the A1 based alloy layer.
  • the transistor characteristics of the device can be sufficiently secured depending on the dopant species and activation heat treatment conditions. .
  • the dopant species further high doping exceeding 5 ⁇ 10 21 atoms / cm 3 is possible, but in the case of an amorphous Si semiconductor device, it is not practical because the activation rate of the dopant does not increase.
  • each dopant species into Si can be carried out by a known method such as a so-called thermal diffusion method or ion implantation method. And the dopant species and its content in Si Can be measured by a secondary ion mass spectrometer (Dynamic SIMS)
  • the A1 based alloy layer is preferably an A1 based alloy containing Ni (nickel). Even if the Al-based alloy layer is pure Al, the present invention is effective if it is an effective Ni-containing A1-based alloy, it is easy to set the resistance of the A1-based alloy layer to 10 ⁇ 'cm or less. This is because it is easy to realize direct bonding with good device characteristics.
  • Specific examples of the Al-based alloy containing Ni include Al-Ni alloy, Al-Ni-B (boron) alloy, Al-Ni-C (carbon) alloy, and Al-Ni-Nd (neodym) alloy. And Al—Ni—La (lanthanum) alloy.
  • Ni content is 0 ⁇ 5 at% ⁇ ; 10 ⁇ O at% force S preferred.
  • Ni content is 0 ⁇ 5 at% ⁇ ; 10 ⁇ O at% force S preferred.
  • Nd and La it is preferable to make Ni content into content of 0.5 at%-2.Oat%.
  • the content of B, C, Nd and La is preferably from 0. lat% to 1.0 at%.
  • the Al-based alloy is more preferably an Al-Ni-B alloy containing B (boron) in an amount of 0. lat% to 0.8 at%.
  • An Al-Ni-B alloy of such a composition enables direct bonding with a transparent electrode layer such as ITO or IZO, and also enables direct bonding with a semiconductor layer such as n + -Si, and thus the transparent electrode. It is possible to form an element excellent in heat resistance, which has a low junction resistance value when directly joined to a layer or a semiconductor layer.
  • this Al-Ni-B alloy it is preferable that the Ni content be 4. Oat% or more and the B content be 0.80at% or less.
  • the Ni content is in the range of 3 ⁇ 60 at% to 6. Oat%, and the B content is in the range of 0 ⁇ 20 at% to 0.80 at%.
  • the A1 alloy of the present invention desirably contains 75 at% or more of A1 itself.
  • the junction structure of the device according to the present invention described above, the interfacial reaction between the direct junction interface between the semiconductor layer and the A1 based alloy layer is suppressed, the ceramic characteristics are maintained, and the resistance of the A1 based alloy layer is maintained. Since the element can have a value of 10 10 ⁇ 'cm or less, it can be said to be suitable for forming a thin film transistor (TFT).
  • TFT thin film transistor
  • the junction structure of the device according to the present invention This is an extremely suitable device structure when forming a so-called bottom gate TFT having a gate electrode located on the substrate side.
  • Example 1 a pure A1 film (specific resistance value: 2.8 ⁇ -cm), an Al- 5. Oat% Ni alloy film (specific resistance value: 4.0 ⁇ -cm), an A1 system alloy layer is used. 5.5. Oat% Ni-0.4at% B film (specific resistance value 4 ⁇ 2 ⁇ ⁇ -cm) is used to directly bond the semiconductor layer with Si, and the characteristics of the element are evaluated. (A1-5. Oat% Ni-0.3at% C film (specific resistance 4 ⁇ 8 ⁇ ′ cm) was also added to the comparative example). As the characteristic evaluation, the ceramic characteristics and Si diffusion heat resistance described below were investigated.
  • each film is a single film (approximately 0 thick) by sputtering (magnetron 'sputtering apparatus, input power 3 ⁇ OW / cm 2 , argon gas flow rate 100 sccm, argon pressure 0 ⁇ 5 Pa) on a glass substrate. (3) 111) and heat-treated in a nitrogen gas atmosphere at 300.degree. C. for 30 minutes, and then measured using a four-terminal resistance measuring apparatus.
  • sputtering magnet 'sputtering apparatus, input power 3 ⁇ OW / cm 2 , argon gas flow rate 100 sccm, argon pressure 0 ⁇ 5 Pa
  • FIG. 2 (A) shows a sample sectional view
  • FIG. 2 (B) shows a sample plan view
  • a 500 A n + -Si semiconductor layer 2 was formed on a glass substrate 1 (Coyung Co., Ltd .: # 1737) by CVD (manufactured by Samco Co., Ltd .: PD-2220L).
  • the deposition conditions for this n + — Si semiconductor layer 2 are: RF 100 W (0.31 W / cm 2 ), SiH gas (hydrogen dilution) flow rate 300 ccm, phosphorus (P) component-containing gas
  • a 300 A-thick n + — Si semiconductor layer 2 was formed at a flow rate of 50 ccm (hydrogen dilution) and a substrate temperature of 300 ° C. Then, A1 system alloy layer 3 was formed with a thickness of 2000 A by sputtering (magnetron 'sputtering apparatus, input power: 3 ⁇ OW / cm 2 , argon gas flow rate: 100 sccm, argon pressure: 0 ⁇ 5 Pa). Then, an evaluation sample was produced by forming the A1 based alloy layer 3 by photolithograpy so as to form a 1000 m ⁇ 300 ⁇ m electrode pad with a pad interval of 50 ⁇ m.
  • the ceramic characteristics were evaluated by performing current-voltage measurement in the range of +5 V and 5 V between both electrode pads formed on this evaluation sample.
  • This method of evaluating the ceramic characteristics is based on the measured current-voltage graph, in which an evaluation sample in which the correlation between the current and the voltage is linear is formed as an evaluation of the ceramic junction! Atomic junctions have a non-linear correlation with voltage It was evaluated! /!
  • Si diffusion heat resistance In an evaluation sample of this property, an n + -Si semiconductor layer (30 OA) is formed on a glass substrate by CVD (the same conditions as in the case of the above-mentioned atomic property), and the semiconductor layer is formed.
  • the A1 based alloy layers (2000 A) were formed by sputtering (magnetron 'sputtering apparatus, input power: 3.0 W / cm 2 , argon gas flow rate: 100 sccm, argon pressure: 0.5 Pa).
  • the N gas is added to the introduced gas of the SiH gas diluted with hydrogen and the phosphorus (P) component-containing gas when forming a film by CVD, and the N pressure is added to the partial pressure ratio.
  • the N gas is added to the introduced gas of the SiH gas diluted with hydrogen and the phosphorus (P) component-containing gas when forming a film by CVD, and the N pressure is added to the partial pressure ratio.
  • a phosphoric acid A1 etching solution (Kanto Chemical Co., Ltd., liquid temperature 32 ° C.
  • a mixed acid etchant / composition (volume ratio) phosphoric acid: succinic acid: acetic acid: water 16: 1: 2: 1) formed in the upper layer by immersion for 10 minutes Only the respective composition films were dissolved to expose the semiconductor layer. The surface of the exposed semiconductor layer was observed under an optical microscope (200 ⁇ ) to examine interdiffusion between Si and A1 and to check whether it was / !.
  • FIGS. 3 and 4 show representative optical micrographs of the exposed semiconductor layer surface.
  • Fig. 3 shows the surface of the semiconductor layer where no interdiffusion is observed (evaluation result:))
  • Fig. 4 shows traces of interdiffusion (black spots in the photograph) (evaluation result: X).
  • FIGS. 3 and 4 are images referred to when determining the presence or absence of interdiffusion, and show the observation results of this example.
  • Tables 1 to 3 show the results of the above characteristic evaluation. Samples No. 1-1 to 13 are cases where nitrogen is contained in the Si semiconductor layer, and samples No. 1-4 to 17 are cases where nitrogen is not contained in the Si semiconductor layer. Also, Table 1 shows the case where the nitrogen content of the Si semiconductor layer is 4 ⁇ 10 19 atoms S / cm 3 , Table 2 shows the case of 1 ⁇ 10 18 atoms / cm 3 , and Table 3 shows 1 ⁇ 10 2 ° atoms / cm. The results for case 3 are shown. The nitrogen content here is an average value.
  • the nitrogen content of the Si semiconductor layer was measured by a secondary ion mass spectrometer (Dynamic SIMS) in the case of 4 ⁇ 10 19 atoms / cm 3 or more.
  • a secondary ion mass spectrometer (Dyna mic SIMS)
  • FIG. 5 shows an example of the result of analyzing nitrogen in the depth direction of a semiconductor layer (source or drain) formed of nitrogen-containing n + -Si with a secondary ion mass spectrometer. ing. As shown in FIG.
  • nitrogen when nitrogen is contained in part of Si of the semiconductor layer, nitrogen is contained in the part corresponding to the thickness of the part containing nitrogen in the part of the Si semiconductor layer containing nitrogen. It is detected. And the nitrogen content (concentration) is specified by the average value of the measurement values corresponding to the upper bottom part of the trapezoidal peak as shown in FIG.
  • the nitrogen content is 1 ⁇ 10 18 atoms S / cm 3 , it is below the detection limit of the secondary ion mass spectrometer, so X-ray photoelectron spectrometer (XPS) is used to detect the Si semiconductor layer. Sputtering is performed in the depth direction by about 50 to OOA, and then the sputtered portion is measured by an X-ray photoelectron spectrometer (XPS), and nitrogen obtained from the result of sample measurement with known nitrogen content The nitrogen content was calculated relative to the integrated intensity of the detected peak.
  • XPS X-ray photoelectron spectrometer
  • This nitrogen content can be measured by either a secondary ion mass spectrometer or an X-ray photoelectron spectrometer, but in the case of a content near the detection limit of the secondary ion mass spectrometer, From the viewpoint of the reliability of the measured values, measurement by an X-ray photoelectron spectrometer may be performed.
  • the on / off ratio which is the switching characteristic of the element, tends not to be able to be obtained by six orders of magnitude.
  • the on / off ratio is 6 digits when the on current is 10_ 4 A and the off current ⁇ ⁇ ⁇ , such a on / off ratio can not be maintained, so the nitrogen content is 1 x 10 2 ° atom It is considered to be practical to set it to S 3 / cm 3 or less.
  • Example 2 with respect to the Si diffusion heat resistance and the switching characteristic (on / off ratio) of the element, the Al semiconductor of various compositions and the Si semiconductor layer in which the nitrogen content is changed. explain the results of the survey in detail.
  • the A1 series alloys evaluated in this Example 2 are nine types of sample Nos. 2 to 1 to 2 shown in Table 4 and Table 5.
  • the switching characteristics of the device were measured by measuring the on / off ratio. Evaluation samples were prepared according to the following procedure.
  • an Al-based alloy film having a thickness of 3000 A was formed on a glass substrate (manufactured by Ko-Yung Co., Ltd .: # 1737) using an Al-based alloy target of each composition.
  • Sputtering conditions are substrate heating temperature 100. C, DC Power 000 W (3. 1 W / cm 2 ), argon gas flow rate 100 sccm, argon pressure 0.5 Pa.
  • the A1 alloy film was etched by photolithography to form a gate wiring width of 50 ⁇ m, and a gate electrode width of 15 m (see FIG. 6).
  • Photolithography conditions are as follows: A1 based alloy film surface resist (TFR- 970: Tokyo Ohka Kogyo Co., Ltd.
  • TMAH developer alkaline developer
  • SiNx to be an insulating layer is formed by RF sputtering to a thickness of 2200 A I made a film.
  • the film forming conditions were a substrate heating temperature of 350 ° C., RF Power 000 W (3.1 W / cm 2 ), an argon gas flow rate of 90 sccm, a nitrogen gas flow rate of 10 sccm, and a pressure of 0.5 Pa.
  • amorphous i-Si and phosphorus-doped ⁇ -Si were optionally deposited by CVD.
  • the film forming conditions for i-Si are: substrate heating temperature 300 ° C., RF power IOOW (0.31 W / cm 2 ), SiH flow rate (10% argon gas dilution) 300 sccm
  • the thickness was 2000 A.
  • the deposition conditions for nitrogen-doped n + — Si (P (phosphorus) -doped film) are the substrate heating temperature of 200. C, RF PowerIOOW (0.31 W / cm 2 ), SiH flow rate (8% argon gas diluted)
  • an Al-based alloy film having the same composition as that of the film first formed on the glass substrate was formed to a thickness of 2000 A.
  • the film forming conditions were the same as the above-described gate wiring.
  • a source wiring, a drain wiring, and an electrode were formed by photolithography.
  • the photolithography conditions are the same as those of the gate wiring.
  • dry etching of the n + -Si layer was performed. Dry etching conditions are RF Power 50 W, SF gas flow rate 30 sccm, pressure lOPa. After that, stripping solution (ST106
  • a 2500 ⁇ thick SiNx insulating film to be a passivation was formed, and only gate, source, and drain electrode portions were exposed by dry etching.
  • the dry etching conditions are: RF Power 100 W, SF gas flow rate 30 sccm, O gas flow rate 5 sccm, pressure lOPa
  • the on / off ratio of the switching characteristic of the element was measured by the three-terminal method for the evaluation sample prepared as described above.
  • the Si diffusion heat resistance was performed in the same manner as the method described in Example 1.
  • Tables 4 and 5 show the results of the Si diffusion heat resistance evaluation (Table 4) and the on / off ratio measurement (Table 5) in the Si semiconductor layer in which the A1 alloy and nitrogen content of each composition were changed. .
  • the nitrogen content of the Si semiconductor layer be in the order of 10 18 atoms / cm 3 to 10 21 atoms / cm 3 .
  • A1-5. Oat% Ni-0.4 at% B alloy (sample No. 2-3), A1-3. Oat% Ni-0.4 at% B alloy (sample No. 2-6), Al- 3.
  • 2 at% Ni—0.2 at% B alloy sample No. 2 ⁇ 7
  • ⁇ 1-2 ⁇ O at% Ni—0.4 at% B alloy sample No. 2-8

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  • Electrodes Of Semiconductors (AREA)

Abstract

La présente invention concerne une structure de jonction d'un dispositif, qui permet d'empêcher la diffusion mutuelle d'Al et de Si quand une couche semi-conductrice comme une couche Si de type n+ et une couche d'alliage d'Al sont directement jointes l'une à l'autre, tout en maintenant les caractéristiques ohmiques et en assurant les caractéristiques de faible résistance de la couche d'alliage d'Al. Elle concerne spécifiquement une structure de jonction d'un dispositif qui comprend une couche semi-conductrice et une couche d'alliage d'Al directement jointe à la couche semi-conductrice. La structure de jonction du dispositif est caractérisée en ce que la couche semi-conductrice jointe directement à la couche d'alliage d'Al est composée de Si contenant de l'azote. La teneur en azote contenue dans le Si est comprise entre 1 x 1018 et 5 x 1021 atomes/cm3.
PCT/JP2007/065477 2006-08-09 2007-08-08 Structure de jonction de dispositif Ceased WO2008018478A1 (fr)

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JP2007541229A JPWO2008018478A1 (ja) 2006-08-09 2007-08-08 素子の接合構造

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JP2006-217228 2006-08-09
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JP2006-282051 2006-10-16
JP2006282051 2006-10-16

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JP2009239263A (ja) * 2008-03-01 2009-10-15 Semiconductor Energy Lab Co Ltd 薄膜トランジスタ及び表示装置
JP2009302524A (ja) * 2008-05-16 2009-12-24 Semiconductor Energy Lab Co Ltd 薄膜トランジスタ
JP2010239120A (ja) * 2009-03-09 2010-10-21 Semiconductor Energy Lab Co Ltd 薄膜トランジスタ

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JP5354781B2 (ja) 2009-03-11 2013-11-27 三菱マテリアル株式会社 バリア層を構成層とする薄膜トランジスターおよび前記バリア層のスパッタ成膜に用いられるＣｕ合金スパッタリングターゲット

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Publication number Priority date Publication date Assignee Title
JP2009239263A (ja) * 2008-03-01 2009-10-15 Semiconductor Energy Lab Co Ltd 薄膜トランジスタ及び表示装置
US8618544B2 (en) 2008-03-01 2013-12-31 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor and display device
JP2009302524A (ja) * 2008-05-16 2009-12-24 Semiconductor Energy Lab Co Ltd 薄膜トランジスタ
JP2010239120A (ja) * 2009-03-09 2010-10-21 Semiconductor Energy Lab Co Ltd 薄膜トランジスタ

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