WO2008136417A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
WO2008136417A1
WO2008136417A1 PCT/JP2008/058088 JP2008058088W WO2008136417A1 WO 2008136417 A1 WO2008136417 A1 WO 2008136417A1 JP 2008058088 W JP2008058088 W JP 2008058088W WO 2008136417 A1 WO2008136417 A1 WO 2008136417A1
Authority
WO
WIPO (PCT)
Prior art keywords
information processing
processing system
memory
chips
volatile memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/058088
Other languages
English (en)
French (fr)
Inventor
Seiji Miura
Yoshinori Haraguchi
Kazuhiko Abe
Shoji Kaneko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
Elpida Memory Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elpida Memory Inc filed Critical Elpida Memory Inc
Priority to US12/597,097 priority Critical patent/US8886893B2/en
Priority to EP08752131A priority patent/EP2149842A4/en
Priority to CN2008800134899A priority patent/CN101669097B/zh
Priority to KR1020097023975A priority patent/KR101101729B1/ko
Publication of WO2008136417A1 publication Critical patent/WO2008136417A1/ja
Anticipated expiration legal-status Critical
Priority to US14/507,068 priority patent/US20150092490A1/en
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

　本発明は、高速且つ低コストで、メモリ容量の拡張性を確保できる使い勝手の良い情報処理システムを提供することを目的とする。情報処理装置、揮発性メモリおよび不揮発性メモリを含む情報処理システムを構成する。情報処理装置、揮発性メモリおよび不揮発性メモリは直列接続させ、接続信号数を少なくすることにより、メモリ容量の拡張性を保ちつつ、高速化を図る。不揮発性メモリのデータを揮発性メモリへ転送させる際は、エラー訂正を行い、信頼性の向上を図る。これら複数のチップからなる情報処理システムを、各チップが相互に積層して配置され、ボールグリッドアレイ(BGA)やチップ間のボンディングによって配線された情報処理システム・モジュールとして構成する。
PCT/JP2008/058088 2007-04-26 2008-04-25 半導体装置 Ceased WO2008136417A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US12/597,097 US8886893B2 (en) 2007-04-26 2008-04-25 Semiconductor device
EP08752131A EP2149842A4 (en) 2007-04-26 2008-04-25 SEMICONDUCTOR DEVICE
CN2008800134899A CN101669097B (zh) 2007-04-26 2008-04-25 半导体装置
KR1020097023975A KR101101729B1 (ko) 2007-04-26 2008-04-25 반도체 장치
US14/507,068 US20150092490A1 (en) 2007-04-26 2014-10-06 Semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007116516A JP5669338B2 (ja) 2007-04-26 2007-04-26 半導体装置
JP2007-116516 2007-04-26

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US12/597,097 A-371-Of-International US8886893B2 (en) 2007-04-26 2008-04-25 Semiconductor device
US14/507,068 Continuation US20150092490A1 (en) 2007-04-26 2014-10-06 Semiconductor device

Publications (1)

Publication Number Publication Date
WO2008136417A1 true WO2008136417A1 (ja) 2008-11-13

Family

ID=39943524

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/058088 Ceased WO2008136417A1 (ja) 2007-04-26 2008-04-25 半導体装置

Country Status (7)

Country Link
US (2) US8886893B2 (ja)
EP (1) EP2149842A4 (ja)
JP (1) JP5669338B2 (ja)
KR (1) KR101101729B1 (ja)
CN (1) CN101669097B (ja)
TW (1) TW200907678A (ja)
WO (1) WO2008136417A1 (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100262979A1 (en) * 2009-04-08 2010-10-14 Google Inc. Circular command queues for communication between a host and a data storage device
US8588017B2 (en) 2010-10-20 2013-11-19 Samsung Electronics Co., Ltd. Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same
US9244842B2 (en) 2009-04-08 2016-01-26 Google Inc. Data storage device with copy command
JP2022548889A (ja) * 2019-09-17 2022-11-22 マイクロン テクノロジー，インク． 多層メモリの柔軟なプロビジョニング

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5214736B2 (ja) * 2008-09-12 2013-06-19 株式会社日立製作所 半導体装置および情報処理システム
US8689017B2 (en) * 2009-03-12 2014-04-01 Cisco Technology, Inc. Server power manager and method for dynamically managing server power consumption
US8904140B2 (en) 2009-05-22 2014-12-02 Hitachi, Ltd. Semiconductor device
US8626997B2 (en) * 2009-07-16 2014-01-07 Micron Technology, Inc. Phase change memory in a dual inline memory module
TWI455146B (zh) * 2010-06-11 2014-10-01 Apacer Technology Inc 可擴充記憶體單元之儲存裝置
JP5614213B2 (ja) * 2010-10-01 2014-10-29 日本電気株式会社 記憶領域提供装置、記憶領域提供方法、及び、記憶領域提供プログラム
US9490003B2 (en) * 2011-03-31 2016-11-08 Intel Corporation Induced thermal gradients
US9658678B2 (en) 2011-03-31 2017-05-23 Intel Corporation Induced thermal gradients
DE112011105760T5 (de) * 2011-10-25 2014-11-13 Hewlett-Packard Development Company, L.P. Lichtquellensteuerung für Laufwerksträger
WO2013095674A1 (en) 2011-12-23 2013-06-27 Intel Corporation Memory operations using system thermal sensor data
US8929146B1 (en) * 2013-07-26 2015-01-06 Avalanche Technology, Inc. Controller management of memory array of storage device using magnetic random access memory (MRAM)
US9940050B2 (en) * 2015-10-05 2018-04-10 Mediatek Inc. Apparatus and method to speed up memory frequency switch flow
US10585791B2 (en) * 2018-03-20 2020-03-10 Intel Corporation Ordering of memory device mapping to reduce contention
US11029883B2 (en) * 2018-12-28 2021-06-08 Micron Technology, Inc. Reduce system active power based on memory usage patterns
CN115699187A (zh) * 2020-06-28 2023-02-03 华为技术有限公司 堆叠存储器及存储系统
US11494317B1 (en) 2020-12-29 2022-11-08 Waymo Llc Memory validation

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0566306A2 (en) 1992-04-16 1993-10-20 Hitachi, Ltd. Semiconductor memory device
JPH07146820A (ja) 1993-04-08 1995-06-06 Hitachi Ltd フラッシュメモリの制御方法及び、それを用いた情報処理装置
JP2001005723A (ja) 1999-06-21 2001-01-12 Mitsubishi Electric Corp 半導体記憶装置およびそれを用いたメモリシステム
JP2002007308A (ja) 2000-06-20 2002-01-11 Nec Corp メモリバスシステムおよび信号線の接続方法
JP2002530742A (ja) * 1998-11-16 2002-09-17 インフィネオン・テクノロジーズ・アーゲー 外部デバイスへのアクセスを優先順序付けるための方法および装置
JP2002366429A (ja) 2001-06-11 2002-12-20 Hitachi Ltd 半導体記憶装置
JP2004192616A (ja) 2002-12-12 2004-07-08 Samsung Electronics Co Ltd メモリシステム及びメモリデバイス並びにメモリモジュール
JP2006163711A (ja) * 2004-12-06 2006-06-22 Renesas Technology Corp 情報処理システム
JP2007310430A (ja) * 2006-05-16 2007-11-29 Hitachi Ltd メモリモジュール

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7000A (en) * 1850-01-08 Smut-machine
JP3850067B2 (ja) * 1996-04-24 2006-11-29 株式会社ルネサステクノロジ メモリシステムおよびそれに用いられる半導体記憶装置
KR100297721B1 (ko) 1998-10-29 2001-08-07 윤종용 반도체 장치간 신호 송수신을 위한 송신회로 및 수신회로
US6446143B1 (en) * 1998-11-25 2002-09-03 Compaq Information Technologies Group, L.P. Methods and apparatus for minimizing the impact of excessive instruction retrieval
TWI244617B (en) 2000-09-16 2005-12-01 Ibm A client/server-based data processing system for performing transactions between clients and a server and a method of performing the transactions
KR100395770B1 (ko) * 2001-05-23 2003-08-21 삼성전자주식회사 시스템의 부트-업 메모리로서 사용 가능한 불휘발성플래시 메모리 장치 및 그의 동작 방법
JP3696812B2 (ja) 2001-07-19 2005-09-21 富士通株式会社 入出力インタフェースおよび半導体集積回路
US7139849B2 (en) * 2002-08-07 2006-11-21 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit device
US6820181B2 (en) * 2002-08-29 2004-11-16 Micron Technology, Inc. Method and system for controlling memory accesses to memory modules having a memory hub architecture
DE112004000821B4 (de) * 2003-05-13 2016-12-01 Advanced Micro Devices, Inc. System mit einem Hauptrechner, der mit mehreren Speichermodulen über eine serielle Speicherverbindung verbunden ist
US6944064B2 (en) * 2003-12-22 2005-09-13 Silicon Storage Technology, Inc. Memory unit having programmable device ID
US7412574B2 (en) * 2004-02-05 2008-08-12 Micron Technology, Inc. System and method for arbitration of memory responses in a hub-based memory system
US7257683B2 (en) * 2004-03-24 2007-08-14 Micron Technology, Inc. Memory arbitration system and method having an arbitration packet protocol
JP2006065697A (ja) * 2004-08-27 2006-03-09 Hitachi Ltd 記憶デバイス制御装置
WO2006074176A2 (en) * 2005-01-05 2006-07-13 The Regents Of The University Of California Memory architectures including non-volatile memory devices
JP2006293969A (ja) * 2005-03-17 2006-10-26 Fujitsu Ltd データ転送装置
US7184360B2 (en) * 2005-06-15 2007-02-27 Infineon Technologies, Ag High-speed interface circuit for semiconductor memory chips and memory system including semiconductor memory chips
US20070016698A1 (en) * 2005-06-22 2007-01-18 Vogt Pete D Memory channel response scheduling
US7865684B2 (en) * 2005-06-27 2011-01-04 Ab Initio Technology Llc Managing message queues
US20070005922A1 (en) * 2005-06-30 2007-01-04 Swaminathan Muthukumar P Fully buffered DIMM variable read latency
US20070045606A1 (en) * 2005-08-30 2007-03-01 Michele Magistretti Shaping a phase change layer in a phase change memory cell
US7546410B2 (en) * 2006-07-26 2009-06-09 International Business Machines Corporation Self timed memory chip having an apportionable data bus

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0566306A2 (en) 1992-04-16 1993-10-20 Hitachi, Ltd. Semiconductor memory device
JPH05299616A (ja) 1992-04-16 1993-11-12 Hitachi Ltd 半導体記憶装置
JPH07146820A (ja) 1993-04-08 1995-06-06 Hitachi Ltd フラッシュメモリの制御方法及び、それを用いた情報処理装置
JP2002530742A (ja) * 1998-11-16 2002-09-17 インフィネオン・テクノロジーズ・アーゲー 外部デバイスへのアクセスを優先順序付けるための方法および装置
JP2001005723A (ja) 1999-06-21 2001-01-12 Mitsubishi Electric Corp 半導体記憶装置およびそれを用いたメモリシステム
JP2002007308A (ja) 2000-06-20 2002-01-11 Nec Corp メモリバスシステムおよび信号線の接続方法
JP2002366429A (ja) 2001-06-11 2002-12-20 Hitachi Ltd 半導体記憶装置
JP2004192616A (ja) 2002-12-12 2004-07-08 Samsung Electronics Co Ltd メモリシステム及びメモリデバイス並びにメモリモジュール
JP2006163711A (ja) * 2004-12-06 2006-06-22 Renesas Technology Corp 情報処理システム
JP2007310430A (ja) * 2006-05-16 2007-11-29 Hitachi Ltd メモリモジュール

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
"Model KBEOOF005A-D411", June 2005, SAMSUNG ELECTRONICS CO., LTD., article "MCP data sheet"
"Model LRS1380", 10 December 2001, SHARP CORPORATION, article "Data Sheet of Combination Memory (Stacked CSP), Flash Memory + RAM"
See also references of EP2149842A4 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100262979A1 (en) * 2009-04-08 2010-10-14 Google Inc. Circular command queues for communication between a host and a data storage device
US9244842B2 (en) 2009-04-08 2016-01-26 Google Inc. Data storage device with copy command
US8588017B2 (en) 2010-10-20 2013-11-19 Samsung Electronics Co., Ltd. Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same
JP2022548889A (ja) * 2019-09-17 2022-11-22 マイクロン テクノロジー，インク． 多層メモリの柔軟なプロビジョニング

Also Published As

Publication number Publication date
JP5669338B2 (ja) 2015-02-12
KR101101729B1 (ko) 2012-01-05
CN101669097A (zh) 2010-03-10
CN101669097B (zh) 2013-05-22
US20100131724A1 (en) 2010-05-27
JP2008276351A (ja) 2008-11-13
US8886893B2 (en) 2014-11-11
EP2149842A1 (en) 2010-02-03
EP2149842A4 (en) 2011-04-06
KR20090127956A (ko) 2009-12-14
US20150092490A1 (en) 2015-04-02
TW200907678A (en) 2009-02-16

Similar Documents

Publication Publication Date Title
WO2008136417A1 (ja) 半導体装置
TW200710655A (en) Memory module, memory system, and information device
US10936418B2 (en) Reduced uncorrectable memory errors
KR102296738B1 (ko) 반도체 메모리 장치, 이를 포함하는 메모리 시스템 및 반도체 메모리 장치의 에러 정정 방법
US9098430B2 (en) Composite semiconductor memory device with error correction
TWI578467B (zh) 具有記憶體封裝下之控制器之記憶體裝置及相關之系統及方法
KR102113359B1 (ko) 이중 모드 핀아웃을 가진 플래시 메모리 제어기
KR101683814B1 (ko) 관통 전극을 구비하는 반도체 장치
WO2008076790A3 (en) Multi-die memory device
WO2008131058A3 (en) Hybrid volatile and non-volatile memory device
WO2007134319A3 (en) Multi-chip package for a flash memory
KR102450553B1 (ko) 저장 장치 및 그것을 내장한 메인 보드 및 그것의 자가 진단 방법
CN112400163B (zh) 存储器系统及控制方法
US20130070507A1 (en) Semiconductor memory device
US9105317B2 (en) Memory system capable of calibrating output voltage level of semiconductor memory device and method of calibrating output voltage level of semiconductor memory device
WO2009011780A3 (en) Photovoltaic modules with integrated devices
US20140078846A1 (en) Semiconductor memory device capable of performing refresh operation without auto refresh command
US20140252656A1 (en) Semiconductor package
WO2009000639A3 (en) System and method for error correction and detection in a memory system
US8884446B2 (en) Semiconductor packages
JP2018032141A (ja) 半導体装置
US20130088838A1 (en) Die package, method of manufacturing the same, and systems including the same
CN108062964B (zh) 存储器件及包括该存储器件的半导体封装体
US20160203103A1 (en) Integrated framework of memory storage module and sensor module
TWI597728B (zh) 指派半導體晶粒以致能高堆疊能力之技術

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200880013489.9

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08752131

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2008752131

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 20097023975

Country of ref document: KR

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 12597097

Country of ref document: US