WO2008146487A1 - 回路基板およびその製造方法 - Google Patents

回路基板およびその製造方法 Download PDF

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Publication number
WO2008146487A1
WO2008146487A1 PCT/JP2008/001324 JP2008001324W WO2008146487A1 WO 2008146487 A1 WO2008146487 A1 WO 2008146487A1 JP 2008001324 W JP2008001324 W JP 2008001324W WO 2008146487 A1 WO2008146487 A1 WO 2008146487A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
circuit board
manufacturing
connecting sheet
same
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/001324
Other languages
English (en)
French (fr)
Inventor
Takayuki Kita
Masaaki Katsumata
Tadashi Nakamura
Kota Fukasawa
Kazuhiro Furugoori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp filed Critical Panasonic Corp
Priority to CN2008800003360A priority Critical patent/CN101543149B/zh
Priority to US12/305,046 priority patent/US8446736B2/en
Priority to JP2008539173A priority patent/JP4935823B2/ja
Priority to EP08763924A priority patent/EP2164311B1/en
Publication of WO2008146487A1 publication Critical patent/WO2008146487A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H05K1/183—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components mounted in and supported by recessed areas of the PCBs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/061—Lamination of previously made multilayered subassemblies
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/063—Lamination of preperforated insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
    • Y10T156/1062—Prior to assembly
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24273—Structurally defined web or sheet [e.g., overall dimension, etc.] including aperture
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24893—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including particulate material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

開口部を有し表層に回路が形成された上側基板と、開口部を有し貫通孔に導電性ペーストが充填された導通孔を有する基板間接続シートと表層に回路が形成された下側基板を積層し加熱加圧する。特に、基板間接続シートは、上側基板および下側基板とは異なる材料である。キャビティ構造および高い層間接続信頼性を備えた全層ＩＶＨ構造を有する多層の回路基板を製造することができる。
PCT/JP2008/001324 2007-05-29 2008-05-28 回路基板およびその製造方法 Ceased WO2008146487A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN2008800003360A CN101543149B (zh) 2007-05-29 2008-05-28 电路基板及其制造方法
US12/305,046 US8446736B2 (en) 2007-05-29 2008-05-28 Circuit board and manufacturing method thereof
JP2008539173A JP4935823B2 (ja) 2007-05-29 2008-05-28 回路基板およびその製造方法
EP08763924A EP2164311B1 (en) 2007-05-29 2008-05-28 Circuit board and method for manufacturing the same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007-141536 2007-05-29
JP2007-141535 2007-05-29
JP2007141535 2007-05-29
JP2007141536 2007-05-29

Publications (1)

Publication Number Publication Date
WO2008146487A1 true WO2008146487A1 (ja) 2008-12-04

Family

ID=40074761

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/001324 Ceased WO2008146487A1 (ja) 2007-05-29 2008-05-28 回路基板およびその製造方法

Country Status (7)

Country Link
US (1) US8446736B2 (ja)
EP (1) EP2164311B1 (ja)
JP (2) JP4935823B2 (ja)
KR (1) KR101024166B1 (ja)
CN (1) CN101543149B (ja)
TW (1) TW200906263A (ja)
WO (1) WO2008146487A1 (ja)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010113448A1 (ja) * 2009-04-02 2010-10-07 パナソニック株式会社 回路基板の製造方法および回路基板
JP2011035045A (ja) * 2009-07-30 2011-02-17 Hitachi Chem Co Ltd 接着シートの製造方法および半導体素子搭載用多層配線板の製造方法
CN101990371A (zh) * 2010-08-03 2011-03-23 广东达进电子科技有限公司 一种陶瓷基互联挠性电路板的制造方法
CN101990373A (zh) * 2010-08-03 2011-03-23 广东达进电子科技有限公司 一种陶瓷基互联刚挠结合多层电路板的制造方法
JP2011082429A (ja) * 2009-10-09 2011-04-21 Hitachi Chem Co Ltd キャビティ部を有する多層配線板とその製造方法
JP2011165842A (ja) * 2010-02-09 2011-08-25 Panasonic Corp 多層プリント配線板の製造方法
CN113299561A (zh) * 2021-05-21 2021-08-24 浙江集迈科微电子有限公司 一种腔底防溢胶结构的制备方法
CN113950205A (zh) * 2020-07-16 2022-01-18 深南电路股份有限公司 一种电路板的加工方法、覆铜板的加工方法以及电路板

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US8217514B2 (en) * 2008-04-07 2012-07-10 Stats Chippac Ltd. Integrated circuit packaging system with warpage control system and method of manufacture thereof
TWI389279B (zh) * 2009-01-23 2013-03-11 欣興電子股份有限公司 電路板結構及其製法
JP2011119616A (ja) * 2009-12-07 2011-06-16 Fujitsu Ltd プリント配線基板の製造方法、プリント配線基板、および電子装置
US20110147069A1 (en) * 2009-12-18 2011-06-23 International Business Machines Corporation Multi-tiered Circuit Board and Method of Manufacture
US20120314390A1 (en) * 2010-03-03 2012-12-13 Mutual-Tek Industries Co., Ltd. Multilayer circuit board
US20110216514A1 (en) * 2010-03-03 2011-09-08 Mutual-Tek Industries Co., Ltd. Combined multilayer circuit board having embedded components and manufacturing method of the same
CN101990370B (zh) * 2010-08-03 2012-10-31 广东达进电子科技有限公司 一种陶瓷基刚挠结合多层电路板的制造方法
CN101990372B (zh) * 2010-08-03 2012-07-04 广东达进电子科技有限公司 一种陶瓷基互联刚性电路板的制造方法
CN101990374B (zh) * 2010-08-03 2013-02-13 广东达进电子科技有限公司 一种陶瓷基刚性电路板的制造方法
CN101976716A (zh) * 2010-10-21 2011-02-16 光颉科技股份有限公司 基板通孔的导电方法
CN102548253B (zh) * 2010-12-28 2013-11-06 富葵精密组件(深圳)有限公司 多层电路板的制作方法
US20130000968A1 (en) * 2011-06-30 2013-01-03 Broadcom Corporation 1-Layer Interposer Substrate With Through-Substrate Posts
US20140227498A1 (en) * 2011-09-20 2014-08-14 3M Innovative Properties Company Method, system for manufacturing a circuit board, and the circuit board thereof
JP5949220B2 (ja) * 2012-06-29 2016-07-06 株式会社村田製作所 伝送線路
JP5749235B2 (ja) * 2012-09-25 2015-07-15 パナソニック株式会社 回路部品内蔵基板の製造方法
JP6016017B2 (ja) * 2012-09-27 2016-10-26 日立化成株式会社 接着シート付きプリント配線板の製造方法及びそれを用いた貼り合せプリント配線板の製造方法
KR101258120B1 (ko) * 2012-10-09 2013-04-25 주식회사 이티엘 필름형 인쇄회로 부착방식의 led 조명 모듈.
KR101241271B1 (ko) * 2012-10-09 2013-03-15 주식회사 이티엘 필름형 인쇄회로 부착방식의 led 모듈 제조 방법
CN103227164A (zh) * 2013-03-21 2013-07-31 日月光半导体制造股份有限公司 半导体封装构造及其制造方法
CN103338600A (zh) * 2013-05-10 2013-10-02 华为技术有限公司 Pcb结构及其制造方法，以及埋入器件pcb的制造方法
US9305853B2 (en) 2013-08-30 2016-04-05 Apple Inc. Ultra fine pitch PoP coreless package
JP2015106610A (ja) * 2013-11-29 2015-06-08 イビデン株式会社 電子部品内蔵基板、電子部品内蔵基板の製造方法
CN105378912B (zh) * 2014-06-09 2018-12-28 三菱电机株式会社 半导体封装件的制造方法以及半导体封装件
WO2016116177A1 (en) * 2015-01-23 2016-07-28 Abb Technology Ag Method of generating a power semiconductor module
JP2017050315A (ja) * 2015-08-31 2017-03-09 イビデン株式会社 プリント配線板及びプリント配線板の製造方法
JP2017050313A (ja) * 2015-08-31 2017-03-09 イビデン株式会社 プリント配線板及びプリント配線板の製造方法
EP3430646B1 (en) * 2016-03-16 2021-11-10 INTEL Corporation Stairstep interposers with integrated shielding for electronics packages
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MY172923A (en) * 2016-03-31 2019-12-13 Twisden Ltd Integrated circuit package having pin up interconnect
TWI595812B (zh) * 2016-11-30 2017-08-11 欣興電子股份有限公司 線路板結構及其製作方法
CN108235558B (zh) * 2016-12-14 2020-12-01 欣兴电子股份有限公司 线路板结构及其制作方法
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