WO2009100472A1 - Système de bus redondant - Google Patents

Système de bus redondant Download PDF

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Publication number
WO2009100472A1
WO2009100472A1 PCT/AT2009/000049 AT2009000049W WO2009100472A1 WO 2009100472 A1 WO2009100472 A1 WO 2009100472A1 AT 2009000049 W AT2009000049 W AT 2009000049W WO 2009100472 A1 WO2009100472 A1 WO 2009100472A1
Authority
WO
WIPO (PCT)
Prior art keywords
bus
microprocessor
bkl
bus node
microprocessors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/AT2009/000049
Other languages
German (de)
English (en)
Inventor
Stefan Poledna
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tttech Computertechnik AG
Ipgate AG
Original Assignee
Tttech Computertechnik AG
Ipgate AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tttech Computertechnik AG, Ipgate AG filed Critical Tttech Computertechnik AG
Publication of WO2009100472A1 publication Critical patent/WO2009100472A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • G06F11/2007—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication media
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/182—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits based on mutual exchange of the output between redundant processing components
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/181—Eliminating the failing redundant component

Definitions

  • the invention relates to a bus system for motor vehicles, comprising at least two bus nodes arranged in spaced-apart regions of the motor vehicle, the bus nodes being connected to each other for communication, each of the bus nodes having two redundant microprocessors, via which microprocessors signals can be read in and output connected bus nodes are connected to each other via two redundant high-speed lines, and wherein a microprocessor of a bus node is connected to a microprocessor of a bus node connected to him via such a high-speed line.
  • Redundant bus systems based on CAN ("Controller Area Network"), LIN ("Local Interconnect Network”), MOST ("Media Oriented Systems Transport", optical fiber) and more recently also FlexRay and Ethernet are known, however
  • CAN Controller Area Network
  • LIN Local Interconnect Network
  • MOST Media Oriented Systems Transport
  • FlexRay and Ethernet are known, however
  • signals from sensors or signals in infotainment used separate lines, so that despite bundling of information and transmissions, the scope of the lines in a motor vehicle in the interior even in such systems with approximately 300 - 500 lines is still considerable.
  • bus nodes have a plurality of microprocessors, which are connected by means of high-speed lines
  • bus nodes have a plurality of microprocessors, which are connected by means of high-speed lines
  • EP 0851 614 A1 and JP 5-3483 With such systems, a significant reduction in the number of lines used for signal transmission in a motor vehicle can be achieved because the wiring between two areas in a motor vehicle, especially from front to back, significantly simplifies and the number of lines are significantly reduced, thereby also a Weight savings go hand in hand.
  • motor vehicles in addition to the passenger cars (PKW) also cars with trailers, but also commercial vehicles (commercial vehicles) and commercial vehicles consisting of towing vehicle and trailer to understand and aircraft under the term motor vehicle subsumed.
  • a cable-tailed sensor is connected in the rear of the vehicle with one to two intermediate plugs to a controller (front bus node) in the front of the vehicle. According to the aforementioned system, these are plugged directly to the rear module (rear bus node).
  • At least one of the bus node further comprises at least a third microprocessor, wherein the third microprocessor is connected to the other two microprocessors of its bus node and the third microprocessor is adapted to the other two microprocessors in terms to monitor their functioning.
  • the third microprocessor By monitoring the microprocessors by a supervisor, namely the third microcontroller in the at least one excellent bus node, the full functionality of this bus node can be guaranteed even if one microprocessor fails, and emergency operation is still possible.
  • the third microprocessor at least for the emergency function (s) assume the arithmetic tasks of one of the other two microprocessors.
  • the functionality of the entire system can continue to be ensured in the event of a failure of a microprocessor in a bus node when the third microprocessor or the three microprocessor-containing bus node is adapted to monitor the microprocessors of the one or more bus nodes connected to it with regard to their functionality ,
  • the third microprocessor or the three microprocessor-containing bus nodes is set up to switch off a monitored microprocessor in the event of an error function.
  • a malfunction of the bus node can be prevented, at the same time at least one emergency operation is still possible by the redundant design of the system, in which the relevant functions of the bus node are still available.
  • the third microprocessor or the three microprocessor-containing bus nodes prefferably be set up to emit a warning signal in the event of an error function of a monitored microprocessor. In this way, the operator of the motor vehicle can be warned and caused to make a repair to the vehicle.
  • the warning signal is transmitted via at least one, preferably via both high-speed lines to another bus node, which is set up to issue a warning, for example in optical or acoustic form, or to cause the delivery of such.
  • all signals relating to the safety and / or operation of the vehicle are transmitted redundantly via high-speed lines connecting in each case both bus nodes. In this way, a particularly reliable transmission of the relevant signals between the bus nodes can be ensured.
  • the two microcontrollers of a vehicle dynamics control unit in a motor vehicle which e.g. ABS and ESP (Electronic Stability Program) controls are used as microcontrollers for one of the bus nodes, which makes the invention cheaper and easier to implement, since already existing equipment in the vehicle can be used.
  • ABS and ESP Electronic Stability Program
  • bus nodes are arranged in series with one another. Furthermore, it may be favorable if one or more bus nodes, which each comprise at least one microcontroller, are connected in parallel to a bus node with three microcontrollers, bus nodes connected in parallel being connected to the third microcontroller of the bus node provided with three microcontrollers.
  • FIG. 1 shows a bus system according to the invention in a schematic block diagram representation with two bus nodes
  • FIG. 3 is a rough schematic representation of a bus system with additionally three parallel to the excellent bus node connected further bus node,
  • Fig. 4 in detail the interaction of the three microprocessors in the excellent bus node
  • Fig. 5 shows the bus system of Figure 1 in a more detailed representation.
  • FIG. 1 shows a bus system SYS according to the invention for a motor vehicle.
  • Bus system SYS comprises two bus nodes BK1, BK2 arranged in spaced-apart regions BE1, BE2 of the motor vehicle, bus nodes BK1, BK2 being connected to one another for communication.
  • Each of the bus nodes BK1, BK2 has two redundant microprocessors MCI1, MC12; MC21, MC22 on which microprocessors MCI1, MC12; MC21, MC22 signals can be read in and / or output.
  • Sensors, actuators, controllers, such as slaves, etc. are via single bus systems, e.g. via a respective LIN bus connected to a bus node, as shown in Figure 5 again in detail.
  • the bus nodes BK1, BK2 are connected to one another via two redundant high-speed lines FR1, FR1, one microprocessor MC1, MC12 of the first bus node BK1 being connected to a microprocessor MC21, MC22 of the second bus node BK2 via such a high-speed line FR1, FR1 '.
  • the line set between two areas BEI, BE2 in a kraft thus, especially from the front (area BEI) to the rear (area BE2) significantly simplifies and the number of lines are significantly reduced, which also goes along with a weight saving ,
  • One of the two bus nodes BK1 also referred to below as “excellent" bus node, comprises, in addition to the two microprocessors MC11, MC12, a third microprocessor MC13, this third microprocessor MC13 being connected to the two other microprocessors MC1, MC12 of its bus node BK1 and the third Microprocessor MC13 is configured to monitor the other two microprocessors MCIl, MC12 with regard to their functionality.
  • the observer MC13 itself can be monitored for its functionality by means of the two other microcontrollers of this bus node BKl.
  • the third microprocessor MC13 of the excellent bus node BKl is furthermore set up to monitor the functionality of the microprocessors MC21, MC22 of the bus node BK2 connected to it.
  • the functionality of the entire system in the event of a failure of a microprocessor in a bus node BKL, BK2 continue to be guaranteed.
  • FIG. 2 shows an extended system SYS consisting of four bus nodes BKL, BK2, BK3, BK4, which are arranged in series with each other.
  • the distinguished bus node BK1 again comprises three microprocessors MCI1, MC12, MC13, while the other bus nodes BK2 - BK4 each have two microprocessors MCZL 7 MC22; MCBl 7 MC32; Include MC41, MC42.
  • the bus nodes are each redundant by means of two high-speed transmission lines FR1, FR1 '; FR2, FR2 '; FR3, FR3 'interconnected.
  • FIG. 3 shows a further conceivable arrangement of a bus system according to the invention.
  • an excellent bus node BK1 with three microprocessors MCI1, MC12, MC13 is connected to a series-arranged bus node BK2 with two microprocessors MC21, MC22.
  • three further bus nodes BK5, BK6, BK7 are connected to the excellent bus node BK1.
  • bus node BK5 One of the three parallel bus nodes, bus node BK5, comprises two microprocessors MC51, M52, each of the two microprocessors MC51, MC52 being connected via a high-speed line FR4, FR4 'to the third microprocessor MC13 of the designated bus node BK1.
  • the two other bus nodes BK6, BK7 each have a microprocessor MC6, MC7, wherein the one microprocessor MC6 is redundantly connected via the two bus lines FR5, FR5 'to the bus node BKl, while the microprocessor MC7 of the other bus node BK7 only via a line FR6 is connected to the bus node BKL.
  • the bus node BK5 is typical of a safety-related system in which 2 processors are used, which switch off in the event of non-identity of the output signals X or by parallel comparison X '.
  • the bus node BK6 may be e.g. serve to relieve the bus systems FR1, FR1 'if signals (for example antenna signals or signals originating from a camera or corresponding functions) are divided from the rear vehicle area onto the bus systems FR1, FR1' and then processed in the bus node BK6.
  • Such a bus node is particularly suitable for infotainment.
  • the bus node BK7 is a bus node which contains no safety-relevant functions.
  • FIG. 4 shows the construction of an excellent bus node BK1 with the three microprocessors MCI1, MC12, MC13 and their mode of operation in detail. It should also be mentioned in advance that it is particularly advantageous if the third microprocessor MC13 or the three microprocessor-containing bus node BK1 is set up to switch off a monitored microprocessor MCI1, MC12 in its bus node BK1 in the event of an error function. As a result, a malfunction of the bus node BKL be prevented, at the same time at least one emergency operation is still possible by the redundant design of the system, in which the relevant functions of the bus node BKL are still available.
  • microprocessor MC13 it is particularly advantageous, if the microprocessor MC13 is also further equipped, the microprocessors of the other bus nodes BK2; BKl - BK4; BKl, BK2, BK5 - BK7 monitor and shut down if necessary.
  • the third microprocessor MC13 or the three microprocessor-containing bus node BK1 is set up to emit a warning signal in the event of an error function of a monitored microprocessor. In this way, the operator of the motor vehicle can be warned and caused to make a repair to the vehicle.
  • This signal is fed to both bus systems FR1, FR1 'and e.g. from an instrument cluster, which will be discussed later, evaluated and displayed.
  • the main output signals are monitored for parity P during operation, e.g. various arithmetic operations, interrupts, etc. are compared.
  • a reset starts and compares a comprehensive test cycle on each microprocessor.
  • the third microprocessor MC13 receives the input signals El, E2 of the two other microprocessors MCI1, MC12 (incoming via the buses FR1, FR1) and their output signals A1, A2. If these do not match in the direct comparison, then in the. Microcontroller MC13 compared, which of the output signals Al, A2 with its own output signals Al ', A2' - which the microcontroller MC13 for deciding which of the two other microcontroller MCIl, MC12 incorrectly generated generates - does not match. That microcontroller in which a mismatch occurs is then turned off.
  • output signals Bl, B2 are conceivable as shown in the figure, which are indeed monitored by the third microprocessor MC13, but are not output via an OR switch as the signals Al, A2.
  • FIG. 5 shows as an example a bus system with preferably a FlexRay architecture for an entire motor vehicle with a bus system SYS according to the invention.
  • the system consists of 2 bus nodes BK1, BK2.
  • the bus nodes are also referred to as domain computers or master basic modules.
  • the first bus node BK1 which has the three microprocessors MCI1-MC13, is located in a front area BEI of the vehicle.
  • a suitably adapted central driving dynamics control unit of a passenger car can be used as a basis for the front bus node BK1.
  • a second bus node BK2 In the rear part of the vehicle there is a second bus node BK2 with two microprocessors MC21, MC22, which in the manner already described above is connected to the front bus node BK1 via the redundant bus lines FR1, FR1 '.
  • the bus node BK1 according to FIG. 5 is again shown simplified, but may have the monitoring structure according to FIG.
  • the bus node BK1 communicates to the outside with a slave control unit SLl, for example via a LIN bus.
  • An actuator AKl is redundantly connected via the OR circuit.
  • the buses FRI, FRI ' communicate with other control devices, such as the domain MOT (eg motor) and with a combination display instrument KO.
  • the domain MOT eg motor
  • BK2 slave SL3, sensors SE3, SE4, actuator AK2
  • a domain computer for information / communication INFO / COMM is connected to the bus node to the bus FRI '.
  • This domain computer INFO / KOMM is additionally with a known digital MOST ring bus MOST, which is usually designed in the form of optical fibers connected.
  • the further signal transfer then takes place via the bus FRl 'or FRl.
  • control units / sensors ana which have analog signals.
  • these can be connected directly to the Info / Communication Don ⁇ änen INFO / KOMM directly or with a shorter line length to the bus node BK2.
  • controller FMO of the MOST ring e.g. a CD player is shown.
  • the front bus node (domain computer) BK1 and the rear bus node BK2 are briefly mentioned by way of example.
  • the front domain computer BKl is, for example, responsible for EPS, light, windscreen wiper, window heating damping, sensors for ABS and level control, door functions, locking systems, driving permissions, tire pressure monitoring and forms a central gateway.
  • the rear domain computer BK2 is also for light, locking systems, sensors for ABS, level control and tank, camera (reversing), windscreen wipers, seat heating, damping, engines for tank, air pump, rear blind, for solenoid valves for air suspension and for a parking brake of the motor vehicle responsible. This list is in no way complete and merely serves as an example for a better understanding.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Small-Scale Networks (AREA)

Abstract

L'invention concerne un système de bus (SYS) pour véhicules automobiles, comprenant au moins deux noeuds de bus (BK1, BK2) situés dans des zones (BE1, BE2) du véhicule automobile distantes l'une de l'autre, ces noeuds de bus (BK1, BK2) étant interconnectés à des fins de communication. Chacun des noeuds de bus (BK1, BK2) présente deux microprocesseurs (MC11, MC12; MC21, MC22) redondants par l'intermédiaire desquels des signaux peuvent entrer et/ou sortir. Les noeuds de bus (BK1, BK2) interconnectés sont reliés entre eux par l'intermédiaire de deux lignes à grande vitesse (FR1, FR1') redondantes respectives, chaque microprocesseur (MC11, MC12) d'un noeud de bus (BK1) étant relié par l'intermédiaire d'une telle ligne à grande vitesse (FR1, FR1') à un microprocesseur (MC21, MC22) correspondant d'un noeud de bus (BK2) relié à celui-ci. Selon l'invention, au moins un des noeuds de bus (BK1) présente en outre au moins un troisième microprocesseur (MC13) qui est relié aux deux autres microprocesseurs (MC11, MC12) de son noeud de bus (BK1) et qui est conçu pour contrôler les deux autres microprocesseurs (MC11, MC12) quant à leur bon fonctionnement.
PCT/AT2009/000049 2008-02-11 2009-02-11 Système de bus redondant Ceased WO2009100472A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
ATA220/2008 2008-02-11
AT2202008A AT506439B1 (de) 2008-02-11 2008-02-11 Redundantes bussystem

Publications (1)

Publication Number Publication Date
WO2009100472A1 true WO2009100472A1 (fr) 2009-08-20

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PCT/AT2009/000049 Ceased WO2009100472A1 (fr) 2008-02-11 2009-02-11 Système de bus redondant

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AT (1) AT506439B1 (fr)
WO (1) WO2009100472A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2719599A4 (fr) * 2011-06-07 2017-05-10 Daesung Electric Co., Ltd. Dispositif et procédé de détection d'erreur dans un système à double contrôleur

Citations (4)

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Publication number Priority date Publication date Assignee Title
FR2591777A1 (fr) * 1985-12-13 1987-06-19 Cimsa Sintra Reseau informatise de grande securite de fonctionnement et procede de commande utilisant un tel reseau
JPH053483A (ja) * 1991-02-27 1993-01-08 Mazda Motor Corp 多重伝送装置
US5901281A (en) * 1991-01-25 1999-05-04 Hitachi, Ltd. Processing unit for a computer and a computer system incorporating such a processing unit
US20060253726A1 (en) * 2005-05-06 2006-11-09 Vikas Kukshya Fault-tolerant architecture for a distributed control system

Family Cites Families (2)

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Publication number Priority date Publication date Assignee Title
JPH07131865A (ja) * 1993-11-08 1995-05-19 Mazda Motor Corp 多重伝送装置
SE9603458L (sv) * 1996-09-23 1997-12-01 Ericsson Telefon Ab L M Förfarande och anordning för att detektera fel i ett nätverk

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Publication number Priority date Publication date Assignee Title
FR2591777A1 (fr) * 1985-12-13 1987-06-19 Cimsa Sintra Reseau informatise de grande securite de fonctionnement et procede de commande utilisant un tel reseau
US5901281A (en) * 1991-01-25 1999-05-04 Hitachi, Ltd. Processing unit for a computer and a computer system incorporating such a processing unit
JPH053483A (ja) * 1991-02-27 1993-01-08 Mazda Motor Corp 多重伝送装置
US20060253726A1 (en) * 2005-05-06 2006-11-09 Vikas Kukshya Fault-tolerant architecture for a distributed control system

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RITER R ED - INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS: "MODELING AND TESTING A CRITICAL FAULT-TOLERANT MULTI-PROCESS SYSTEM", 25TH. INTERNATIONAL SYMPOSIUM ON FAULT TOLERANT COMPUTING. DIGEST OF PAPERS. PASADENA, JUNE 27 - 30, 1995; [INTERNATIONAL SYMPOSIUM ON FAULT TOLERANT COMPUTING], LOS ALAMITOS, IEEE COMP. SOC. PRESS, US, vol. SYMP. 25, 27 June 1995 (1995-06-27), pages 516 - 521, XP000597823, ISBN: 978-0-7803-2965-2 *
SHRIVASTAVA S K ET AL: "PRINCIPAL FEATURES OF THE VOLTAN FAMILY OF RELIABLE NODE ARCHITECTURES FOR DISTRIBUTED SYSTEMS", IEEE TRANSACTIONS ON COMPUTERS, IEEE SERVICE CENTER, LOS ALAMITOS, CA, US, vol. 41, no. 5, 1 May 1992 (1992-05-01), pages 542 - 549, XP000278184, ISSN: 0018-9340 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2719599A4 (fr) * 2011-06-07 2017-05-10 Daesung Electric Co., Ltd. Dispositif et procédé de détection d'erreur dans un système à double contrôleur

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Publication number Publication date
AT506439A1 (de) 2009-09-15
AT506439B1 (de) 2012-11-15

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