WO2009133380A3 - Diviseur de fréquence fractionnaire n - Google Patents

Diviseur de fréquence fractionnaire n Download PDF

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Publication number
WO2009133380A3
WO2009133380A3 PCT/GB2009/050282 GB2009050282W WO2009133380A3 WO 2009133380 A3 WO2009133380 A3 WO 2009133380A3 GB 2009050282 W GB2009050282 W GB 2009050282W WO 2009133380 A3 WO2009133380 A3 WO 2009133380A3
Authority
WO
WIPO (PCT)
Prior art keywords
clock signal
signal
divider
equal
frequency divider
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/GB2009/050282
Other languages
English (en)
Other versions
WO2009133380A2 (fr
Inventor
Sebastian Loeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Elonics Ltd
Original Assignee
Elonics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elonics Ltd filed Critical Elonics Ltd
Priority to US12/989,704 priority Critical patent/US20110163784A1/en
Priority to EP09738410A priority patent/EP2272166A2/fr
Publication of WO2009133380A2 publication Critical patent/WO2009133380A2/fr
Publication of WO2009133380A3 publication Critical patent/WO2009133380A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/68—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a base which is a non-integer
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

L’invention concerne un diviseur de fréquence fractionnaire n qui résout le problème de la présence de zones dites mortes dans les circuits diviseurs de fréquence connus. n cellules de diviseur sont connectées de manière à former un compteur asynchrone (n étant un nombre entier supérieur ou égal à 2) et un multiplexeur de sortie reçoit un signal d’horloge et un signal d’horloge inversé de la part de la n-ième cellule de diviseur. Un circuit de polarité génère un signal de polarité qui synchronise le multiplexeur de sortie de manière à combiner de manière commandable le signal d’horloge et le signal d’horloge inversé afin de produire un signal de sortie. Un signal de basculement fait basculer entre une première et une deuxième configuration de division par un nombre entier de manière à réaliser des sorties divisionnaires fractionnaires entre elles. Avec n cellules de diviseur 2/3, le rapport de division peut ainsi prendre toute valeur fractionnaire qui satisfait à l’inégalité suivante : 2n-1 < rapport de division < 2n+1 - 1.
PCT/GB2009/050282 2008-04-29 2009-03-25 Diviseur de fréquence fractionnaire n Ceased WO2009133380A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/989,704 US20110163784A1 (en) 2008-04-29 2009-03-25 Fractional frequency divider
EP09738410A EP2272166A2 (fr) 2008-04-29 2009-03-25 Diviseur de fréquence fractionnaire n

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0807749.7A GB0807749D0 (en) 2008-04-29 2008-04-29 Fractional-n frequency divider
GB0807749.7 2008-04-29

Publications (2)

Publication Number Publication Date
WO2009133380A2 WO2009133380A2 (fr) 2009-11-05
WO2009133380A3 true WO2009133380A3 (fr) 2010-05-27

Family

ID=39522720

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2009/050282 Ceased WO2009133380A2 (fr) 2008-04-29 2009-03-25 Diviseur de fréquence fractionnaire n

Country Status (4)

Country Link
US (1) US20110163784A1 (fr)
EP (1) EP2272166A2 (fr)
GB (1) GB0807749D0 (fr)
WO (1) WO2009133380A2 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015149516A (ja) * 2014-02-04 2015-08-20 ソニー株式会社 分周回路および位相同期回路
US10298382B2 (en) 2016-06-23 2019-05-21 Omnivision Technologies, Inc. 1-16 and 1.5-7.5 frequency divider for clock synthesizer in digital systems
US10700669B2 (en) 2018-06-19 2020-06-30 Aura Semiconductor Pvt. Ltd Avoiding very low duty cycles in a divided clock generated by a frequency divider
US10742220B1 (en) * 2019-04-30 2020-08-11 Synopsys, Inc. Method and apparatus for operating programmable clock divider using reset paths
CN113765515B (zh) * 2020-06-03 2024-04-19 瑞昱半导体股份有限公司 开环分数分频器
US11955982B2 (en) * 2022-06-29 2024-04-09 Ati Technologies Ulc Granular clock frequency division using dithering mechanism
CN116647233B (zh) * 2023-05-18 2024-04-02 成都电科星拓科技有限公司 一种降低不同分频比相位差的多模分频器、锁相环及芯片

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030063699A1 (en) * 2001-09-28 2003-04-03 Weldon Paul J. Generating non-integer clock division
US20070147571A1 (en) * 2005-12-27 2007-06-28 Memetics Technology Co., Ltd. Configuration and controlling method of Fractional-N PLL having fractional frequency divider

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030063699A1 (en) * 2001-09-28 2003-04-03 Weldon Paul J. Generating non-integer clock division
US20070147571A1 (en) * 2005-12-27 2007-06-28 Memetics Technology Co., Ltd. Configuration and controlling method of Fractional-N PLL having fractional frequency divider

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
CICERO S VAUCHER ET AL: "A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-m CMOS Technology", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 35, no. 7, 1 July 2000 (2000-07-01), XP011061290, ISSN: 0018-9200 *
ROGERS, J. W. M. ET AL: "A Multiband Delta Sigma Fractional-N Frequency Synthesizer for a MIMO WLAN Transceiver RFIC", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 40, no. 3, 1 March 2005 (2005-03-01), pages 678 - 689, XP011128275, ISSN: 0018-9200 *

Also Published As

Publication number Publication date
WO2009133380A2 (fr) 2009-11-05
GB0807749D0 (en) 2008-06-04
EP2272166A2 (fr) 2011-01-12
US20110163784A1 (en) 2011-07-07

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